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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/sound/soc/codecs/wm8962.c
....@@ -1,14 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * wm8962.c  --  WM8962 ALSA SoC Audio driver
34  *
45  * Copyright 2010-2 Wolfson Microelectronics plc
56  *
67  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7
- *
8
- *
9
- * This program is free software; you can redistribute it and/or modify
10
- * it under the terms of the GNU General Public License version 2 as
11
- * published by the Free Software Foundation.
128  */
139 
1410 #include <linux/module.h>
....@@ -122,7 +118,7 @@
122118 	{ 5, 0x0018 },   /* R5     - ADC & DAC Control 1 */
123119 	{ 6, 0x2008 },   /* R6     - ADC & DAC Control 2 */
124120 	{ 7, 0x000A },   /* R7     - Audio Interface 0 */
125
-
121
+	{ 8, 0x01E4 },   /* R8     - Clocking2 */
126122 	{ 9, 0x0300 },   /* R9     - Audio Interface 1 */
127123 	{ 10, 0x00C0 },  /* R10    - Left DAC volume */
128124 	{ 11, 0x00C0 },  /* R11    - Right DAC volume */
....@@ -792,7 +788,6 @@
792788 {
793789 	switch (reg) {
794790 	case WM8962_CLOCKING1:
795
-	case WM8962_CLOCKING2:
796791 	case WM8962_SOFTWARE_RESET:
797792 	case WM8962_THERMAL_SHUTDOWN_STATUS:
798793 	case WM8962_ADDITIONAL_CONTROL_4:
....@@ -961,7 +956,6 @@
961956 	case WM8962_EQ39:
962957 	case WM8962_EQ40:
963958 	case WM8962_EQ41:
964
-	case WM8962_GPIO_BASE:
965959 	case WM8962_GPIO_2:
966960 	case WM8962_GPIO_3:
967961 	case WM8962_GPIO_5:
....@@ -1485,9 +1479,9 @@
14851479 
14861480 static int wm8962_dsp2_set_enable(struct snd_soc_component *component, u16 val)
14871481 {
1488
-	u16 adcl = snd_soc_component_read32(component, WM8962_LEFT_ADC_VOLUME);
1489
-	u16 adcr = snd_soc_component_read32(component, WM8962_RIGHT_ADC_VOLUME);
1490
-	u16 dac = snd_soc_component_read32(component, WM8962_ADC_DAC_CONTROL_1);
1482
+	u16 adcl = snd_soc_component_read(component, WM8962_LEFT_ADC_VOLUME);
1483
+	u16 adcr = snd_soc_component_read(component, WM8962_RIGHT_ADC_VOLUME);
1484
+	u16 dac = snd_soc_component_read(component, WM8962_ADC_DAC_CONTROL_1);
14911485 
14921486 	/* Mute the ADCs and DACs */
14931487 	snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, 0);
....@@ -1566,7 +1560,7 @@
15661560 	struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
15671561 	int old = wm8962->dsp2_ena;
15681562 	int ret = 0;
1569
-	int dsp2_running = snd_soc_component_read32(component, WM8962_DSP2_POWER_MANAGEMENT) &
1563
+	int dsp2_running = snd_soc_component_read(component, WM8962_DSP2_POWER_MANAGEMENT) &
15701564 		WM8962_DSP2_ENA;
15711565 
15721566 	mutex_lock(&wm8962->dsp2_ena_lock);
....@@ -1609,17 +1603,17 @@
16091603 		return 0;
16101604 
16111605 	/* If the left PGA is enabled hit that VU bit... */
1612
-	ret = snd_soc_component_read32(component, WM8962_PWR_MGMT_2);
1606
+	ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
16131607 	if (ret & WM8962_HPOUTL_PGA_ENA) {
16141608 		snd_soc_component_write(component, WM8962_HPOUTL_VOLUME,
1615
-			      snd_soc_component_read32(component, WM8962_HPOUTL_VOLUME));
1609
+			      snd_soc_component_read(component, WM8962_HPOUTL_VOLUME));
16161610 		return 1;
16171611 	}
16181612 
16191613 	/* ...otherwise the right.  The VU is stereo. */
16201614 	if (ret & WM8962_HPOUTR_PGA_ENA)
16211615 		snd_soc_component_write(component, WM8962_HPOUTR_VOLUME,
1622
-			      snd_soc_component_read32(component, WM8962_HPOUTR_VOLUME));
1616
+			      snd_soc_component_read(component, WM8962_HPOUTR_VOLUME));
16231617 
16241618 	return 1;
16251619 }
....@@ -1639,17 +1633,17 @@
16391633 		return 0;
16401634 
16411635 	/* If the left PGA is enabled hit that VU bit... */
1642
-	ret = snd_soc_component_read32(component, WM8962_PWR_MGMT_2);
1636
+	ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
16431637 	if (ret & WM8962_SPKOUTL_PGA_ENA) {
16441638 		snd_soc_component_write(component, WM8962_SPKOUTL_VOLUME,
1645
-			      snd_soc_component_read32(component, WM8962_SPKOUTL_VOLUME));
1639
+			      snd_soc_component_read(component, WM8962_SPKOUTL_VOLUME));
16461640 		return 1;
16471641 	}
16481642 
16491643 	/* ...otherwise the right.  The VU is stereo. */
16501644 	if (ret & WM8962_SPKOUTR_PGA_ENA)
16511645 		snd_soc_component_write(component, WM8962_SPKOUTR_VOLUME,
1652
-			      snd_soc_component_read32(component, WM8962_SPKOUTR_VOLUME));
1646
+			      snd_soc_component_read(component, WM8962_SPKOUTR_VOLUME));
16531647 
16541648 	return 1;
16551649 }
....@@ -1708,6 +1702,8 @@
17081702 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
17091703 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
17101704 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1705
+SOC_SINGLE("DAC Monomix Switch", WM8962_DAC_DSP_MIXING_1, WM8962_DAC_MONOMIX_SHIFT, 1, 0),
1706
+SOC_SINGLE("ADC Monomix Switch", WM8962_THREED1, WM8962_ADC_MONOMIX_SHIFT, 1, 0),
17111707 
17121708 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
17131709 	   5, 1, 0),
....@@ -1844,6 +1840,49 @@
18441840 	       4, 1, 0, inmix_tlv),
18451841 };
18461842 
1843
+static int tp_event(struct snd_soc_dapm_widget *w,
1844
+		    struct snd_kcontrol *kcontrol, int event)
1845
+{
1846
+	int ret, reg, val, mask;
1847
+	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1848
+
1849
+	ret = pm_runtime_resume_and_get(component->dev);
1850
+	if (ret < 0) {
1851
+		dev_err(component->dev, "Failed to resume device: %d\n", ret);
1852
+		return ret;
1853
+	}
1854
+
1855
+	reg = WM8962_ADDITIONAL_CONTROL_4;
1856
+
1857
+	if (!strcmp(w->name, "TEMP_HP")) {
1858
+		mask = WM8962_TEMP_ENA_HP_MASK;
1859
+		val = WM8962_TEMP_ENA_HP;
1860
+	} else if (!strcmp(w->name, "TEMP_SPK")) {
1861
+		mask = WM8962_TEMP_ENA_SPK_MASK;
1862
+		val = WM8962_TEMP_ENA_SPK;
1863
+	} else {
1864
+		pm_runtime_put(component->dev);
1865
+		return -EINVAL;
1866
+	}
1867
+
1868
+	switch (event) {
1869
+	case SND_SOC_DAPM_POST_PMD:
1870
+		val = 0;
1871
+		fallthrough;
1872
+	case SND_SOC_DAPM_POST_PMU:
1873
+		ret = snd_soc_component_update_bits(component, reg, mask, val);
1874
+		break;
1875
+	default:
1876
+		WARN(1, "Invalid event %d\n", event);
1877
+		pm_runtime_put(component->dev);
1878
+		return -EINVAL;
1879
+	}
1880
+
1881
+	pm_runtime_put(component->dev);
1882
+
1883
+	return 0;
1884
+}
1885
+
18471886 static int cp_event(struct snd_soc_dapm_widget *w,
18481887 		    struct snd_kcontrol *kcontrol, int event)
18491888 {
....@@ -1893,7 +1932,7 @@
18931932 		timeout = 0;
18941933 		do {
18951934 			msleep(1);
1896
-			reg = snd_soc_component_read32(component, WM8962_DC_SERVO_6);
1935
+			reg = snd_soc_component_read(component, WM8962_DC_SERVO_6);
18971936 			if (reg < 0) {
18981937 				dev_err(component->dev,
18991938 					"Failed to read DCS status: %d\n",
....@@ -1980,7 +2019,8 @@
19802019 
19812020 	switch (event) {
19822021 	case SND_SOC_DAPM_POST_PMU:
1983
-		return snd_soc_component_write(component, reg, snd_soc_component_read32(component, reg));
2022
+		return snd_soc_component_write(component, reg,
2023
+			snd_soc_component_read(component, reg));
19842024 	default:
19852025 		WARN(1, "Invalid event %d\n", event);
19862026 		return -EINVAL;
....@@ -2136,8 +2176,10 @@
21362176 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
21372177 		      WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
21382178 		      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2139
-SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2140
-SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
2179
+SND_SOC_DAPM_SUPPLY("TEMP_HP", SND_SOC_NOPM, 0, 0, tp_event,
2180
+		SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2181
+SND_SOC_DAPM_SUPPLY("TEMP_SPK", SND_SOC_NOPM, 0, 0, tp_event,
2182
+		SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
21412183 
21422184 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
21432185 		   inpgal, ARRAY_SIZE(inpgal)),
....@@ -2447,7 +2489,15 @@
24472489 		snd_soc_component_update_bits(component, WM8962_CLOCKING2,
24482490 				WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
24492491 
2450
-	dspclk = snd_soc_component_read32(component, WM8962_CLOCKING1);
2492
+	/* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
2493
+	 * correct frequency of LRCLK and BCLK. Sometimes the read-only value
2494
+	 * can't be updated timely after enabling SYSCLK. This results in wrong
2495
+	 * calculation values. Delay is introduced here to wait for newest
2496
+	 * value from register. The time of the delay should be at least
2497
+	 * 500~1000us according to test.
2498
+	 */
2499
+	usleep_range(500, 1000);
2500
+	dspclk = snd_soc_component_read(component, WM8962_CLOCKING1);
24512501 
24522502 	if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
24532503 		snd_soc_component_update_bits(component, WM8962_CLOCKING2,
....@@ -2649,7 +2699,7 @@
26492699 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
26502700 	case SND_SOC_DAIFMT_DSP_B:
26512701 		aif0 |= WM8962_LRCLK_INV | 3;
2652
-		/* fall through */
2702
+		fallthrough;
26532703 	case SND_SOC_DAIFMT_DSP_A:
26542704 		aif0 |= 3;
26552705 
....@@ -2885,6 +2935,7 @@
28852935 
28862936 	ret = pm_runtime_get_sync(component->dev);
28872937 	if (ret < 0) {
2938
+		pm_runtime_put_noidle(component->dev);
28882939 		dev_err(component->dev, "Failed to resume device: %d\n", ret);
28892940 		return ret;
28902941 	}
....@@ -2921,7 +2972,7 @@
29212972 	return 0;
29222973 }
29232974 
2924
-static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2975
+static int wm8962_mute(struct snd_soc_dai *dai, int mute, int direction)
29252976 {
29262977 	struct snd_soc_component *component = dai->component;
29272978 	int val, ret;
....@@ -2954,7 +3005,8 @@
29543005 	.hw_params = wm8962_hw_params,
29553006 	.set_sysclk = wm8962_set_dai_sysclk,
29563007 	.set_fmt = wm8962_set_dai_fmt,
2957
-	.digital_mute = wm8962_mute,
3008
+	.mute_stream = wm8962_mute,
3009
+	.no_capture_mute = 1,
29583010 };
29593011 
29603012 static struct snd_soc_dai_driver wm8962_dai = {
....@@ -2987,7 +3039,7 @@
29873039 	int irq_pol = 0;
29883040 	int reg;
29893041 
2990
-	reg = snd_soc_component_read32(component, WM8962_ADDITIONAL_CONTROL_4);
3042
+	reg = snd_soc_component_read(component, WM8962_ADDITIONAL_CONTROL_4);
29913043 
29923044 	if (reg & WM8962_MICDET_STS) {
29933045 		status |= SND_JACK_MICROPHONE;
....@@ -3017,6 +3069,7 @@
30173069 
30183070 	ret = pm_runtime_get_sync(dev);
30193071 	if (ret < 0) {
3072
+		pm_runtime_put_noidle(dev);
30203073 		dev_err(dev, "Failed to resume: %d\n", ret);
30213074 		return IRQ_NONE;
30223075 	}
....@@ -3424,8 +3477,9 @@
34243477 
34253478 	/* This should really be moved into the regulator core */
34263479 	for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3427
-		ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3428
-						  &wm8962->disable_nb[i]);
3480
+		ret = devm_regulator_register_notifier(
3481
+						wm8962->supplies[i].consumer,
3482
+						&wm8962->disable_nb[i]);
34293483 		if (ret != 0) {
34303484 			dev_err(component->dev,
34313485 				"Failed to register regulator notifier: %d\n",
....@@ -3438,8 +3492,14 @@
34383492 	/* Save boards having to disable DMIC when not in use */
34393493 	dmicclk = false;
34403494 	dmicdat = false;
3441
-	for (i = 0; i < WM8962_MAX_GPIO; i++) {
3442
-		switch (snd_soc_component_read32(component, WM8962_GPIO_BASE + i)
3495
+	for (i = 1; i < WM8962_MAX_GPIO; i++) {
3496
+		/*
3497
+		 * Register 515 (WM8962_GPIO_BASE + 3) does not exist,
3498
+		 * so skip its access
3499
+		 */
3500
+		if (i == 3)
3501
+			continue;
3502
+		switch (snd_soc_component_read(component, WM8962_GPIO_BASE + i)
34433503 			& WM8962_GP2_FN_MASK) {
34443504 		case WM8962_GPIO_FN_DMICCLK:
34453505 			dmicclk = true;
....@@ -3467,15 +3527,11 @@
34673527 static void wm8962_remove(struct snd_soc_component *component)
34683528 {
34693529 	struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3470
-	int i;
34713530 
34723531 	cancel_delayed_work_sync(&wm8962->mic_work);
34733532 
34743533 	wm8962_free_gpio(component);
34753534 	wm8962_free_beep(component);
3476
-	for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3477
-		regulator_unregister_notifier(wm8962->supplies[i].consumer,
3478
-					      &wm8962->disable_nb[i]);
34793535 }
34803536 
34813537 static const struct snd_soc_component_driver soc_component_dev_wm8962 = {
....@@ -3757,6 +3813,11 @@
37573813 	if (ret < 0)
37583814 		goto err_pm_runtime;
37593815 
3816
+	regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3817
+			    WM8962_TEMP_ENA_HP_MASK, 0);
3818
+	regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3819
+			    WM8962_TEMP_ENA_SPK_MASK, 0);
3820
+
37603821 	regcache_cache_only(wm8962->regmap, true);
37613822 
37623823 	/* The drivers should power up as needed */
....@@ -3806,8 +3867,8 @@
38063867 	/* SYSCLK defaults to on; make sure it is off so we can safely
38073868 	 * write to registers if the device is declocked.
38083869 	 */
3809
-	regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3810
-			   WM8962_SYSCLK_ENA, 0);
3870
+	regmap_write_bits(wm8962->regmap, WM8962_CLOCKING2,
3871
+			  WM8962_SYSCLK_ENA, 0);
38113872 
38123873 	/* Ensure we have soft control over all registers */
38133874 	regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
....@@ -3861,6 +3922,7 @@
38613922 #endif
38623923 
38633924 static const struct dev_pm_ops wm8962_pm = {
3925
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
38643926 	SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
38653927 };
38663928