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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/sound/soc/codecs/tscs454.c
..
..
@@ -22,7 +22,6 @@
22
22
 
23
23
 #include "tscs454.h"
24
24
 
25
-static const unsigned int PLL_48K_RATE = (48000 * 256);
26
25
 static const unsigned int PLL_44_1K_RATE = (44100 * 256);
27
26
 
28
27
 #define COEFF_SIZE 3
..
..
@@ -354,12 +353,7 @@
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353
 	for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) {
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354
 
356
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 		for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
357
-			ret = snd_soc_component_read(component, r_stat, &val);
358
-			if (ret < 0) {
359
-				dev_err(component->dev,
360
-					"Failed to read stat (%d)\n", ret);
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-				return ret;
362
-			}
356
+			val = snd_soc_component_read(component, r_stat);
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 			if (!val)
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 				break;
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 		}
..
..
@@ -445,12 +439,7 @@
445
439
 	mutex_lock(&tscs454->pll1.lock);
446
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 	mutex_lock(&tscs454->pll2.lock);
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441
 
448
-	ret = snd_soc_component_read(component, R_PLLSTAT, &val);
449
-	if (ret < 0) {
450
-		dev_err(component->dev, "Failed to read PLL status (%d)\n",
451
-				ret);
452
-		goto exit;
453
-	}
442
+	val = snd_soc_component_read(component, R_PLLSTAT);
454
443
 	if (val) { /* PLLs locked */
455
444
 		ret = write_coeff_ram(component, coeff_ram,
456
445
 			r_stat, r_addr, r_wr,
..
..
@@ -2643,13 +2632,10 @@
2643
2632
 	struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2644
2633
 	unsigned int val;
2645
2634
 	int bclk_dai;
2646
-	int ret;
2647
2635
 
2648
2636
 	dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq);
2649
2637
 
2650
-	ret = snd_soc_component_read(component, R_PLLCTL, &val);
2651
-	if (ret < 0)
2652
-		return ret;
2638
+	val = snd_soc_component_read(component, R_PLLCTL);
2653
2639
 
2654
2640
 	bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL;
2655
2641
 	if (bclk_dai != dai->id)
..
..
@@ -3129,18 +3115,17 @@
3129
3115
 	unsigned int width;
3130
3116
 	int ret;
3131
3117
 
3132
-	switch (format) {
3133
-	case SNDRV_PCM_FORMAT_S16_LE:
3118
+	switch (snd_pcm_format_width(format)) {
3119
+	case 16:
3134
3120
 		width = FV_WL_16;
3135
3121
 		break;
3136
-	case SNDRV_PCM_FORMAT_S20_3LE:
3122
+	case 20:
3137
3123
 		width = FV_WL_20;
3138
3124
 		break;
3139
-	case SNDRV_PCM_FORMAT_S24_3LE:
3125
+	case 24:
3140
3126
 		width = FV_WL_24;
3141
3127
 		break;
3142
-	case SNDRV_PCM_FORMAT_S24_LE:
3143
-	case SNDRV_PCM_FORMAT_S32_LE:
3128
+	case 32:
3144
3129
 		width = FV_WL_32;
3145
3130
 		break;
3146
3131
 	default:
..
..
@@ -3205,10 +3190,7 @@
3205
3190
 	}
3206
3191
 
3207
3192
 	if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */
3208
-		ret = snd_soc_component_read(component, R_ISRC, &val);
3209
-		if (ret < 0)
3210
-			goto exit;
3211
-
3193
+		val = snd_soc_component_read(component, R_ISRC);
3212
3194
 		if ((val & FM_ISRC_IBR) == FV_IBR_48)
3213
3195
 			tscs454->internal_rate.pll = &tscs454->pll1;
3214
3196
 		else
..
..
@@ -3338,6 +3320,7 @@
3338
3320
 	.num_dapm_routes = ARRAY_SIZE(tscs454_intercon),
3339
3321
 	.controls =	tscs454_snd_controls,
3340
3322
 	.num_controls = ARRAY_SIZE(tscs454_snd_controls),
3323
+	.endianness = 1,
3341
3324
 };
3342
3325
 
3343
3326
 #define TSCS454_RATES SNDRV_PCM_RATE_8000_96000
..
..
@@ -3459,7 +3442,7 @@
3459
3442
 	/* Sync pg sel reg with cache */
3460
3443
 	regmap_write(tscs454->regmap, R_PAGESEL, 0x00);
3461
3444
 
3462
-	ret = snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454,
3445
+	ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454,
3463
3446
 			tscs454_dais, ARRAY_SIZE(tscs454_dais));
3464
3447
 	if (ret) {
3465
3448
 		dev_err(&i2c->dev, "Failed to register component (%d)\n", ret);