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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/sound/soc/codecs/rt5682.h
....@@ -1,18 +1,21 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * rt5682.h  --  RT5682/RT5658 ALSA SoC audio driver
34  *
45  * Copyright 2018 Realtek Microelectronics
56  * Author: Bard Liao <bardliao@realtek.com>
6
- *
7
- * This program is free software; you can redistribute it and/or modify
8
- * it under the terms of the GNU General Public License version 2 as
9
- * published by the Free Software Foundation.
107  */
118 
129 #ifndef __RT5682_H__
1310 #define __RT5682_H__
1411 
1512 #include <sound/rt5682.h>
13
+#include <linux/regulator/consumer.h>
14
+#include <linux/clk.h>
15
+#include <linux/clkdev.h>
16
+#include <linux/clk-provider.h>
17
+#include <linux/soundwire/sdw.h>
18
+#include <linux/soundwire/sdw_type.h>
1619 
1720 #define DEVICE_ID 0x6530
1821 
....@@ -180,7 +183,7 @@
180183 #define RT5682_TEST_MODE_CTRL_4			0x0148
181184 #define RT5682_TEST_MODE_CTRL_5			0x0149
182185 #define RT5682_PLL1_INTERNAL			0x0150
183
-#define RT5682_PLL2_INTERNAL			0x0151
186
+#define RT5682_PLL2_INTERNAL			0x0156
184187 #define RT5682_STO_NG2_CTRL_1			0x0160
185188 #define RT5682_STO_NG2_CTRL_2			0x0161
186189 #define RT5682_STO_NG2_CTRL_3			0x0162
....@@ -654,6 +657,8 @@
654657 #define RT5682_DMIC_1_EN_SFT			15
655658 #define RT5682_DMIC_1_DIS			(0x0 << 15)
656659 #define RT5682_DMIC_1_EN			(0x1 << 15)
660
+#define RT5682_FIFO_CLK_DIV_MASK		(0x7 << 12)
661
+#define RT5682_FIFO_CLK_DIV_2			(0x1 << 12)
657662 #define RT5682_DMIC_1_DP_MASK			(0x3 << 4)
658663 #define RT5682_DMIC_1_DP_SFT			4
659664 #define RT5682_DMIC_1_DP_GPIO2			(0x0 << 4)
....@@ -741,7 +746,7 @@
741746 #define RT5682_ADC_OSR_D_24			(0x7 << 12)
742747 #define RT5682_ADC_OSR_D_32			(0x8 << 12)
743748 #define RT5682_ADC_OSR_D_48			(0x9 << 12)
744
-#define RT5682_I2S_M_DIV_MASK			(0xf << 12)
749
+#define RT5682_I2S_M_DIV_MASK			(0xf << 8)
745750 #define RT5682_I2S_M_DIV_SFT			8
746751 #define RT5682_I2S_M_D_1			(0x0 << 8)
747752 #define RT5682_I2S_M_D_2			(0x1 << 8)
....@@ -823,6 +828,12 @@
823828 #define RT5682_TDM_DF_PCM_B			(0x3 << 11)
824829 #define RT5682_TDM_DF_PCM_A_N			(0x6 << 11)
825830 #define RT5682_TDM_DF_PCM_B_N			(0x7 << 11)
831
+#define RT5682_TDM_BCLK_MS1_MASK		(0x3 << 9)
832
+#define RT5682_TDM_BCLK_MS1_SFT			9
833
+#define RT5682_TDM_BCLK_MS1_32			(0x0 << 9)
834
+#define RT5682_TDM_BCLK_MS1_64			(0x1 << 9)
835
+#define RT5682_TDM_BCLK_MS1_128			(0x2 << 9)
836
+#define RT5682_TDM_BCLK_MS1_256			(0x3 << 9)
826837 #define RT5682_TDM_CL_MASK			(0x3 << 4)
827838 #define RT5682_TDM_CL_16			(0x0 << 4)
828839 #define RT5682_TDM_CL_20			(0x1 << 4)
....@@ -838,8 +849,8 @@
838849 #define RT5682_TDM_M_LP_INV			(0x1 << 1)
839850 #define RT5682_TDM_MS_MASK			(0x1 << 0)
840851 #define RT5682_TDM_MS_SFT			0
841
-#define RT5682_TDM_MS_M				(0x0 << 0)
842
-#define RT5682_TDM_MS_S				(0x1 << 0)
852
+#define RT5682_TDM_MS_S				(0x0 << 0)
853
+#define RT5682_TDM_MS_M				(0x1 << 0)
843854 
844855 /* Global Clock Control (0x0080) */
845856 #define RT5682_SCLK_SRC_MASK			(0x7 << 13)
....@@ -1052,6 +1063,32 @@
10521063 #define RT5682_PWR_CLK1M_PD			(0x0 << 8)
10531064 #define RT5682_PWR_CLK1M_PU			(0x1 << 8)
10541065 
1066
+/* PLL2 M/N/K Code Control 1 (0x009b) */
1067
+#define RT5682_PLL2F_K_MASK			(0x1f << 8)
1068
+#define RT5682_PLL2F_K_SFT			8
1069
+#define RT5682_PLL2B_K_MASK			(0xf << 4)
1070
+#define RT5682_PLL2B_K_SFT			4
1071
+#define RT5682_PLL2B_M_MASK			(0xf << 0)
1072
+
1073
+/* PLL2 M/N/K Code Control 2 (0x009c) */
1074
+#define RT5682_PLL2F_M_MASK			(0x3f << 8)
1075
+#define RT5682_PLL2F_M_SFT			8
1076
+#define RT5682_PLL2B_N_MASK			(0x3f << 0)
1077
+
1078
+/* PLL2 M/N/K Code Control 2 (0x009d) */
1079
+#define RT5682_PLL2F_N_MASK			(0x7f << 8)
1080
+#define RT5682_PLL2F_N_SFT			8
1081
+
1082
+/* PLL2 M/N/K Code Control 2 (0x009e) */
1083
+#define RT5682_PLL2B_SEL_PS_MASK		(0x1 << 13)
1084
+#define RT5682_PLL2B_SEL_PS_SFT			13
1085
+#define RT5682_PLL2B_PS_BYP_MASK		(0x1 << 12)
1086
+#define RT5682_PLL2B_PS_BYP_SFT			12
1087
+#define RT5682_PLL2B_M_BP_MASK			(0x1 << 11)
1088
+#define RT5682_PLL2B_M_BP_SFT			11
1089
+#define RT5682_PLL2F_M_BP_MASK			(0x1 << 7)
1090
+#define RT5682_PLL2F_M_BP_SFT			7
1091
+
10551092 /* RC Clock Control (0x009f) */
10561093 #define RT5682_POW_IRQ				(0x1 << 15)
10571094 #define RT5682_POW_JDH				(0x1 << 14)
....@@ -1094,11 +1131,17 @@
10941131 #define RT5682_JD1_POL_MASK			(0x1 << 13)
10951132 #define RT5682_JD1_POL_NOR			(0x0 << 13)
10961133 #define RT5682_JD1_POL_INV			(0x1 << 13)
1134
+#define RT5682_JD1_IRQ_MASK			(0x1 << 10)
1135
+#define RT5682_JD1_IRQ_LEV			(0x0 << 10)
1136
+#define RT5682_JD1_IRQ_PUL			(0x1 << 10)
10971137 
10981138 /* IRQ Control 3 (0x00b8) */
10991139 #define RT5682_IL_IRQ_MASK			(0x1 << 7)
11001140 #define RT5682_IL_IRQ_DIS			(0x0 << 7)
11011141 #define RT5682_IL_IRQ_EN			(0x1 << 7)
1142
+#define RT5682_IL_IRQ_TYPE_MASK			(0x1 << 4)
1143
+#define RT5682_IL_IRQ_LEV			(0x0 << 4)
1144
+#define RT5682_IL_IRQ_PUL			(0x1 << 4)
11021145 
11031146 /* GPIO Control 1 (0x00c0) */
11041147 #define RT5682_GP1_PIN_MASK			(0x3 << 14)
....@@ -1214,6 +1257,20 @@
12141257 #define RT5682_JDH_NO_PLUG			(0x1 << 4)
12151258 #define RT5682_JDH_PLUG				(0x0 << 4)
12161259 
1260
+/* Bias current control 8 (0x0111) */
1261
+#define RT5682_HPA_CP_BIAS_CTRL_MASK			(0x3 << 2)
1262
+#define RT5682_HPA_CP_BIAS_2UA			(0x0 << 2)
1263
+#define RT5682_HPA_CP_BIAS_3UA			(0x1 << 2)
1264
+#define RT5682_HPA_CP_BIAS_4UA			(0x2 << 2)
1265
+#define RT5682_HPA_CP_BIAS_6UA			(0x3 << 2)
1266
+
1267
+/* Charge Pump Internal Register1 (0x0125) */
1268
+#define RT5682_CP_CLK_HP_MASK			(0x3 << 4)
1269
+#define RT5682_CP_CLK_HP_100KHZ			(0x0 << 4)
1270
+#define RT5682_CP_CLK_HP_200KHZ			(0x1 << 4)
1271
+#define RT5682_CP_CLK_HP_300KHZ			(0x2 << 4)
1272
+#define RT5682_CP_CLK_HP_600KHZ			(0x3 << 4)
1273
+
12171274 /* Chopper and Clock control for DAC (0x013a)*/
12181275 #define RT5682_CKXEN_DAC1_MASK			(0x1 << 13)
12191276 #define RT5682_CKXEN_DAC1_SFT			13
....@@ -1284,6 +1341,13 @@
12841341 #define RT5682_SAR_SOUR_BTN			(0x3f)
12851342 #define RT5682_SAR_SOUR_TYPE			(0x0)
12861343 
1344
+/* soundwire timeout */
1345
+#define RT5682_PROBE_TIMEOUT			2000
1346
+
1347
+
1348
+#define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1349
+#define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1350
+		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
12871351 
12881352 /* System Clock Source */
12891353 enum {
....@@ -1298,11 +1362,19 @@
12981362 	RT5682_PLL1_S_MCLK,
12991363 	RT5682_PLL1_S_BCLK1,
13001364 	RT5682_PLL1_S_RCCLK,
1365
+	RT5682_PLL2_S_MCLK,
1366
+};
1367
+
1368
+enum {
1369
+	RT5682_PLL1,
1370
+	RT5682_PLL2,
1371
+	RT5682_PLLS,
13011372 };
13021373 
13031374 enum {
13041375 	RT5682_AIF1,
13051376 	RT5682_AIF2,
1377
+	RT5682_SDW,
13061378 	RT5682_AIFS
13071379 };
13081380 
....@@ -1318,7 +1390,66 @@
13181390 	RT5682_CLK_SEL_I2S2_ASRC,
13191391 };
13201392 
1393
+#define RT5682_NUM_SUPPLIES 3
1394
+
1395
+struct rt5682_priv {
1396
+	struct snd_soc_component *component;
1397
+	struct rt5682_platform_data pdata;
1398
+	struct regmap *regmap;
1399
+	struct regmap *sdw_regmap;
1400
+	struct snd_soc_jack *hs_jack;
1401
+	struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
1402
+	struct delayed_work jack_detect_work;
1403
+	struct delayed_work jd_check_work;
1404
+	struct mutex calibrate_mutex;
1405
+	struct sdw_slave *slave;
1406
+	enum sdw_slave_status status;
1407
+	struct sdw_bus_params params;
1408
+	bool hw_init;
1409
+	bool first_hw_init;
1410
+	bool is_sdw;
1411
+
1412
+#ifdef CONFIG_COMMON_CLK
1413
+	struct clk_hw dai_clks_hw[RT5682_DAI_NUM_CLKS];
1414
+	struct clk *mclk;
1415
+#endif
1416
+
1417
+	int sysclk;
1418
+	int sysclk_src;
1419
+	int lrck[RT5682_AIFS];
1420
+	int bclk[RT5682_AIFS];
1421
+	int master[RT5682_AIFS];
1422
+
1423
+	int pll_src[RT5682_PLLS];
1424
+	int pll_in[RT5682_PLLS];
1425
+	int pll_out[RT5682_PLLS];
1426
+
1427
+	int jack_type;
1428
+};
1429
+
1430
+extern const char *rt5682_supply_names[RT5682_NUM_SUPPLIES];
1431
+
13211432 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
13221433 		unsigned int filter_mask, unsigned int clk_src);
13231434 
1435
+void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev);
1436
+
1437
+int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert);
1438
+void rt5682_jack_detect_handler(struct work_struct *work);
1439
+
1440
+bool rt5682_volatile_register(struct device *dev, unsigned int reg);
1441
+bool rt5682_readable_register(struct device *dev, unsigned int reg);
1442
+
1443
+int rt5682_register_component(struct device *dev);
1444
+void rt5682_calibrate(struct rt5682_priv *rt5682);
1445
+void rt5682_reset(struct rt5682_priv *rt5682);
1446
+int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev);
1447
+
1448
+#define RT5682_REG_NUM 318
1449
+extern const struct reg_default rt5682_reg[RT5682_REG_NUM];
1450
+
1451
+extern const struct snd_soc_dai_ops rt5682_aif1_dai_ops;
1452
+extern const struct snd_soc_dai_ops rt5682_aif2_dai_ops;
1453
+extern const struct snd_soc_component_driver rt5682_soc_component_dev;
1454
+
13241455 #endif /* __RT5682_H__ */