~hc/RK356X_SDK_RELEASE.git

..	..	@@ -2,6 +2,7 @@
2	2	// Copyright (c) 2017, Maxim Integrated
3	3
4	4	#include <linux/acpi.h>
	5	+#include <linux/delay.h>
5	6	#include <linux/i2c.h>
6	7	#include <linux/module.h>
7	8	#include <linux/regmap.h>
..	..	@@ -11,385 +12,10 @@
11	12	#include <sound/pcm_params.h>
12	13	#include <sound/soc.h>
13	14	#include <linux/gpio.h>
	15	+#include <linux/of.h>
14	16	#include <linux/of_gpio.h>
15	17	#include <sound/tlv.h>
16	18	#include "max98373.h"
17		-
18		-static struct reg_default max98373_reg[] = {
19		- {MAX98373_R2000_SW_RESET, 0x00},
20		- {MAX98373_R2001_INT_RAW1, 0x00},
21		- {MAX98373_R2002_INT_RAW2, 0x00},
22		- {MAX98373_R2003_INT_RAW3, 0x00},
23		- {MAX98373_R2004_INT_STATE1, 0x00},
24		- {MAX98373_R2005_INT_STATE2, 0x00},
25		- {MAX98373_R2006_INT_STATE3, 0x00},
26		- {MAX98373_R2007_INT_FLAG1, 0x00},
27		- {MAX98373_R2008_INT_FLAG2, 0x00},
28		- {MAX98373_R2009_INT_FLAG3, 0x00},
29		- {MAX98373_R200A_INT_EN1, 0x00},
30		- {MAX98373_R200B_INT_EN2, 0x00},
31		- {MAX98373_R200C_INT_EN3, 0x00},
32		- {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
33		- {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
34		- {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
35		- {MAX98373_R2010_IRQ_CTRL, 0x00},
36		- {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
37		- {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
38		- {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
39		- {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
40		- {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
41		- {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
42		- {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
43		- {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
44		- {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
45		- {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
46		- {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
47		- {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
48		- {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
49		- {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
50		- {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
51		- {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
52		- {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
53		- {MAX98373_R202B_PCM_RX_EN, 0x00},
54		- {MAX98373_R202C_PCM_TX_EN, 0x00},
55		- {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
56		- {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
57		- {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
58		- {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
59		- {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
60		- {MAX98373_R2034_ICC_TX_CNTL, 0x00},
61		- {MAX98373_R2035_ICC_TX_EN, 0x00},
62		- {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
63		- {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
64		- {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
65		- {MAX98373_R203F_AMP_DSP_CFG, 0x02},
66		- {MAX98373_R2040_TONE_GEN_CFG, 0x00},
67		- {MAX98373_R2041_AMP_CFG, 0x03},
68		- {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
69		- {MAX98373_R2043_AMP_EN, 0x00},
70		- {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
71		- {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
72		- {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
73		- {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
74		- {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
75		- {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
76		- {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
77		- {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
78		- {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
79		- {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
80		- {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
81		- {MAX98373_R2097_BDE_L1_THRESH, 0x00},
82		- {MAX98373_R2098_BDE_L2_THRESH, 0x00},
83		- {MAX98373_R2099_BDE_L3_THRESH, 0x00},
84		- {MAX98373_R209A_BDE_L4_THRESH, 0x00},
85		- {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
86		- {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
87		- {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
88		- {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
89		- {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
90		- {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
91		- {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
92		- {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
93		- {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
94		- {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
95		- {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
96		- {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
97		- {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
98		- {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
99		- {MAX98373_R20B5_BDE_EN, 0x00},
100		- {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
101		- {MAX98373_R20D1_DHT_CFG, 0x01},
102		- {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
103		- {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
104		- {MAX98373_R20D4_DHT_EN, 0x00},
105		- {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
106		- {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
107		- {MAX98373_R20E2_LIMITER_EN, 0x00},
108		- {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
109		- {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
110		- {MAX98373_R21FF_REV_ID, 0x42},
111		-};
112		-
113		-static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
114		-{
115		- struct snd_soc_component *component = codec_dai->component;
116		- struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
117		- unsigned int format = 0;
118		- unsigned int invert = 0;
119		-
120		- dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
121		-
122		- switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
123		- case SND_SOC_DAIFMT_NB_NF:
124		- break;
125		- case SND_SOC_DAIFMT_IB_NF:
126		- invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE;
127		- break;
128		- default:
129		- dev_err(component->dev, "DAI invert mode unsupported\n");
130		- return -EINVAL;
131		- }
132		-
133		- regmap_update_bits(max98373->regmap,
134		- MAX98373_R2026_PCM_CLOCK_RATIO,
135		- MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE,
136		- invert);
137		-
138		- /* interface format */
139		- switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
140		- case SND_SOC_DAIFMT_I2S:
141		- format = MAX98373_PCM_FORMAT_I2S;
142		- break;
143		- case SND_SOC_DAIFMT_LEFT_J:
144		- format = MAX98373_PCM_FORMAT_LJ;
145		- break;
146		- case SND_SOC_DAIFMT_DSP_A:
147		- format = MAX98373_PCM_FORMAT_TDM_MODE1;
148		- break;
149		- case SND_SOC_DAIFMT_DSP_B:
150		- format = MAX98373_PCM_FORMAT_TDM_MODE0;
151		- break;
152		- default:
153		- return -EINVAL;
154		- }
155		-
156		- regmap_update_bits(max98373->regmap,
157		- MAX98373_R2024_PCM_DATA_FMT_CFG,
158		- MAX98373_PCM_MODE_CFG_FORMAT_MASK,
159		- format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT);
160		-
161		- return 0;
162		-}
163		-
164		-/* BCLKs per LRCLK */
165		-static const int bclk_sel_table[] = {
166		- 32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
167		-};
168		-
169		-static int max98373_get_bclk_sel(int bclk)
170		-{
171		- int i;
172		- /* match BCLKs per LRCLK */
173		- for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
174		- if (bclk_sel_table[i] == bclk)
175		- return i + 2;
176		- }
177		- return 0;
178		-}
179		-
180		-static int max98373_set_clock(struct snd_soc_component *component,
181		- struct snd_pcm_hw_params *params)
182		-{
183		- struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
184		- /* BCLK/LRCLK ratio calculation */
185		- int blr_clk_ratio = params_channels(params) * max98373->ch_size;
186		- int value;
187		-
188		- if (!max98373->tdm_mode) {
189		- /* BCLK configuration */
190		- value = max98373_get_bclk_sel(blr_clk_ratio);
191		- if (!value) {
192		- dev_err(component->dev, "format unsupported %d\n",
193		- params_format(params));
194		- return -EINVAL;
195		- }
196		-
197		- regmap_update_bits(max98373->regmap,
198		- MAX98373_R2026_PCM_CLOCK_RATIO,
199		- MAX98373_PCM_CLK_SETUP_BSEL_MASK,
200		- value);
201		- }
202		- return 0;
203		-}
204		-
205		-static int max98373_dai_hw_params(struct snd_pcm_substream *substream,
206		- struct snd_pcm_hw_params *params,
207		- struct snd_soc_dai *dai)
208		-{
209		- struct snd_soc_component *component = dai->component;
210		- struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
211		- unsigned int sampling_rate = 0;
212		- unsigned int chan_sz = 0;
213		-
214		- /* pcm mode configuration */
215		- switch (snd_pcm_format_width(params_format(params))) {
216		- case 16:
217		- chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
218		- break;
219		- case 24:
220		- chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
221		- break;
222		- case 32:
223		- chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
224		- break;
225		- default:
226		- dev_err(component->dev, "format unsupported %d\n",
227		- params_format(params));
228		- goto err;
229		- }
230		-
231		- max98373->ch_size = snd_pcm_format_width(params_format(params));
232		-
233		- regmap_update_bits(max98373->regmap,
234		- MAX98373_R2024_PCM_DATA_FMT_CFG,
235		- MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
236		-
237		- dev_dbg(component->dev, "format supported %d",
238		- params_format(params));
239		-
240		- /* sampling rate configuration */
241		- switch (params_rate(params)) {
242		- case 8000:
243		- sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
244		- break;
245		- case 11025:
246		- sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
247		- break;
248		- case 12000:
249		- sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
250		- break;
251		- case 16000:
252		- sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
253		- break;
254		- case 22050:
255		- sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
256		- break;
257		- case 24000:
258		- sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
259		- break;
260		- case 32000:
261		- sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
262		- break;
263		- case 44100:
264		- sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
265		- break;
266		- case 48000:
267		- sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
268		- break;
269		- default:
270		- dev_err(component->dev, "rate %d not supported\n",
271		- params_rate(params));
272		- goto err;
273		- }
274		-
275		- /* set DAI_SR to correct LRCLK frequency */
276		- regmap_update_bits(max98373->regmap,
277		- MAX98373_R2027_PCM_SR_SETUP_1,
278		- MAX98373_PCM_SR_SET1_SR_MASK,
279		- sampling_rate);
280		- regmap_update_bits(max98373->regmap,
281		- MAX98373_R2028_PCM_SR_SETUP_2,
282		- MAX98373_PCM_SR_SET2_SR_MASK,
283		- sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
284		-
285		- /* set sampling rate of IV */
286		- if (max98373->interleave_mode &&
287		- sampling_rate > MAX98373_PCM_SR_SET1_SR_16000)
288		- regmap_update_bits(max98373->regmap,
289		- MAX98373_R2028_PCM_SR_SETUP_2,
290		- MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
291		- sampling_rate - 3);
292		- else
293		- regmap_update_bits(max98373->regmap,
294		- MAX98373_R2028_PCM_SR_SETUP_2,
295		- MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
296		- sampling_rate);
297		-
298		- return max98373_set_clock(component, params);
299		-err:
300		- return -EINVAL;
301		-}
302		-
303		-static int max98373_dai_tdm_slot(struct snd_soc_dai *dai,
304		- unsigned int tx_mask, unsigned int rx_mask,
305		- int slots, int slot_width)
306		-{
307		- struct snd_soc_component *component = dai->component;
308		- struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
309		- int bsel = 0;
310		- unsigned int chan_sz = 0;
311		- unsigned int mask;
312		- int x, slot_found;
313		-
314		- if (!tx_mask && !rx_mask && !slots && !slot_width)
315		- max98373->tdm_mode = false;
316		- else
317		- max98373->tdm_mode = true;
318		-
319		- /* BCLK configuration */
320		- bsel = max98373_get_bclk_sel(slots * slot_width);
321		- if (bsel == 0) {
322		- dev_err(component->dev, "BCLK %d not supported\n",
323		- slots * slot_width);
324		- return -EINVAL;
325		- }
326		-
327		- regmap_update_bits(max98373->regmap,
328		- MAX98373_R2026_PCM_CLOCK_RATIO,
329		- MAX98373_PCM_CLK_SETUP_BSEL_MASK,
330		- bsel);
331		-
332		- /* Channel size configuration */
333		- switch (slot_width) {
334		- case 16:
335		- chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
336		- break;
337		- case 24:
338		- chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
339		- break;
340		- case 32:
341		- chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
342		- break;
343		- default:
344		- dev_err(component->dev, "format unsupported %d\n",
345		- slot_width);
346		- return -EINVAL;
347		- }
348		-
349		- regmap_update_bits(max98373->regmap,
350		- MAX98373_R2024_PCM_DATA_FMT_CFG,
351		- MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
352		-
353		- /* Rx slot configuration */
354		- slot_found = 0;
355		- mask = rx_mask;
356		- for (x = 0 ; x < 16 ; x++, mask >>= 1) {
357		- if (mask & 0x1) {
358		- if (slot_found == 0)
359		- regmap_update_bits(max98373->regmap,
360		- MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
361		- MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x);
362		- else
363		- regmap_write(max98373->regmap,
364		- MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
365		- x);
366		- slot_found++;
367		- if (slot_found > 1)
368		- break;
369		- }
370		- }
371		-
372		- /* Tx slot Hi-Z configuration */
373		- regmap_write(max98373->regmap,
374		- MAX98373_R2020_PCM_TX_HIZ_EN_1,
375		- ~tx_mask & 0xFF);
376		- regmap_write(max98373->regmap,
377		- MAX98373_R2021_PCM_TX_HIZ_EN_2,
378		- (~tx_mask & 0xFF00) >> 8);
379		-
380		- return 0;
381		-}
382		-
383		-#define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
384		-
385		-#define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \| \
386		- SNDRV_PCM_FMTBIT_S24_LE \| SNDRV_PCM_FMTBIT_S32_LE)
387		-
388		-static const struct snd_soc_dai_ops max98373_dai_ops = {
389		- .set_fmt = max98373_dai_set_fmt,
390		- .hw_params = max98373_dai_hw_params,
391		- .set_tdm_slot = max98373_dai_tdm_slot,
392		-};
393	19
394	20	static int max98373_dac_event(struct snd_soc_dapm_widget *w,
395	21	struct snd_kcontrol *kcontrol, int event)
..	..	@@ -402,12 +28,14 @@
402	28	regmap_update_bits(max98373->regmap,
403	29	MAX98373_R20FF_GLOBAL_SHDN,
404	30	MAX98373_GLOBAL_EN_MASK, 1);
	31	+ usleep_range(30000, 31000);
405	32	break;
406	33	case SND_SOC_DAPM_POST_PMD:
407	34	regmap_update_bits(max98373->regmap,
408	35	MAX98373_R20FF_GLOBAL_SHDN,
409	36	MAX98373_GLOBAL_EN_MASK, 0);
410		- max98373->tdm_mode = 0;
	37	+ usleep_range(30000, 31000);
	38	+ max98373->tdm_mode = false;
411	39	break;
412	40	default:
413	41	return 0;
..	..	@@ -454,7 +82,7 @@
454	82	SND_SOC_DAPM_SIGGEN("FBMON"),
455	83	};
456	84
457		-static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, 0, -50, 0);
	85	+static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
458	86	static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
459	87	0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
460	88	9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
..	..	@@ -470,66 +98,20 @@
470	98	0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
471	99	);
472	100	static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
473		- 0, 1, TLV_DB_SCALE_ITEM(-50, -50, 0),
474		- 2, 7, TLV_DB_SCALE_ITEM(-200, -100, 0),
475		- 8, 9, TLV_DB_SCALE_ITEM(-1000, -200, 0),
476		- 10, 11, TLV_DB_SCALE_ITEM(-1500, -300, 0),
477		- 12, 13, TLV_DB_SCALE_ITEM(-2000, -200, 0),
478		- 14, 15, TLV_DB_SCALE_ITEM(-2500, -500, 0),
	101	+ 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
	102	+ 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
	103	+ 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
	104	+ 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
	105	+ 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
	106	+ 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
479	107	);
480	108	static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
481		- 0, 15, TLV_DB_SCALE_ITEM(0, -100, 0),
	109	+ 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
482	110	);
483	111
484	112	static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
485		- 0, 60, TLV_DB_SCALE_ITEM(0, -25, 0),
	113	+ 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0),
486	114	);
487		-
488		-static bool max98373_readable_register(struct device *dev, unsigned int reg)
489		-{
490		- switch (reg) {
491		- case MAX98373_R2000_SW_RESET:
492		- case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3:
493		- case MAX98373_R2010_IRQ_CTRL:
494		- case MAX98373_R2014_THERM_WARN_THRESH
495		- ... MAX98373_R2018_THERM_FOLDBACK_EN:
496		- case MAX98373_R201E_PIN_DRIVE_STRENGTH
497		- ... MAX98373_R2036_SOUNDWIRE_CTRL:
498		- case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
499		- case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
500		- ... MAX98373_R2047_IV_SENSE_ADC_EN:
501		- case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
502		- ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
503		- case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
504		- case MAX98373_R2097_BDE_L1_THRESH
505		- ... MAX98373_R209B_BDE_THRESH_HYST:
506		- case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
507		- case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
508		- case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
509		- case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
510		- case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
511		- ... MAX98373_R20FF_GLOBAL_SHDN:
512		- case MAX98373_R21FF_REV_ID:
513		- return true;
514		- default:
515		- return false;
516		- }
517		-};
518		-
519		-static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
520		-{
521		- switch (reg) {
522		- case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
523		- case MAX98373_R203E_AMP_PATH_GAIN:
524		- case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
525		- case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
526		- case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
527		- case MAX98373_R21FF_REV_ID:
528		- return true;
529		- default:
530		- return false;
531		- }
532		-}
533	115
534	116	static const char * const max98373_output_voltage_lvl_text[] = {
535	117	"5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
..	..	@@ -604,7 +186,7 @@
604	186	SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
605	187	MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
606	188	SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
607		- 0, 0x7F, 0, max98373_digital_tlv),
	189	+ 0, 0x7F, 1, max98373_digital_tlv),
608	190	SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
609	191	MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
610	192	SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
..	..	@@ -616,7 +198,7 @@
616	198	SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
617	199	MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
618	200	SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
619		- MAX98373_DHT_ROT_PNT_SHIFT, 15, 0, max98373_dht_rotation_point_tlv),
	201	+ MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv),
620	202	SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
621	203	MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
622	204	SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
..	..	@@ -653,29 +235,29 @@
653	235	SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
654	236	SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
655	237	SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
656		- 0, 0x3C, 0, max98373_bde_gain_tlv),
	238	+ 0, 0x3C, 1, max98373_bde_gain_tlv),
657	239	SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
658		- 0, 0x3C, 0, max98373_bde_gain_tlv),
	240	+ 0, 0x3C, 1, max98373_bde_gain_tlv),
659	241	SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
660		- 0, 0x3C, 0, max98373_bde_gain_tlv),
	242	+ 0, 0x3C, 1, max98373_bde_gain_tlv),
661	243	SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
662		- 0, 0x3C, 0, max98373_bde_gain_tlv),
	244	+ 0, 0x3C, 1, max98373_bde_gain_tlv),
663	245	SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
664		- 0, 0x3C, 0, max98373_bde_gain_tlv),
	246	+ 0, 0x3C, 1, max98373_bde_gain_tlv),
665	247	SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
666		- 0, 0x3C, 0, max98373_bde_gain_tlv),
	248	+ 0, 0x3C, 1, max98373_bde_gain_tlv),
667	249	SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
668		- 0, 0x3C, 0, max98373_bde_gain_tlv),
	250	+ 0, 0x3C, 1, max98373_bde_gain_tlv),
669	251	SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
670		- 0, 0x3C, 0, max98373_bde_gain_tlv),
	252	+ 0, 0x3C, 1, max98373_bde_gain_tlv),
671	253	SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
672		- 0, 0xF, 0, max98373_limiter_thresh_tlv),
	254	+ 0, 0xF, 1, max98373_limiter_thresh_tlv),
673	255	SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
674		- 0, 0xF, 0, max98373_limiter_thresh_tlv),
	256	+ 0, 0xF, 1, max98373_limiter_thresh_tlv),
675	257	SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
676		- 0, 0xF, 0, max98373_limiter_thresh_tlv),
	258	+ 0, 0xF, 1, max98373_limiter_thresh_tlv),
677	259	SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
678		- 0, 0xF, 0, max98373_limiter_thresh_tlv),
	260	+ 0, 0xF, 1, max98373_limiter_thresh_tlv),
679	261	/* Limiter */
680	262	SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
681	263	MAX98373_LIMITER_EN_SHIFT, 1, 0),
..	..	@@ -702,35 +284,40 @@
702	284	{ "Speaker FB Sense", NULL, "SpkFB Sense" },
703	285	};
704	286
705		-static struct snd_soc_dai_driver max98373_dai[] = {
706		- {
707		- .name = "max98373-aif1",
708		- .playback = {
709		- .stream_name = "HiFi Playback",
710		- .channels_min = 1,
711		- .channels_max = 2,
712		- .rates = MAX98373_RATES,
713		- .formats = MAX98373_FORMATS,
714		- },
715		- .capture = {
716		- .stream_name = "HiFi Capture",
717		- .channels_min = 1,
718		- .channels_max = 2,
719		- .rates = MAX98373_RATES,
720		- .formats = MAX98373_FORMATS,
721		- },
722		- .ops = &max98373_dai_ops,
	287	+void max98373_reset(struct max98373_priv max98373, struct device dev)
	288	+{
	289	+ int ret, reg, count;
	290	+
	291	+ /* Software Reset */
	292	+ ret = regmap_update_bits(max98373->regmap,
	293	+ MAX98373_R2000_SW_RESET,
	294	+ MAX98373_SOFT_RESET,
	295	+ MAX98373_SOFT_RESET);
	296	+ if (ret)
	297	+ dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
	298	+
	299	+ count = 0;
	300	+ while (count < 3) {
	301	+ usleep_range(10000, 11000);
	302	+ /* Software Reset Verification */
	303	+ ret = regmap_read(max98373->regmap,
	304	+ MAX98373_R21FF_REV_ID, &reg);
	305	+ if (!ret) {
	306	+ dev_info(dev, "Reset completed (retry:%d)\n", count);
	307	+ return;
	308	+ }
	309	+ count++;
723	310	}
724		-};
	311	+ dev_err(dev, "Reset failed. (ret:%d)\n", ret);
	312	+}
	313	+EXPORT_SYMBOL_GPL(max98373_reset);
725	314
726	315	static int max98373_probe(struct snd_soc_component *component)
727	316	{
728	317	struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
729	318
730	319	/* Software Reset */
731		- regmap_write(max98373->regmap,
732		- MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
733		- usleep_range(10000, 11000);
	320	+ max98373_reset(max98373, component->dev);
734	321
735	322	/* IV default slot configuration */
736	323	regmap_write(max98373->regmap,
..	..	@@ -746,13 +333,6 @@
746	333	regmap_write(max98373->regmap,
747	334	MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
748	335	0x1);
749		- /* Set inital volume (0dB) */
750		- regmap_write(max98373->regmap,
751		- MAX98373_R203D_AMP_DIG_VOL_CTRL,
752		- 0x00);
753		- regmap_write(max98373->regmap,
754		- MAX98373_R203E_AMP_PATH_GAIN,
755		- 0x00);
756	336	/* Enable DC blocker */
757	337	regmap_write(max98373->regmap,
758	338	MAX98373_R203F_AMP_DSP_CFG,
..	..	@@ -804,33 +384,7 @@
804	384	return 0;
805	385	}
806	386
807		-#ifdef CONFIG_PM_SLEEP
808		-static int max98373_suspend(struct device *dev)
809		-{
810		- struct max98373_priv *max98373 = dev_get_drvdata(dev);
811		-
812		- regcache_cache_only(max98373->regmap, true);
813		- regcache_mark_dirty(max98373->regmap);
814		- return 0;
815		-}
816		-static int max98373_resume(struct device *dev)
817		-{
818		- struct max98373_priv *max98373 = dev_get_drvdata(dev);
819		-
820		- regmap_write(max98373->regmap,
821		- MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
822		- usleep_range(10000, 11000);
823		- regcache_cache_only(max98373->regmap, false);
824		- regcache_sync(max98373->regmap);
825		- return 0;
826		-}
827		-#endif
828		-
829		-static const struct dev_pm_ops max98373_pm = {
830		- SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
831		-};
832		-
833		-static const struct snd_soc_component_driver soc_codec_dev_max98373 = {
	387	+const struct snd_soc_component_driver soc_codec_dev_max98373 = {
834	388	.probe = max98373_probe,
835	389	.controls = max98373_snd_controls,
836	390	.num_controls = ARRAY_SIZE(max98373_snd_controls),
..	..	@@ -838,28 +392,30 @@
838	392	.num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
839	393	.dapm_routes = max98373_audio_map,
840	394	.num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
841		- .idle_bias_on = 1,
842	395	.use_pmdown_time = 1,
843	396	.endianness = 1,
844	397	.non_legacy_dai_naming = 1,
845	398	};
	399	+EXPORT_SYMBOL_GPL(soc_codec_dev_max98373);
846	400
847		-static const struct regmap_config max98373_regmap = {
848		- .reg_bits = 16,
849		- .val_bits = 8,
850		- .max_register = MAX98373_R21FF_REV_ID,
851		- .reg_defaults = max98373_reg,
852		- .num_reg_defaults = ARRAY_SIZE(max98373_reg),
853		- .readable_reg = max98373_readable_register,
854		- .volatile_reg = max98373_volatile_reg,
855		- .cache_type = REGCACHE_RBTREE,
	401	+const struct snd_soc_component_driver soc_codec_dev_max98373_sdw = {
	402	+ .probe = NULL,
	403	+ .controls = max98373_snd_controls,
	404	+ .num_controls = ARRAY_SIZE(max98373_snd_controls),
	405	+ .dapm_widgets = max98373_dapm_widgets,
	406	+ .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
	407	+ .dapm_routes = max98373_audio_map,
	408	+ .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
	409	+ .use_pmdown_time = 1,
	410	+ .endianness = 1,
	411	+ .non_legacy_dai_naming = 1,
856	412	};
	413	+EXPORT_SYMBOL_GPL(soc_codec_dev_max98373_sdw);
857	414
858		-static void max98373_slot_config(struct i2c_client *i2c,
859		- struct max98373_priv *max98373)
	415	+void max98373_slot_config(struct device *dev,
	416	+ struct max98373_priv *max98373)
860	417	{
861	418	int value;
862		- struct device *dev = &i2c->dev;
863	419
864	420	if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
865	421	max98373->v_slot = value & 0xF;
..	..	@@ -870,103 +426,28 @@
870	426	max98373->i_slot = value & 0xF;
871	427	else
872	428	max98373->i_slot = 1;
	429	+ if (dev->of_node) {
	430	+ max98373->reset_gpio = of_get_named_gpio(dev->of_node,
	431	+ "maxim,reset-gpio", 0);
	432	+ if (!gpio_is_valid(max98373->reset_gpio)) {
	433	+ dev_err(dev, "Looking up %s property in node %s failed %d\n",
	434	+ "maxim,reset-gpio", dev->of_node->full_name,
	435	+ max98373->reset_gpio);
	436	+ } else {
	437	+ dev_dbg(dev, "maxim,reset-gpio=%d",
	438	+ max98373->reset_gpio);
	439	+ }
	440	+ } else {
	441	+ /* this makes reset_gpio as invalid */
	442	+ max98373->reset_gpio = -1;
	443	+ }
873	444
874	445	if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
875	446	max98373->spkfb_slot = value & 0xF;
876	447	else
877	448	max98373->spkfb_slot = 2;
878	449	}
879		-
880		-static int max98373_i2c_probe(struct i2c_client *i2c,
881		- const struct i2c_device_id *id)
882		-{
883		-
884		- int ret = 0;
885		- int reg = 0;
886		- struct max98373_priv *max98373 = NULL;
887		-
888		- max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL);
889		-
890		- if (!max98373) {
891		- ret = -ENOMEM;
892		- return ret;
893		- }
894		- i2c_set_clientdata(i2c, max98373);
895		-
896		- /* update interleave mode info */
897		- if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode"))
898		- max98373->interleave_mode = 1;
899		- else
900		- max98373->interleave_mode = 0;
901		-
902		-
903		- /* regmap initialization */
904		- max98373->regmap
905		- = devm_regmap_init_i2c(i2c, &max98373_regmap);
906		- if (IS_ERR(max98373->regmap)) {
907		- ret = PTR_ERR(max98373->regmap);
908		- dev_err(&i2c->dev,
909		- "Failed to allocate regmap: %d\n", ret);
910		- return ret;
911		- }
912		-
913		- /* Check Revision ID */
914		- ret = regmap_read(max98373->regmap,
915		- MAX98373_R21FF_REV_ID, &reg);
916		- if (ret < 0) {
917		- dev_err(&i2c->dev,
918		- "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID);
919		- return ret;
920		- }
921		- dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg);
922		-
923		- /* voltage/current slot configuration */
924		- max98373_slot_config(i2c, max98373);
925		-
926		- /* codec registeration */
927		- ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373,
928		- max98373_dai, ARRAY_SIZE(max98373_dai));
929		- if (ret < 0)
930		- dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
931		-
932		- return ret;
933		-}
934		-
935		-static const struct i2c_device_id max98373_i2c_id[] = {
936		- { "max98373", 0},
937		- { },
938		-};
939		-
940		-MODULE_DEVICE_TABLE(i2c, max98373_i2c_id);
941		-
942		-#if defined(CONFIG_OF)
943		-static const struct of_device_id max98373_of_match[] = {
944		- { .compatible = "maxim,max98373", },
945		- { }
946		-};
947		-MODULE_DEVICE_TABLE(of, max98373_of_match);
948		-#endif
949		-
950		-#ifdef CONFIG_ACPI
951		-static const struct acpi_device_id max98373_acpi_match[] = {
952		- { "MX98373", 0 },
953		- {},
954		-};
955		-MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
956		-#endif
957		-
958		-static struct i2c_driver max98373_i2c_driver = {
959		- .driver = {
960		- .name = "max98373",
961		- .of_match_table = of_match_ptr(max98373_of_match),
962		- .acpi_match_table = ACPI_PTR(max98373_acpi_match),
963		- .pm = &max98373_pm,
964		- },
965		- .probe = max98373_i2c_probe,
966		- .id_table = max98373_i2c_id,
967		-};
968		-
969		-module_i2c_driver(max98373_i2c_driver)
	450	+EXPORT_SYMBOL_GPL(max98373_slot_config);
970	451
971	452	MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
972	453	MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");