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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/sound/soc/codecs/max98095.c
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..
@@ -1,11 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * max98095.c -- MAX98095 ALSA SoC Audio driver
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  *
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  * Copyright 2011 Maxim Integrated Products
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #include <linux/module.h>
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@@ -974,7 +971,7 @@
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 	cdata->rate = rate;
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 	/* Configure NI when operating as master */
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-	if (snd_soc_component_read32(component, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
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+	if (snd_soc_component_read(component, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
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 		if (max98095->sysclk == 0) {
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 			dev_err(component->dev, "Invalid system clock frequency\n");
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 			return -EINVAL;
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@@ -1035,7 +1032,7 @@
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 	cdata->rate = rate;
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 	/* Configure NI when operating as master */
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-	if (snd_soc_component_read32(component, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
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+	if (snd_soc_component_read(component, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
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 		if (max98095->sysclk == 0) {
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 			dev_err(component->dev, "Invalid system clock frequency\n");
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 			return -EINVAL;
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@@ -1096,7 +1093,7 @@
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 	cdata->rate = rate;
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 	/* Configure NI when operating as master */
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-	if (snd_soc_component_read32(component, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
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+	if (snd_soc_component_read(component, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
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 		if (max98095->sysclk == 0) {
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 			dev_err(component->dev, "Invalid system clock frequency\n");
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 			return -EINVAL;
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@@ -1537,7 +1534,7 @@
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 	regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
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 	/* Disable filter while configuring, and save current on/off state */
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-	regsave = snd_soc_component_read32(component, M98095_088_CFG_LEVEL);
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+	regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
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 	snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
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 	mutex_lock(&max98095->lock);
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@@ -1688,7 +1685,7 @@
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 	regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
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 	/* Disable filter while configuring, and save current on/off state */
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-	regsave = snd_soc_component_read32(component, M98095_088_CFG_LEVEL);
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+	regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
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 	snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
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 	mutex_lock(&max98095->lock);
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@@ -1819,7 +1816,7 @@
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 	int mic_report = 0;
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 	/* Read the Jack Status Register */
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-	value = snd_soc_component_read32(component, M98095_007_JACK_AUTO_STS);
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+	value = snd_soc_component_read(component, M98095_007_JACK_AUTO_STS);
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 	/* If ddone is not set, then detection isn't finished yet */
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 	if ((value & M98095_DDONE) == 0)
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@@ -1975,7 +1972,7 @@
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 	/* Reset to hardware default for registers, as there is not
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 	 * a soft reset hardware control register */
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 	for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
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-		ret = snd_soc_component_write(component, i, snd_soc_component_read32(component, i));
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+		ret = snd_soc_component_write(component, i, snd_soc_component_read(component, i));
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 		if (ret < 0) {
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 			dev_err(component->dev, "Failed to reset: %d\n", ret);
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 			return ret;
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@@ -2041,7 +2038,7 @@
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 		}
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 	}
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-	ret = snd_soc_component_read32(component, M98095_0FF_REV_ID);
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+	ret = snd_soc_component_read(component, M98095_0FF_REV_ID);
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 	if (ret < 0) {
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 		dev_err(component->dev, "Failure reading hardware revision: %d\n",
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 			ret);