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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/include/uapi/rdma/mlx5-abi.h
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@@ -45,6 +45,11 @@
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 	MLX5_QP_FLAG_BFREG_INDEX	= 1 << 3,
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 	MLX5_QP_FLAG_TYPE_DCT		= 1 << 4,
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 	MLX5_QP_FLAG_TYPE_DCI		= 1 << 5,
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+	MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6,
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+	MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
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+	MLX5_QP_FLAG_ALLOW_SCATTER_CQE	= 1 << 8,
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+	MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE	= 1 << 9,
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+	MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10,
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 };
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 enum {
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@@ -74,6 +79,7 @@
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 enum mlx5_lib_caps {
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 	MLX5_LIB_CAP_4K_UAR	= (__u64)1 << 0,
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+	MLX5_LIB_CAP_DYN_UAR	= (__u64)1 << 1,
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 };
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 enum mlx5_ib_alloc_uctx_v2_flags {
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@@ -94,6 +100,7 @@
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 enum mlx5_ib_alloc_ucontext_resp_mask {
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 	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
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 	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY    = 1UL << 1,
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+	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE               = 1UL << 2,
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 };
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 enum mlx5_user_cmds_supp_uhw {
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@@ -233,6 +240,8 @@
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 	/* Support 128B CQE compression */
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 	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
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 	MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD  = 1 << 1,
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+	MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
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+	MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3,
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 };
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 enum mlx5_ib_tunnel_offloads {
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@@ -260,6 +269,7 @@
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 enum mlx5_ib_create_cq_flags {
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 	MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD	= 1 << 0,
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+	MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX  = 1 << 1,
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 };
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 struct mlx5_ib_create_cq {
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@@ -269,6 +279,9 @@
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 	__u8    cqe_comp_en;
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 	__u8    cqe_comp_res_format;
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 	__u16	flags;
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+	__u16	uar_page_index;
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+	__u16	reserved0;
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+	__u32	reserved1;
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 };
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 struct mlx5_ib_create_cq_resp {
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@@ -310,6 +323,8 @@
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 		__aligned_u64 sq_buf_addr;
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 		__aligned_u64 access_key;
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 	};
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+	__u32  ece_options;
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+	__u32  reserved;
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 };
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 /* RX Hash function flags */
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@@ -349,9 +364,24 @@
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 	__u32	flags;
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 };
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+enum mlx5_ib_create_qp_resp_mask {
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+	MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0,
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+	MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1,
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+	MLX5_IB_CREATE_QP_RESP_MASK_RQN  = 1UL << 2,
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+	MLX5_IB_CREATE_QP_RESP_MASK_SQN  = 1UL << 3,
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+	MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR  = 1UL << 4,
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+};
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+
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 struct mlx5_ib_create_qp_resp {
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 	__u32	bfreg_index;
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-	__u32   reserved;
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+	__u32   ece_options;
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+	__u32	comp_mask;
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+	__u32	tirn;
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+	__u32	tisn;
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+	__u32	rqn;
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+	__u32	sqn;
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+	__u32   reserved1;
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+	__u64	tir_icm_addr;
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 };
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 struct mlx5_ib_alloc_mw {
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@@ -393,12 +423,14 @@
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 struct mlx5_ib_modify_qp {
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 	__u32			   comp_mask;
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 	struct mlx5_ib_burst_info  burst_info;
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-	__u32			   reserved;
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+	__u32			   ece_options;
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 };
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 struct mlx5_ib_modify_qp_resp {
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 	__u32	response_length;
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 	__u32	dctn;
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+	__u32   ece_options;
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+	__u32   reserved;
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 };
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 struct mlx5_ib_create_wq_resp {