| .. | .. |
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| 1 | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
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| 2 | 2 | /* |
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| 3 | 3 | * |
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| 4 | | - * (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved. |
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| 4 | + * (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved. |
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| 5 | 5 | * |
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| 6 | 6 | * This program is free software and is provided to you under the terms of the |
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| 7 | 7 | * GNU General Public License version 2 as published by the Free Software |
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| .. | .. |
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| 23 | 23 | #define _UAPI_BASE_JM_KERNEL_H_ |
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| 24 | 24 | |
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| 25 | 25 | #include <linux/types.h> |
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| 26 | +#include "../mali_base_common_kernel.h" |
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| 26 | 27 | |
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| 27 | | -/* Memory allocation, access/hint flags. |
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| 28 | +/* Memory allocation, access/hint flags & mask specific to JM GPU. |
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| 28 | 29 | * |
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| 29 | 30 | * See base_mem_alloc_flags. |
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| 30 | 31 | */ |
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| 31 | 32 | |
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| 32 | | -/* IN */ |
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| 33 | | -/* Read access CPU side |
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| 34 | | - */ |
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| 35 | | -#define BASE_MEM_PROT_CPU_RD ((base_mem_alloc_flags)1 << 0) |
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| 36 | | - |
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| 37 | | -/* Write access CPU side |
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| 38 | | - */ |
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| 39 | | -#define BASE_MEM_PROT_CPU_WR ((base_mem_alloc_flags)1 << 1) |
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| 40 | | - |
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| 41 | | -/* Read access GPU side |
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| 42 | | - */ |
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| 43 | | -#define BASE_MEM_PROT_GPU_RD ((base_mem_alloc_flags)1 << 2) |
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| 44 | | - |
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| 45 | | -/* Write access GPU side |
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| 46 | | - */ |
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| 47 | | -#define BASE_MEM_PROT_GPU_WR ((base_mem_alloc_flags)1 << 3) |
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| 48 | | - |
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| 49 | | -/* Execute allowed on the GPU side |
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| 50 | | - */ |
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| 51 | | -#define BASE_MEM_PROT_GPU_EX ((base_mem_alloc_flags)1 << 4) |
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| 52 | | - |
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| 53 | | -/* Will be permanently mapped in kernel space. |
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| 54 | | - * Flag is only allowed on allocations originating from kbase. |
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| 55 | | - */ |
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| 56 | | -#define BASEP_MEM_PERMANENT_KERNEL_MAPPING ((base_mem_alloc_flags)1 << 5) |
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| 57 | | - |
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| 58 | | -/* The allocation will completely reside within the same 4GB chunk in the GPU |
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| 59 | | - * virtual space. |
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| 60 | | - * Since this flag is primarily required only for the TLS memory which will |
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| 61 | | - * not be used to contain executable code and also not used for Tiler heap, |
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| 62 | | - * it can't be used along with BASE_MEM_PROT_GPU_EX and TILER_ALIGN_TOP flags. |
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| 63 | | - */ |
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| 64 | | -#define BASE_MEM_GPU_VA_SAME_4GB_PAGE ((base_mem_alloc_flags)1 << 6) |
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| 65 | | - |
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| 66 | | -/* Userspace is not allowed to free this memory. |
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| 67 | | - * Flag is only allowed on allocations originating from kbase. |
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| 68 | | - */ |
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| 69 | | -#define BASEP_MEM_NO_USER_FREE ((base_mem_alloc_flags)1 << 7) |
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| 70 | | - |
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| 33 | +/* Used as BASE_MEM_FIXED in other backends */ |
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| 71 | 34 | #define BASE_MEM_RESERVED_BIT_8 ((base_mem_alloc_flags)1 << 8) |
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| 72 | 35 | |
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| 73 | | -/* Grow backing store on GPU Page Fault |
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| 74 | | - */ |
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| 75 | | -#define BASE_MEM_GROW_ON_GPF ((base_mem_alloc_flags)1 << 9) |
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| 76 | | - |
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| 77 | | -/* Page coherence Outer shareable, if available |
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| 78 | | - */ |
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| 79 | | -#define BASE_MEM_COHERENT_SYSTEM ((base_mem_alloc_flags)1 << 10) |
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| 80 | | - |
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| 81 | | -/* Page coherence Inner shareable |
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| 82 | | - */ |
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| 83 | | -#define BASE_MEM_COHERENT_LOCAL ((base_mem_alloc_flags)1 << 11) |
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| 84 | | - |
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| 85 | | -/* IN/OUT */ |
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| 86 | | -/* Should be cached on the CPU, returned if actually cached |
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| 87 | | - */ |
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| 88 | | -#define BASE_MEM_CACHED_CPU ((base_mem_alloc_flags)1 << 12) |
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| 89 | | - |
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| 90 | | -/* IN/OUT */ |
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| 91 | | -/* Must have same VA on both the GPU and the CPU |
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| 92 | | - */ |
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| 93 | | -#define BASE_MEM_SAME_VA ((base_mem_alloc_flags)1 << 13) |
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| 94 | | - |
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| 95 | | -/* OUT */ |
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| 96 | | -/* Must call mmap to acquire a GPU address for the allocation |
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| 97 | | - */ |
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| 98 | | -#define BASE_MEM_NEED_MMAP ((base_mem_alloc_flags)1 << 14) |
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| 99 | | - |
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| 100 | | -/* IN */ |
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| 101 | | -/* Page coherence Outer shareable, required. |
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| 102 | | - */ |
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| 103 | | -#define BASE_MEM_COHERENT_SYSTEM_REQUIRED ((base_mem_alloc_flags)1 << 15) |
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| 104 | | - |
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| 105 | | -/* Protected memory |
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| 106 | | - */ |
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| 107 | | -#define BASE_MEM_PROTECTED ((base_mem_alloc_flags)1 << 16) |
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| 108 | | - |
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| 109 | | -/* Not needed physical memory |
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| 110 | | - */ |
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| 111 | | -#define BASE_MEM_DONT_NEED ((base_mem_alloc_flags)1 << 17) |
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| 112 | | - |
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| 113 | | -/* Must use shared CPU/GPU zone (SAME_VA zone) but doesn't require the |
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| 114 | | - * addresses to be the same |
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| 115 | | - */ |
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| 116 | | -#define BASE_MEM_IMPORT_SHARED ((base_mem_alloc_flags)1 << 18) |
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| 117 | | - |
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| 118 | 36 | /** |
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| 119 | | - * Bit 19 is reserved. |
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| 37 | + * BASE_MEM_RESERVED_BIT_19 - Bit 19 is reserved. |
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| 120 | 38 | * |
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| 121 | 39 | * Do not remove, use the next unreserved bit for new flags |
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| 122 | 40 | */ |
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| 123 | 41 | #define BASE_MEM_RESERVED_BIT_19 ((base_mem_alloc_flags)1 << 19) |
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| 124 | 42 | |
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| 125 | 43 | /** |
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| 126 | | - * Memory starting from the end of the initial commit is aligned to 'extension' |
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| 127 | | - * pages, where 'extension' must be a power of 2 and no more than |
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| 44 | + * BASE_MEM_TILER_ALIGN_TOP - Memory starting from the end of the initial commit is aligned |
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| 45 | + * to 'extension' pages, where 'extension' must be a power of 2 and no more than |
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| 128 | 46 | * BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES |
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| 129 | 47 | */ |
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| 130 | 48 | #define BASE_MEM_TILER_ALIGN_TOP ((base_mem_alloc_flags)1 << 20) |
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| 131 | 49 | |
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| 132 | | -/* Should be uncached on the GPU, will work only for GPUs using AARCH64 mmu |
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| 133 | | - * mode. Some components within the GPU might only be able to access memory |
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| 134 | | - * that is GPU cacheable. Refer to the specific GPU implementation for more |
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| 135 | | - * details. The 3 shareability flags will be ignored for GPU uncached memory. |
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| 136 | | - * If used while importing USER_BUFFER type memory, then the import will fail |
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| 137 | | - * if the memory is not aligned to GPU and CPU cache line width. |
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| 138 | | - */ |
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| 139 | | -#define BASE_MEM_UNCACHED_GPU ((base_mem_alloc_flags)1 << 21) |
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| 140 | | - |
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| 141 | | -/* |
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| 142 | | - * Bits [22:25] for group_id (0~15). |
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| 143 | | - * |
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| 144 | | - * base_mem_group_id_set() should be used to pack a memory group ID into a |
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| 145 | | - * base_mem_alloc_flags value instead of accessing the bits directly. |
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| 146 | | - * base_mem_group_id_get() should be used to extract the memory group ID from |
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| 147 | | - * a base_mem_alloc_flags value. |
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| 148 | | - */ |
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| 149 | | -#define BASEP_MEM_GROUP_ID_SHIFT 22 |
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| 150 | | -#define BASE_MEM_GROUP_ID_MASK \ |
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| 151 | | - ((base_mem_alloc_flags)0xF << BASEP_MEM_GROUP_ID_SHIFT) |
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| 152 | | - |
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| 153 | | -/* Must do CPU cache maintenance when imported memory is mapped/unmapped |
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| 154 | | - * on GPU. Currently applicable to dma-buf type only. |
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| 155 | | - */ |
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| 156 | | -#define BASE_MEM_IMPORT_SYNC_ON_MAP_UNMAP ((base_mem_alloc_flags)1 << 26) |
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| 157 | | - |
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| 158 | 50 | /* Use the GPU VA chosen by the kernel client */ |
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| 159 | 51 | #define BASE_MEM_FLAG_MAP_FIXED ((base_mem_alloc_flags)1 << 27) |
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| 160 | | - |
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| 161 | | -/* OUT */ |
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| 162 | | -/* Kernel side cache sync ops required */ |
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| 163 | | -#define BASE_MEM_KERNEL_SYNC ((base_mem_alloc_flags)1 << 28) |
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| 164 | 52 | |
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| 165 | 53 | /* Force trimming of JIT allocations when creating a new allocation */ |
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| 166 | 54 | #define BASEP_MEM_PERFORM_JIT_TRIM ((base_mem_alloc_flags)1 << 29) |
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| 167 | 55 | |
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| 168 | | -/* Number of bits used as flags for base memory management |
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| 169 | | - * |
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| 170 | | - * Must be kept in sync with the base_mem_alloc_flags flags |
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| 56 | +/* Note that the number of bits used for base_mem_alloc_flags |
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| 57 | + * must be less than BASE_MEM_FLAGS_NR_BITS !!! |
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| 171 | 58 | */ |
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| 172 | | -#define BASE_MEM_FLAGS_NR_BITS 30 |
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| 173 | 59 | |
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| 174 | 60 | /* A mask of all the flags which are only valid for allocations within kbase, |
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| 175 | 61 | * and may not be passed from user space. |
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| .. | .. |
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| 178 | 64 | (BASEP_MEM_PERMANENT_KERNEL_MAPPING | BASEP_MEM_NO_USER_FREE | \ |
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| 179 | 65 | BASE_MEM_FLAG_MAP_FIXED | BASEP_MEM_PERFORM_JIT_TRIM) |
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| 180 | 66 | |
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| 181 | | -/* A mask for all output bits, excluding IN/OUT bits. |
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| 182 | | - */ |
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| 183 | | -#define BASE_MEM_FLAGS_OUTPUT_MASK BASE_MEM_NEED_MMAP |
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| 184 | | - |
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| 185 | | -/* A mask for all input bits, including IN/OUT bits. |
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| 186 | | - */ |
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| 187 | | -#define BASE_MEM_FLAGS_INPUT_MASK \ |
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| 188 | | - (((1 << BASE_MEM_FLAGS_NR_BITS) - 1) & ~BASE_MEM_FLAGS_OUTPUT_MASK) |
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| 189 | | - |
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| 190 | 67 | /* A mask of all currently reserved flags |
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| 191 | 68 | */ |
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| 192 | 69 | #define BASE_MEM_FLAGS_RESERVED \ |
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| 193 | 70 | (BASE_MEM_RESERVED_BIT_8 | BASE_MEM_RESERVED_BIT_19) |
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| 194 | 71 | |
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| 195 | | -#define BASEP_MEM_INVALID_HANDLE (0ull << 12) |
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| 196 | | -#define BASE_MEM_MMU_DUMP_HANDLE (1ull << 12) |
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| 197 | | -#define BASE_MEM_TRACE_BUFFER_HANDLE (2ull << 12) |
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| 198 | | -#define BASE_MEM_MAP_TRACKING_HANDLE (3ull << 12) |
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| 199 | | -#define BASEP_MEM_WRITE_ALLOC_PAGES_HANDLE (4ull << 12) |
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| 200 | | -/* reserved handles ..-47<<PAGE_SHIFT> for future special handles */ |
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| 201 | | -#define BASE_MEM_COOKIE_BASE (64ul << 12) |
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| 202 | | -#define BASE_MEM_FIRST_FREE_ADDRESS ((BITS_PER_LONG << 12) + \ |
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| 203 | | - BASE_MEM_COOKIE_BASE) |
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| 204 | 72 | |
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| 205 | 73 | /* Similar to BASE_MEM_TILER_ALIGN_TOP, memory starting from the end of the |
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| 206 | 74 | * initial commit is aligned to 'extension' pages, where 'extension' must be a power |
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| .. | .. |
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| 209 | 77 | #define BASE_JIT_ALLOC_MEM_TILER_ALIGN_TOP (1 << 0) |
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| 210 | 78 | |
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| 211 | 79 | /** |
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| 212 | | - * If set, the heap info address points to a __u32 holding the used size in bytes; |
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| 80 | + * BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE - If set, the heap info address points |
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| 81 | + * to a __u32 holding the used size in bytes; |
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| 213 | 82 | * otherwise it points to a __u64 holding the lowest address of unused memory. |
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| 214 | 83 | */ |
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| 215 | 84 | #define BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE (1 << 1) |
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| 216 | 85 | |
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| 217 | 86 | /** |
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| 218 | | - * Valid set of just-in-time memory allocation flags |
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| 87 | + * BASE_JIT_ALLOC_VALID_FLAGS - Valid set of just-in-time memory allocation flags |
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| 219 | 88 | * |
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| 220 | 89 | * Note: BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE cannot be set if heap_info_gpu_addr |
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| 221 | 90 | * in %base_jit_alloc_info is 0 (atom with BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE set |
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| .. | .. |
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| 223 | 92 | */ |
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| 224 | 93 | #define BASE_JIT_ALLOC_VALID_FLAGS \ |
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| 225 | 94 | (BASE_JIT_ALLOC_MEM_TILER_ALIGN_TOP | BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE) |
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| 226 | | - |
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| 227 | | -/** |
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| 228 | | - * typedef base_context_create_flags - Flags to pass to ::base_context_init. |
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| 229 | | - * |
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| 230 | | - * Flags can be ORed together to enable multiple things. |
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| 231 | | - * |
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| 232 | | - * These share the same space as BASEP_CONTEXT_FLAG_*, and so must |
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| 233 | | - * not collide with them. |
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| 234 | | - */ |
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| 235 | | -typedef __u32 base_context_create_flags; |
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| 236 | | - |
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| 237 | | -/* No flags set */ |
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| 238 | | -#define BASE_CONTEXT_CREATE_FLAG_NONE ((base_context_create_flags)0) |
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| 239 | | - |
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| 240 | | -/* Base context is embedded in a cctx object (flag used for CINSTR |
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| 241 | | - * software counter macros) |
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| 242 | | - */ |
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| 243 | | -#define BASE_CONTEXT_CCTX_EMBEDDED ((base_context_create_flags)1 << 0) |
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| 244 | | - |
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| 245 | | -/* Base context is a 'System Monitor' context for Hardware counters. |
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| 246 | | - * |
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| 247 | | - * One important side effect of this is that job submission is disabled. |
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| 248 | | - */ |
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| 249 | | -#define BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED \ |
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| 250 | | - ((base_context_create_flags)1 << 1) |
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| 251 | | - |
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| 252 | | -/* Bit-shift used to encode a memory group ID in base_context_create_flags |
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| 253 | | - */ |
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| 254 | | -#define BASEP_CONTEXT_MMU_GROUP_ID_SHIFT (3) |
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| 255 | | - |
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| 256 | | -/* Bitmask used to encode a memory group ID in base_context_create_flags |
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| 257 | | - */ |
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| 258 | | -#define BASEP_CONTEXT_MMU_GROUP_ID_MASK \ |
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| 259 | | - ((base_context_create_flags)0xF << BASEP_CONTEXT_MMU_GROUP_ID_SHIFT) |
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| 260 | | - |
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| 261 | | -/* Bitpattern describing the base_context_create_flags that can be |
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| 262 | | - * passed to the kernel |
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| 263 | | - */ |
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| 264 | | -#define BASEP_CONTEXT_CREATE_KERNEL_FLAGS \ |
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| 265 | | - (BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED | \ |
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| 266 | | - BASEP_CONTEXT_MMU_GROUP_ID_MASK) |
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| 267 | 95 | |
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| 268 | 96 | /* Bitpattern describing the ::base_context_create_flags that can be |
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| 269 | 97 | * passed to base_context_init() |
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| .. | .. |
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| 284 | 112 | #define BASEP_CONTEXT_FLAG_JOB_DUMP_DISABLED \ |
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| 285 | 113 | ((base_context_create_flags)(1 << 31)) |
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| 286 | 114 | |
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| 287 | | -/* Enable additional tracepoints for latency measurements (TL_ATOM_READY, |
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| 288 | | - * TL_ATOM_DONE, TL_ATOM_PRIO_CHANGE, TL_ATOM_EVENT_POST) |
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| 289 | | - */ |
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| 290 | | -#define BASE_TLSTREAM_ENABLE_LATENCY_TRACEPOINTS (1 << 0) |
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| 291 | | - |
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| 292 | | -/* Indicate that job dumping is enabled. This could affect certain timers |
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| 293 | | - * to account for the performance impact. |
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| 294 | | - */ |
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| 295 | | -#define BASE_TLSTREAM_JOB_DUMPING_ENABLED (1 << 1) |
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| 296 | | - |
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| 115 | +/* Flags for base tracepoint specific to JM */ |
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| 297 | 116 | #define BASE_TLSTREAM_FLAGS_MASK (BASE_TLSTREAM_ENABLE_LATENCY_TRACEPOINTS | \ |
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| 298 | 117 | BASE_TLSTREAM_JOB_DUMPING_ENABLED) |
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| 299 | 118 | /* |
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| .. | .. |
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| 314 | 133 | /** |
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| 315 | 134 | * struct base_jd_udata - Per-job data |
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| 316 | 135 | * |
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| 136 | + * @blob: per-job data array |
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| 137 | + * |
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| 317 | 138 | * This structure is used to store per-job data, and is completely unused |
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| 318 | 139 | * by the Base driver. It can be used to store things such as callback |
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| 319 | 140 | * function pointer, data to handle job completion. It is guaranteed to be |
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| 320 | 141 | * untouched by the Base driver. |
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| 321 | | - * |
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| 322 | | - * @blob: per-job data array |
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| 323 | 142 | */ |
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| 324 | 143 | struct base_jd_udata { |
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| 325 | 144 | __u64 blob[2]; |
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| .. | .. |
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| 506 | 325 | * takes priority |
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| 507 | 326 | * |
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| 508 | 327 | * This is only guaranteed to work for BASE_JD_REQ_ONLY_COMPUTE atoms. |
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| 509 | | - * |
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| 510 | | - * If the core availability policy is keeping the required core group turned |
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| 511 | | - * off, then the job will fail with a BASE_JD_EVENT_PM_EVENT error code. |
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| 512 | 328 | */ |
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| 513 | 329 | #define BASE_JD_REQ_SPECIFIC_COHERENT_GROUP ((base_jd_core_req)1 << 11) |
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| 514 | 330 | |
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| .. | .. |
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| 611 | 427 | BASE_JD_REQ_V | BASE_JD_REQ_SOFT_JOB | BASE_JD_REQ_ONLY_COMPUTE) |
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| 612 | 428 | |
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| 613 | 429 | /** |
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| 614 | | - * Mask of all bits in base_jd_core_req that control the type of a soft job. |
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| 430 | + * BASE_JD_REQ_SOFT_JOB_TYPE - Mask of all bits in base_jd_core_req that |
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| 431 | + * controls the type of a soft job. |
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| 615 | 432 | */ |
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| 616 | 433 | #define BASE_JD_REQ_SOFT_JOB_TYPE (BASE_JD_REQ_SOFT_JOB | 0x1f) |
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| 617 | 434 | |
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| .. | .. |
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| 623 | 440 | ((core_req) & BASE_JD_REQ_ATOM_TYPE) == BASE_JD_REQ_DEP) |
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| 624 | 441 | |
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| 625 | 442 | /** |
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| 626 | | - * enum kbase_jd_atom_state |
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| 443 | + * enum kbase_jd_atom_state - Atom states |
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| 627 | 444 | * |
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| 628 | 445 | * @KBASE_JD_ATOM_STATE_UNUSED: Atom is not used. |
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| 629 | 446 | * @KBASE_JD_ATOM_STATE_QUEUED: Atom is queued in JD. |
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| .. | .. |
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| 648 | 465 | typedef __u8 base_atom_id; |
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| 649 | 466 | |
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| 650 | 467 | /** |
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| 651 | | - * struct base_dependency - |
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| 468 | + * struct base_dependency - base dependency |
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| 652 | 469 | * |
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| 653 | 470 | * @atom_id: An atom number |
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| 654 | 471 | * @dependency_type: Dependency type |
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| .. | .. |
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| 765 | 582 | * BASE_JD_PRIO_MEDIUM, and BASE_JD_PRIO_LOW |
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| 766 | 583 | */ |
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| 767 | 584 | #define BASE_JD_PRIO_REALTIME ((base_jd_prio)3) |
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| 585 | + |
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| 586 | +/* Invalid atom priority (max uint8_t value) */ |
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| 587 | +#define BASE_JD_PRIO_INVALID ((base_jd_prio)255) |
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| 768 | 588 | |
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| 769 | 589 | /* Count of the number of priority levels. This itself is not a valid |
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| 770 | 590 | * base_jd_prio setting |
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| .. | .. |
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| 1012 | 832 | * BASE_JD_EVENT_JOB_CONFIG_FAULT, or if the |
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| 1013 | 833 | * platform doesn't support the feature specified in |
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| 1014 | 834 | * the atom. |
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| 1015 | | - * @BASE_JD_EVENT_PM_EVENT: TODO: remove as it's not used |
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| 1016 | | - * @BASE_JD_EVENT_TIMED_OUT: TODO: remove as it's not used |
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| 1017 | | - * @BASE_JD_EVENT_BAG_INVALID: TODO: remove as it's not used |
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| 1018 | | - * @BASE_JD_EVENT_PROGRESS_REPORT: TODO: remove as it's not used |
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| 1019 | | - * @BASE_JD_EVENT_BAG_DONE: TODO: remove as it's not used |
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| 1020 | 835 | * @BASE_JD_EVENT_DRV_TERMINATED: this is a special event generated to indicate |
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| 1021 | 836 | * to userspace that the KBase context has been |
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| 1022 | 837 | * destroyed and Base should stop listening for |
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| .. | .. |
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| 1111 | 926 | /* SW defined exceptions */ |
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| 1112 | 927 | BASE_JD_EVENT_MEM_GROWTH_FAILED = |
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| 1113 | 928 | BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x000, |
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| 1114 | | - BASE_JD_EVENT_TIMED_OUT = |
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| 1115 | | - BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x001, |
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| 1116 | 929 | BASE_JD_EVENT_JOB_CANCELLED = |
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| 1117 | 930 | BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x002, |
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| 1118 | 931 | BASE_JD_EVENT_JOB_INVALID = |
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| 1119 | 932 | BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x003, |
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| 1120 | | - BASE_JD_EVENT_PM_EVENT = |
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| 1121 | | - BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x004, |
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| 1122 | | - |
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| 1123 | | - BASE_JD_EVENT_BAG_INVALID = |
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| 1124 | | - BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_BAG | 0x003, |
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| 1125 | 933 | |
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| 1126 | 934 | BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_END = BASE_JD_SW_EVENT | |
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| 1127 | 935 | BASE_JD_SW_EVENT_RESERVED | 0x3FF, |
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| .. | .. |
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| 1129 | 937 | BASE_JD_EVENT_RANGE_SW_SUCCESS_START = BASE_JD_SW_EVENT | |
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| 1130 | 938 | BASE_JD_SW_EVENT_SUCCESS | 0x000, |
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| 1131 | 939 | |
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| 1132 | | - BASE_JD_EVENT_PROGRESS_REPORT = BASE_JD_SW_EVENT | |
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| 1133 | | - BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_JOB | 0x000, |
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| 1134 | | - BASE_JD_EVENT_BAG_DONE = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | |
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| 1135 | | - BASE_JD_SW_EVENT_BAG | 0x000, |
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| 1136 | 940 | BASE_JD_EVENT_DRV_TERMINATED = BASE_JD_SW_EVENT | |
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| 1137 | 941 | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_INFO | 0x000, |
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| 1138 | 942 | |
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| .. | .. |
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| 1153 | 957 | /** |
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| 1154 | 958 | * struct base_jd_event_v2 - Event reporting structure |
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| 1155 | 959 | * |
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| 1156 | | - * @event_code: event code. |
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| 960 | + * @event_code: event code of type @ref base_jd_event_code. |
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| 1157 | 961 | * @atom_number: the atom number that has completed. |
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| 962 | + * @padding: padding. |
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| 1158 | 963 | * @udata: user data. |
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| 1159 | 964 | * |
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| 1160 | 965 | * This structure is used by the kernel driver to report information |
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| .. | .. |
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| 1165 | 970 | * by ANDing with BASE_JD_SW_EVENT_TYPE_MASK. |
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| 1166 | 971 | */ |
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| 1167 | 972 | struct base_jd_event_v2 { |
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| 1168 | | - enum base_jd_event_code event_code; |
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| 973 | + __u32 event_code; |
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| 1169 | 974 | base_atom_id atom_number; |
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| 975 | + __u8 padding[3]; |
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| 1170 | 976 | struct base_jd_udata udata; |
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| 1171 | 977 | }; |
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| 1172 | 978 | |
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| .. | .. |
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| 1197 | 1003 | __u8 padding[36]; |
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| 1198 | 1004 | }; |
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| 1199 | 1005 | |
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| 1006 | +/** |
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| 1007 | + * struct mali_base_gpu_core_props - GPU core props info |
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| 1008 | + * |
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| 1009 | + * @product_id: Pro specific value. |
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| 1010 | + * @version_status: Status of the GPU release. No defined values, but starts at |
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| 1011 | + * 0 and increases by one for each release status (alpha, beta, EAC, etc.). |
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| 1012 | + * 4 bit values (0-15). |
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| 1013 | + * @minor_revision: Minor release number of the GPU. "P" part of an "RnPn" |
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| 1014 | + * release number. |
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| 1015 | + * 8 bit values (0-255). |
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| 1016 | + * @major_revision: Major release number of the GPU. "R" part of an "RnPn" |
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| 1017 | + * release number. |
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| 1018 | + * 4 bit values (0-15). |
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| 1019 | + * @padding: padding to align to 8-byte |
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| 1020 | + * @gpu_freq_khz_max: The maximum GPU frequency. Reported to applications by |
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| 1021 | + * clGetDeviceInfo() |
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| 1022 | + * @log2_program_counter_size: Size of the shader program counter, in bits. |
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| 1023 | + * @texture_features: TEXTURE_FEATURES_x registers, as exposed by the GPU. This |
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| 1024 | + * is a bitpattern where a set bit indicates that the format is supported. |
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| 1025 | + * Before using a texture format, it is recommended that the corresponding |
|---|
| 1026 | + * bit be checked. |
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| 1027 | + * @paddings_1: Padding bytes. |
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| 1028 | + * @gpu_available_memory_size: Theoretical maximum memory available to the GPU. |
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| 1029 | + * It is unlikely that a client will be able to allocate all of this memory |
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| 1030 | + * for their own purposes, but this at least provides an upper bound on the |
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| 1031 | + * memory available to the GPU. |
|---|
| 1032 | + * This is required for OpenCL's clGetDeviceInfo() call when |
|---|
| 1033 | + * CL_DEVICE_GLOBAL_MEM_SIZE is requested, for OpenCL GPU devices. The |
|---|
| 1034 | + * client will not be expecting to allocate anywhere near this value. |
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| 1035 | + * @num_exec_engines: The number of execution engines. Only valid for tGOX |
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| 1036 | + * (Bifrost) GPUs, where GPU_HAS_REG_CORE_FEATURES is defined. Otherwise, |
|---|
| 1037 | + * this is always 0. |
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| 1038 | + * @paddings_2: Padding bytes. |
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| 1039 | + */ |
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| 1040 | +struct mali_base_gpu_core_props { |
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| 1041 | + __u32 product_id; |
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| 1042 | + __u16 version_status; |
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| 1043 | + __u16 minor_revision; |
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| 1044 | + __u16 major_revision; |
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| 1045 | + __u16 padding; |
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| 1046 | + __u32 gpu_freq_khz_max; |
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| 1047 | + __u32 log2_program_counter_size; |
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| 1048 | + __u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS]; |
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| 1049 | + __u8 paddings_1[4]; |
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| 1050 | + __u64 gpu_available_memory_size; |
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| 1051 | + __u8 num_exec_engines; |
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| 1052 | + __u8 paddings_2[7]; |
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| 1053 | +}; |
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| 1054 | + |
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| 1200 | 1055 | #endif /* _UAPI_BASE_JM_KERNEL_H_ */ |
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