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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/include/linux/qcom-geni-se.h
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@@ -1,10 +1,12 @@
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-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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+/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
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  */
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 #ifndef _LINUX_QCOM_GENI_SE
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 #define _LINUX_QCOM_GENI_SE
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+
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+#include <linux/interconnect.h>
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 /* Transfer mode supported by GENI Serial Engines */
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 enum geni_se_xfer_mode {
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@@ -25,6 +27,17 @@
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 struct geni_wrapper;
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 struct clk;
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+enum geni_icc_path_index {
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+	GENI_TO_CORE,
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+	CPU_TO_GENI,
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+	GENI_TO_DDR
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+};
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+
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+struct geni_icc_path {
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+	struct icc_path *path;
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+	unsigned int avg_bw;
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+};
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+
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 /**
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  * struct geni_se - GENI Serial Engine
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  * @base:		Base Address of the Serial Engine's register block
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@@ -33,6 +46,9 @@
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  * @clk:		Handle to the core serial engine clock
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  * @num_clk_levels:	Number of valid clock levels in clk_perf_tbl
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  * @clk_perf_tbl:	Table of clock frequency input to serial engine clock
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+ * @icc_paths:		Array of ICC paths for SE
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+ * @opp_table:		Pointer to the OPP table
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+ * @has_opp_table:	Specifies if the SE has an OPP table
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  */
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 struct geni_se {
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 	void __iomem *base;
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@@ -41,6 +57,9 @@
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 	struct clk *clk;
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 	unsigned int num_clk_levels;
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 	unsigned long *clk_perf_tbl;
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+	struct geni_icc_path icc_paths[3];
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+	struct opp_table *opp_table;
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+	bool has_opp_table;
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 };
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 /* Common SE registers */
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@@ -225,18 +244,31 @@
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 #define HW_VER_MINOR_SHFT		16
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 #define HW_VER_STEP_MASK		GENMASK(15, 0)
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+#define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
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+#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
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+#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
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+
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+/* QUP SE VERSION value for major number 2 and minor number 5 */
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+#define QUP_SE_VERSION_2_5                  0x20050000
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+
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+/*
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+ * Define bandwidth thresholds that cause the underlying Core 2X interconnect
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+ * clock to run at the named frequency. These baseline values are recommended
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+ * by the hardware team, and are not dynamically scaled with GENI bandwidth
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+ * beyond basic on/off.
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+ */
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+#define CORE_2X_19_2_MHZ		960
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+#define CORE_2X_50_MHZ			2500
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+#define CORE_2X_100_MHZ			5000
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+#define CORE_2X_150_MHZ			7500
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+#define CORE_2X_200_MHZ			10000
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+#define CORE_2X_236_MHZ			16383
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+
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+#define GENI_DEFAULT_BW			Bps_to_icc(1000)
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+
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 #if IS_ENABLED(CONFIG_QCOM_GENI_SE)
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 u32 geni_se_get_qup_hw_version(struct geni_se *se);
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-
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-#define geni_se_get_wrapper_version(se, major, minor, step) do { \
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-	u32 ver; \
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-\
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-	ver = geni_se_get_qup_hw_version(se); \
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-	major = (ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT; \
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-	minor = (ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT; \
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-	step = version & HW_VER_STEP_MASK; \
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-} while (0)
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 /**
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  * geni_se_read_proto() - Read the protocol configured for a serial engine
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@@ -267,7 +299,7 @@
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 	u32 m_cmd;
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 	m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
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-	writel_relaxed(m_cmd, se->base + SE_GENI_M_CMD0);
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+	writel(m_cmd, se->base + SE_GENI_M_CMD0);
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 }
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 /**
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@@ -287,7 +319,7 @@
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 	s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
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 	s_cmd |= (cmd << S_OPCODE_SHFT);
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 	s_cmd |= (params & S_PARAMS_MSK);
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-	writel_relaxed(s_cmd, se->base + SE_GENI_S_CMD0);
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+	writel(s_cmd, se->base + SE_GENI_S_CMD0);
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 }
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 /**
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@@ -421,5 +453,14 @@
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 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
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 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
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+
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+int geni_icc_get(struct geni_se *se, const char *icc_ddr);
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+
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+int geni_icc_set_bw(struct geni_se *se);
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+void geni_icc_set_tag(struct geni_se *se, u32 tag);
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+
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+int geni_icc_enable(struct geni_se *se);
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+
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+int geni_icc_disable(struct geni_se *se);
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 #endif
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 #endif