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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/include/linux/mtd/spi-nor.h
....@@ -1,10 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
12 /*
23  * Copyright (C) 2014 Freescale Semiconductor, Inc.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License as published by
6
- * the Free Software Foundation; either version 2 of the License, or
7
- * (at your option) any later version.
84  */
95 
106 #ifndef __LINUX_MTD_SPI_NOR_H
....@@ -13,21 +9,7 @@
139 #include <linux/bitops.h>
1410 #include <linux/mtd/cfi.h>
1511 #include <linux/mtd/mtd.h>
16
-
17
-/*
18
- * Manufacturer IDs
19
- *
20
- * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
21
- * Sometimes these are the same as CFI IDs, but sometimes they aren't.
22
- */
23
-#define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
24
-#define SNOR_MFR_GIGADEVICE	0xc8
25
-#define SNOR_MFR_INTEL		CFI_MFR_INTEL
26
-#define SNOR_MFR_MICRON		CFI_MFR_ST /* ST Micro <--> Micron */
27
-#define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
28
-#define SNOR_MFR_SPANSION	CFI_MFR_AMD
29
-#define SNOR_MFR_SST		CFI_MFR_SST
30
-#define SNOR_MFR_WINBOND	0xef /* Also used by some Spansion */
12
+#include <linux/spi/spi-mem.h>
3113 
3214 /*
3315  * Note on opcode nomenclature: some opcodes have a format like
....@@ -38,6 +20,7 @@
3820  */
3921 
4022 /* Flash opcodes. */
23
+#define SPINOR_OP_WRDI		0x04	/* Write disable */
4124 #define SPINOR_OP_WREN		0x06	/* Write enable */
4225 #define SPINOR_OP_RDSR		0x05	/* Read status register */
4326 #define SPINOR_OP_WRSR		0x01	/* Write status register 1 byte */
....@@ -49,9 +32,13 @@
4932 #define SPINOR_OP_READ_1_2_2	0xbb	/* Read data bytes (Dual I/O SPI) */
5033 #define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad Output SPI) */
5134 #define SPINOR_OP_READ_1_4_4	0xeb	/* Read data bytes (Quad I/O SPI) */
35
+#define SPINOR_OP_READ_1_1_8	0x8b	/* Read data bytes (Octal Output SPI) */
36
+#define SPINOR_OP_READ_1_8_8	0xcb	/* Read data bytes (Octal I/O SPI) */
5237 #define SPINOR_OP_PP		0x02	/* Page program (up to 256 bytes) */
5338 #define SPINOR_OP_PP_1_1_4	0x32	/* Quad page program */
5439 #define SPINOR_OP_PP_1_4_4	0x38	/* Quad page program */
40
+#define SPINOR_OP_PP_1_1_8	0x82	/* Octal page program */
41
+#define SPINOR_OP_PP_1_8_8	0xc2	/* Octal page program */
5542 #define SPINOR_OP_BE_4K		0x20	/* Erase 4KiB block */
5643 #define SPINOR_OP_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */
5744 #define SPINOR_OP_BE_32K	0x52	/* Erase 32KiB block */
....@@ -60,6 +47,7 @@
6047 #define SPINOR_OP_RDID		0x9f	/* Read JEDEC ID */
6148 #define SPINOR_OP_RDSFDP	0x5a	/* Read SFDP */
6249 #define SPINOR_OP_RDCR		0x35	/* Read configuration register */
50
+#define SPINOR_OP_WRCR		0x31	/* Write configure register */
6351 #define SPINOR_OP_RDFSR		0x70	/* Read flag status register */
6452 #define SPINOR_OP_CLFSR		0x50	/* Clear flag status register */
6553 #define SPINOR_OP_RDEAR		0xc8	/* Read Extended Address Register */
....@@ -72,9 +60,13 @@
7260 #define SPINOR_OP_READ_1_2_2_4B	0xbc	/* Read data bytes (Dual I/O SPI) */
7361 #define SPINOR_OP_READ_1_1_4_4B	0x6c	/* Read data bytes (Quad Output SPI) */
7462 #define SPINOR_OP_READ_1_4_4_4B	0xec	/* Read data bytes (Quad I/O SPI) */
63
+#define SPINOR_OP_READ_1_1_8_4B	0x7c	/* Read data bytes (Octal Output SPI) */
64
+#define SPINOR_OP_READ_1_8_8_4B	0xcc	/* Read data bytes (Octal I/O SPI) */
7565 #define SPINOR_OP_PP_4B		0x12	/* Page program (up to 256 bytes) */
7666 #define SPINOR_OP_PP_1_1_4_4B	0x34	/* Quad page program */
7767 #define SPINOR_OP_PP_1_4_4_4B	0x3e	/* Quad page program */
68
+#define SPINOR_OP_PP_1_1_8_4B	0x84	/* Octal page program */
69
+#define SPINOR_OP_PP_1_8_8_4B	0x8e	/* Octal page program */
7870 #define SPINOR_OP_BE_4K_4B	0x21	/* Erase 4KiB block */
7971 #define SPINOR_OP_BE_32K_4B	0x5c	/* Erase 32KiB block */
8072 #define SPINOR_OP_SE_4B		0xdc	/* Sector erase (usually 64KiB) */
....@@ -90,7 +82,6 @@
9082 
9183 /* Used for SST flashes only. */
9284 #define SPINOR_OP_BP		0x02	/* Byte program */
93
-#define SPINOR_OP_WRDI		0x04	/* Write disable */
9485 #define SPINOR_OP_AAI_WP	0xad	/* Auto address increment word program */
9586 
9687 /* Used for S3AN flashes only */
....@@ -121,13 +112,18 @@
121112 #define SR_BP0			BIT(2)	/* Block protect 0 */
122113 #define SR_BP1			BIT(3)	/* Block protect 1 */
123114 #define SR_BP2			BIT(4)	/* Block protect 2 */
124
-#define SR_TB			BIT(5)	/* Top/Bottom protect */
115
+#define SR_BP3			BIT(5)	/* Block protect 3 */
116
+#define SR_TB_BIT5		BIT(5)	/* Top/Bottom protect */
117
+#define SR_BP3_BIT6		BIT(6)	/* Block protect 3 */
118
+#define SR_TB_BIT6		BIT(6)	/* Top/Bottom protect */
125119 #define SR_SRWD			BIT(7)	/* SR write protect */
126120 /* Spansion/Cypress specific status bits */
127121 #define SR_E_ERR		BIT(5)
128122 #define SR_P_ERR		BIT(6)
129123 
130
-#define SR_QUAD_EN_MX		BIT(6)	/* Macronix Quad I/O */
124
+#define SR1_QUAD_EN_BIT6	BIT(6)
125
+
126
+#define SR_BP_SHIFT		2
131127 
132128 /* Enhanced Volatile Configuration Register bits */
133129 #define EVCR_QUAD_EN_MICRON	BIT(7)	/* Micron Quad I/O */
....@@ -138,10 +134,9 @@
138134 #define FSR_P_ERR		BIT(4)	/* Program operation status */
139135 #define FSR_PT_ERR		BIT(1)	/* Protection error bit */
140136 
141
-/* Configuration Register bits. */
142
-#define CR_QUAD_EN_SPAN		BIT(1)	/* Spansion Quad I/O */
143
-
144137 /* Status Register 2 bits. */
138
+#define SR2_QUAD_EN_BIT1	BIT(1)
139
+#define SR2_QUAD_EN_BIT2	BIT(2)
145140 #define SR2_QUAD_EN_BIT7	BIT(7)
146141 
147142 /* Supported SPI protocols */
....@@ -219,115 +214,6 @@
219214 	return spi_nor_get_protocol_data_nbits(proto);
220215 }
221216 
222
-#define SPI_NOR_MAX_CMD_SIZE	8
223
-enum spi_nor_ops {
224
-	SPI_NOR_OPS_READ = 0,
225
-	SPI_NOR_OPS_WRITE,
226
-	SPI_NOR_OPS_ERASE,
227
-	SPI_NOR_OPS_LOCK,
228
-	SPI_NOR_OPS_UNLOCK,
229
-};
230
-
231
-enum spi_nor_option_flags {
232
-	SNOR_F_USE_FSR		= BIT(0),
233
-	SNOR_F_HAS_SR_TB	= BIT(1),
234
-	SNOR_F_NO_OP_CHIP_ERASE	= BIT(2),
235
-	SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
236
-	SNOR_F_READY_XSR_RDY	= BIT(4),
237
-	SNOR_F_USE_CLSR		= BIT(5),
238
-	SNOR_F_BROKEN_RESET	= BIT(6),
239
-};
240
-
241
-/**
242
- * struct flash_info - Forward declaration of a structure used internally by
243
- *		       spi_nor_scan()
244
- */
245
-struct flash_info;
246
-
247
-/**
248
- * struct spi_nor - Structure for defining a the SPI NOR layer
249
- * @mtd:		point to a mtd_info structure
250
- * @lock:		the lock for the read/write/erase/lock/unlock operations
251
- * @dev:		point to a spi device, or a spi nor controller device.
252
- * @info:		spi-nor part JDEC MFR id and other info
253
- * @page_size:		the page size of the SPI NOR
254
- * @addr_width:		number of address bytes
255
- * @erase_opcode:	the opcode for erasing a sector
256
- * @read_opcode:	the read opcode
257
- * @read_dummy:		the dummy needed by the read operation
258
- * @program_opcode:	the program opcode
259
- * @sst_write_second:	used by the SST write operation
260
- * @flags:		flag options for the current SPI-NOR (SNOR_F_*)
261
- * @read_proto:		the SPI protocol for read operations
262
- * @write_proto:	the SPI protocol for write operations
263
- * @reg_proto		the SPI protocol for read_reg/write_reg/erase operations
264
- * @cmd_buf:		used by the write_reg
265
- * @prepare:		[OPTIONAL] do some preparations for the
266
- *			read/write/erase/lock/unlock operations
267
- * @unprepare:		[OPTIONAL] do some post work after the
268
- *			read/write/erase/lock/unlock operations
269
- * @read_reg:		[DRIVER-SPECIFIC] read out the register
270
- * @write_reg:		[DRIVER-SPECIFIC] write data to the register
271
- * @read:		[DRIVER-SPECIFIC] read data from the SPI NOR
272
- * @write:		[DRIVER-SPECIFIC] write data to the SPI NOR
273
- * @erase:		[DRIVER-SPECIFIC] erase a sector of the SPI NOR
274
- *			at the offset @offs; if not provided by the driver,
275
- *			spi-nor will send the erase opcode via write_reg()
276
- * @flash_lock:		[FLASH-SPECIFIC] lock a region of the SPI NOR
277
- * @flash_unlock:	[FLASH-SPECIFIC] unlock a region of the SPI NOR
278
- * @flash_is_locked:	[FLASH-SPECIFIC] check if a region of the SPI NOR is
279
- * @quad_enable:	[FLASH-SPECIFIC] enables SPI NOR quad mode
280
- *			completely locked
281
- * @priv:		the private data
282
- */
283
-struct spi_nor {
284
-	struct mtd_info		mtd;
285
-	struct mutex		lock;
286
-	struct device		*dev;
287
-	const struct flash_info	*info;
288
-	u32			page_size;
289
-	u8			addr_width;
290
-	u8			erase_opcode;
291
-	u8			read_opcode;
292
-	u8			read_dummy;
293
-	u8			program_opcode;
294
-	enum spi_nor_protocol	read_proto;
295
-	enum spi_nor_protocol	write_proto;
296
-	enum spi_nor_protocol	reg_proto;
297
-	bool			sst_write_second;
298
-	u32			flags;
299
-	u8			cmd_buf[SPI_NOR_MAX_CMD_SIZE];
300
-
301
-	int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
302
-	void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
303
-	int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
304
-	int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
305
-
306
-	ssize_t (*read)(struct spi_nor *nor, loff_t from,
307
-			size_t len, u_char *read_buf);
308
-	ssize_t (*write)(struct spi_nor *nor, loff_t to,
309
-			size_t len, const u_char *write_buf);
310
-	int (*erase)(struct spi_nor *nor, loff_t offs);
311
-
312
-	int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
313
-	int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
314
-	int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
315
-	int (*quad_enable)(struct spi_nor *nor);
316
-
317
-	void *priv;
318
-};
319
-
320
-static inline void spi_nor_set_flash_node(struct spi_nor *nor,
321
-					  struct device_node *np)
322
-{
323
-	mtd_set_of_node(&nor->mtd, np);
324
-}
325
-
326
-static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
327
-{
328
-	return mtd_get_of_node(&nor->mtd);
329
-}
330
-
331217 /**
332218  * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
333219  * supported by the SPI controller (bus master).
....@@ -340,7 +226,7 @@
340226 /*
341227  *(Fast) Read capabilities.
342228  * MUST be ordered by priority: the higher bit position, the higher priority.
343
- * As a matter of performances, it is relevant to use Octo SPI protocols first,
229
+ * As a matter of performances, it is relevant to use Octal SPI protocols first,
344230  * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
345231  * (Slow) Read.
346232  */
....@@ -361,7 +247,7 @@
361247 #define SNOR_HWCAPS_READ_4_4_4		BIT(9)
362248 #define SNOR_HWCAPS_READ_1_4_4_DTR	BIT(10)
363249 
364
-#define SNOR_HWCPAS_READ_OCTO		GENMASK(14, 11)
250
+#define SNOR_HWCAPS_READ_OCTAL		GENMASK(14, 11)
365251 #define SNOR_HWCAPS_READ_1_1_8		BIT(11)
366252 #define SNOR_HWCAPS_READ_1_8_8		BIT(12)
367253 #define SNOR_HWCAPS_READ_8_8_8		BIT(13)
....@@ -370,7 +256,7 @@
370256 /*
371257  * Page Program capabilities.
372258  * MUST be ordered by priority: the higher bit position, the higher priority.
373
- * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
259
+ * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
374260  * legacy SPI 1-1-1 protocol.
375261  * Note that Dual Page Programs are not supported because there is no existing
376262  * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
....@@ -384,11 +270,139 @@
384270 #define SNOR_HWCAPS_PP_1_4_4	BIT(18)
385271 #define SNOR_HWCAPS_PP_4_4_4	BIT(19)
386272 
387
-#define SNOR_HWCAPS_PP_OCTO	GENMASK(22, 20)
273
+#define SNOR_HWCAPS_PP_OCTAL	GENMASK(22, 20)
388274 #define SNOR_HWCAPS_PP_1_1_8	BIT(20)
389275 #define SNOR_HWCAPS_PP_1_8_8	BIT(21)
390276 #define SNOR_HWCAPS_PP_8_8_8	BIT(22)
391277 
278
+#define SNOR_HWCAPS_X_X_X	(SNOR_HWCAPS_READ_2_2_2 |	\
279
+				 SNOR_HWCAPS_READ_4_4_4 |	\
280
+				 SNOR_HWCAPS_READ_8_8_8 |	\
281
+				 SNOR_HWCAPS_PP_4_4_4 |		\
282
+				 SNOR_HWCAPS_PP_8_8_8)
283
+
284
+#define SNOR_HWCAPS_DTR		(SNOR_HWCAPS_READ_1_1_1_DTR |	\
285
+				 SNOR_HWCAPS_READ_1_2_2_DTR |	\
286
+				 SNOR_HWCAPS_READ_1_4_4_DTR |	\
287
+				 SNOR_HWCAPS_READ_1_8_8_DTR)
288
+
289
+#define SNOR_HWCAPS_ALL		(SNOR_HWCAPS_READ_MASK |	\
290
+				 SNOR_HWCAPS_PP_MASK)
291
+
292
+/* Forward declaration that is used in 'struct spi_nor_controller_ops' */
293
+struct spi_nor;
294
+
295
+/**
296
+ * struct spi_nor_controller_ops - SPI NOR controller driver specific
297
+ *                                 operations.
298
+ * @prepare:		[OPTIONAL] do some preparations for the
299
+ *			read/write/erase/lock/unlock operations.
300
+ * @unprepare:		[OPTIONAL] do some post work after the
301
+ *			read/write/erase/lock/unlock operations.
302
+ * @read_reg:		read out the register.
303
+ * @write_reg:		write data to the register.
304
+ * @read:		read data from the SPI NOR.
305
+ * @write:		write data to the SPI NOR.
306
+ * @erase:		erase a sector of the SPI NOR at the offset @offs; if
307
+ *			not provided by the driver, SPI NOR will send the erase
308
+ *			opcode via write_reg().
309
+ */
310
+struct spi_nor_controller_ops {
311
+	int (*prepare)(struct spi_nor *nor);
312
+	void (*unprepare)(struct spi_nor *nor);
313
+	int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
314
+	int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
315
+			 size_t len);
316
+
317
+	ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
318
+	ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
319
+			 const u8 *buf);
320
+	int (*erase)(struct spi_nor *nor, loff_t offs);
321
+};
322
+
323
+/*
324
+ * Forward declarations that are used internally by the core and manufacturer
325
+ * drivers.
326
+ */
327
+struct flash_info;
328
+struct spi_nor_manufacturer;
329
+struct spi_nor_flash_parameter;
330
+
331
+/**
332
+ * struct spi_nor - Structure for defining the SPI NOR layer
333
+ * @mtd:		an mtd_info structure
334
+ * @lock:		the lock for the read/write/erase/lock/unlock operations
335
+ * @dev:		pointer to an SPI device or an SPI NOR controller device
336
+ * @spimem:		pointer to the SPI memory device
337
+ * @bouncebuf:		bounce buffer used when the buffer passed by the MTD
338
+ *                      layer is not DMA-able
339
+ * @bouncebuf_size:	size of the bounce buffer
340
+ * @info:		SPI NOR part JEDEC MFR ID and other info
341
+ * @manufacturer:	SPI NOR manufacturer
342
+ * @page_size:		the page size of the SPI NOR
343
+ * @addr_width:		number of address bytes
344
+ * @erase_opcode:	the opcode for erasing a sector
345
+ * @read_opcode:	the read opcode
346
+ * @read_dummy:		the dummy needed by the read operation
347
+ * @program_opcode:	the program opcode
348
+ * @sst_write_second:	used by the SST write operation
349
+ * @flags:		flag options for the current SPI NOR (SNOR_F_*)
350
+ * @read_proto:		the SPI protocol for read operations
351
+ * @write_proto:	the SPI protocol for write operations
352
+ * @reg_proto:		the SPI protocol for read_reg/write_reg/erase operations
353
+ * @controller_ops:	SPI NOR controller driver specific operations.
354
+ * @params:		[FLASH-SPECIFIC] SPI NOR flash parameters and settings.
355
+ *                      The structure includes legacy flash parameters and
356
+ *                      settings that can be overwritten by the spi_nor_fixups
357
+ *                      hooks, or dynamically when parsing the SFDP tables.
358
+ * @dirmap:		pointers to struct spi_mem_dirmap_desc for reads/writes.
359
+ * @priv:		pointer to the private data
360
+ */
361
+struct spi_nor {
362
+	struct mtd_info		mtd;
363
+	struct mutex		lock;
364
+	struct device		*dev;
365
+	struct spi_mem		*spimem;
366
+	u8			*bouncebuf;
367
+	size_t			bouncebuf_size;
368
+	const struct flash_info	*info;
369
+	const struct spi_nor_manufacturer *manufacturer;
370
+	u32			page_size;
371
+	u8			addr_width;
372
+	u8			erase_opcode;
373
+	u8			read_opcode;
374
+	u8			read_dummy;
375
+	u8			program_opcode;
376
+	enum spi_nor_protocol	read_proto;
377
+	enum spi_nor_protocol	write_proto;
378
+	enum spi_nor_protocol	reg_proto;
379
+	bool			sst_write_second;
380
+	u32			flags;
381
+
382
+	const struct spi_nor_controller_ops *controller_ops;
383
+
384
+	struct spi_nor_flash_parameter *params;
385
+
386
+	struct {
387
+		struct spi_mem_dirmap_desc *rdesc;
388
+		struct spi_mem_dirmap_desc *wdesc;
389
+	} dirmap;
390
+
391
+	struct miscdevice *misc_dev;
392
+	void *priv;
393
+};
394
+
395
+static inline void spi_nor_set_flash_node(struct spi_nor *nor,
396
+					  struct device_node *np)
397
+{
398
+	mtd_set_of_node(&nor->mtd, np);
399
+}
400
+
401
+static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
402
+{
403
+	return mtd_get_of_node(&nor->mtd);
404
+}
405
+
392406 /**
393407  * spi_nor_scan() - scan the SPI NOR
394408  * @nor:	the spi_nor structure