| .. | .. |
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| 120 | 120 | { |
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| 121 | 121 | u32 R = 0, F = 0, OD = 0, ODIndex = 0; |
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| 122 | 122 | u32 ulBestR = 0, ulBestF = 0, ulBestOD = 0; |
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| 123 | | - u32 ulBestVCO = 0, ulBestClk = 0, ulBestScore = 0; |
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| 123 | + u32 ulBestClk = 0, ulBestScore = 0; |
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| 124 | 124 | u32 ulScore, ulPhaseScore, ulVcoScore; |
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| 125 | 125 | u32 ulTmp = 0, ulVCO; |
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| 126 | 126 | u32 ulScaleClockReq, ulMinClock, ulMaxClock; |
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| .. | .. |
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| 189 | 189 | ulScore = ulPhaseScore + ulVcoScore; |
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| 190 | 190 | |
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| 191 | 191 | if (!ulBestScore) { |
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| 192 | | - ulBestVCO = ulVCO; |
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| 193 | 192 | ulBestOD = OD; |
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| 194 | 193 | ulBestF = F; |
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| 195 | 194 | ulBestR = R; |
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| .. | .. |
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| 206 | 205 | but we shall keep this code in case new restrictions come into play |
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| 207 | 206 | --------------------------------------------------------------------------*/ |
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| 208 | 207 | if ((ulScore >= ulBestScore) && (OD > 0)) { |
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| 209 | | - ulBestVCO = ulVCO; |
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| 210 | 208 | ulBestOD = OD; |
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| 211 | 209 | ulBestF = F; |
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| 212 | 210 | ulBestR = R; |
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| .. | .. |
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| 244 | 242 | { |
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| 245 | 243 | u32 F, R, P; |
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| 246 | 244 | u16 core_pll = 0, sub; |
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| 247 | | - u32 ulCoreClock; |
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| 248 | 245 | u32 tmp; |
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| 249 | 246 | u32 ulChipSpeed; |
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| 250 | 247 | |
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| .. | .. |
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| 282 | 279 | if (ulChipSpeed == 0) |
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| 283 | 280 | return -EINVAL; |
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| 284 | 281 | |
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| 285 | | - ulCoreClock = ProgramClock(REF_FREQ, CORE_PLL_FREQ, &F, &R, &P); |
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| 282 | + ProgramClock(REF_FREQ, CORE_PLL_FREQ, &F, &R, &P); |
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| 286 | 283 | |
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| 287 | 284 | core_pll |= ((P) | ((F - 2) << 2) | ((R - 2) << 11)); |
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| 288 | 285 | |
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