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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/drivers/usb/mtu3/mtu3_core.c
..
..
@@ -16,6 +16,9 @@
16
16
 #include <linux/platform_device.h>
17
17
 
18
18
 #include "mtu3.h"
19
+#include "mtu3_dr.h"
20
+#include "mtu3_debug.h"
21
+#include "mtu3_trace.h"
19
22
 
20
23
 static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
21
24
 {
..
..
@@ -148,17 +151,6 @@
148
151
 	mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
149
152
 }
150
153
 
151
-/* disable all interrupts */
152
-static void mtu3_intr_disable(struct mtu3 *mtu)
153
-{
154
-	void __iomem *mbase = mtu->mac_base;
155
-
156
-	/* Disable level 1 interrupts */
157
-	mtu3_writel(mbase, U3D_LV1IECR, ~0x0);
158
-	/* Disable endpoint interrupts */
159
-	mtu3_writel(mbase, U3D_EPIECR, ~0x0);
160
-}
161
-
162
154
 static void mtu3_intr_status_clear(struct mtu3 *mtu)
163
155
 {
164
156
 	void __iomem *mbase = mtu->mac_base;
..
..
@@ -171,6 +163,18 @@
171
163
 	mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
172
164
 	/* Clear speed change interrupt status */
173
165
 	mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
166
+	/* Clear QMU interrupt status */
167
+	mtu3_writel(mbase, U3D_QISAR0, ~0x0);
168
+}
169
+
170
+/* disable all interrupts */
171
+static void mtu3_intr_disable(struct mtu3 *mtu)
172
+{
173
+	/* Disable level 1 interrupts */
174
+	mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0);
175
+	/* Disable endpoint interrupts */
176
+	mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0);
177
+	mtu3_intr_status_clear(mtu);
174
178
 }
175
179
 
176
180
 /* enable system global interrupt */
..
..
@@ -184,7 +188,7 @@
184
188
 	mtu3_writel(mbase, U3D_LV1IESR, value);
185
189
 
186
190
 	/* Enable U2 common USB interrupts */
187
-	value = SUSPEND_INTR | RESUME_INTR | RESET_INTR | LPM_RESUME_INTR;
191
+	value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
188
192
 	mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
189
193
 
190
194
 	if (mtu->is_u3_ip) {
..
..
@@ -201,6 +205,71 @@
201
205
 
202
206
 	/* Enable speed change interrupt */
203
207
 	mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
208
+}
209
+
210
+void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed)
211
+{
212
+	void __iomem *mbase = mtu->mac_base;
213
+
214
+	if (speed > mtu->max_speed)
215
+		speed = mtu->max_speed;
216
+
217
+	switch (speed) {
218
+	case USB_SPEED_FULL:
219
+		/* disable U3 SS function */
220
+		mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
221
+		/* disable HS function */
222
+		mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
223
+		break;
224
+	case USB_SPEED_HIGH:
225
+		mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
226
+		/* HS/FS detected by HW */
227
+		mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
228
+		break;
229
+	case USB_SPEED_SUPER:
230
+		mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
231
+		mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
232
+			     SSUSB_U3_PORT_SSP_SPEED);
233
+		break;
234
+	case USB_SPEED_SUPER_PLUS:
235
+		mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
236
+		mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
237
+			     SSUSB_U3_PORT_SSP_SPEED);
238
+		break;
239
+	default:
240
+		dev_err(mtu->dev, "invalid speed: %s\n",
241
+			usb_speed_string(speed));
242
+		return;
243
+	}
244
+
245
+	mtu->speed = speed;
246
+	dev_dbg(mtu->dev, "set speed: %s\n", usb_speed_string(speed));
247
+}
248
+
249
+/* CSR registers will be reset to default value if port is disabled */
250
+static void mtu3_csr_init(struct mtu3 *mtu)
251
+{
252
+	void __iomem *mbase = mtu->mac_base;
253
+
254
+	if (mtu->is_u3_ip) {
255
+		/* disable LGO_U1/U2 by default */
256
+		mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
257
+				SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
258
+		/* enable accept LGO_U1/U2 link command from host */
259
+		mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
260
+				SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
261
+		/* device responses to u3_exit from host automatically */
262
+		mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
263
+		/* automatically build U2 link when U3 detect fail */
264
+		mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
265
+		/* auto clear SOFT_CONN when clear USB3_EN if work as HS */
266
+		mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
267
+	}
268
+
269
+	/* delay about 0.1us from detecting reset to send chirp-K */
270
+	mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
271
+	/* enable automatical HWRW from L1 */
272
+	mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
204
273
 }
205
274
 
206
275
 /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
..
..
@@ -250,13 +319,13 @@
250
319
 
251
320
 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
252
321
 {
253
-	if (mtu->is_u3_ip && mtu->max_speed >= USB_SPEED_SUPER)
322
+	if (mtu->is_u3_ip && mtu->speed >= USB_SPEED_SUPER)
254
323
 		mtu3_ss_func_set(mtu, is_on);
255
324
 	else
256
325
 		mtu3_hs_softconn_set(mtu, is_on);
257
326
 
258
327
 	dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
259
-		usb_speed_string(mtu->max_speed), is_on ? "+" : "-");
328
+		usb_speed_string(mtu->speed), is_on ? "+" : "-");
260
329
 }
261
330
 
262
331
 void mtu3_start(struct mtu3 *mtu)
..
..
@@ -268,13 +337,8 @@
268
337
 
269
338
 	mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
270
339
 
271
-	/*
272
-	 * When disable U2 port, USB2_CSR's register will be reset to
273
-	 * default value after re-enable it again(HS is enabled by default).
274
-	 * So if force mac to work as FS, disable HS function.
275
-	 */
276
-	if (mtu->max_speed == USB_SPEED_FULL)
277
-		mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
340
+	mtu3_csr_init(mtu);
341
+	mtu3_set_speed(mtu, mtu->speed);
278
342
 
279
343
 	/* Initialize the default interrupts */
280
344
 	mtu3_intr_enable(mtu);
..
..
@@ -289,7 +353,6 @@
289
353
 	dev_dbg(mtu->dev, "%s\n", __func__);
290
354
 
291
355
 	mtu3_intr_disable(mtu);
292
-	mtu3_intr_status_clear(mtu);
293
356
 
294
357
 	if (mtu->softconnect)
295
358
 		mtu3_dev_on_off(mtu, 0);
..
..
@@ -303,6 +366,7 @@
303
366
 			int interval, int burst, int mult)
304
367
 {
305
368
 	void __iomem *mbase = mtu->mac_base;
369
+	bool gen2cp = mtu->gen2cp;
306
370
 	int epnum = mep->epnum;
307
371
 	u32 csr0, csr1, csr2;
308
372
 	int fifo_sgsz, fifo_addr;
..
..
@@ -323,7 +387,7 @@
323
387
 
324
388
 		num_pkts = (burst + 1) * (mult + 1) - 1;
325
389
 		csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
326
-		csr1 |= TX_MAX_PKT(num_pkts) | TX_MULT(mult);
390
+		csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
327
391
 
328
392
 		csr2 = TX_FIFOADDR(fifo_addr >> 4);
329
393
 		csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
..
..
@@ -359,7 +423,7 @@
359
423
 
360
424
 		num_pkts = (burst + 1) * (mult + 1) - 1;
361
425
 		csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
362
-		csr1 |= RX_MAX_PKT(num_pkts) | RX_MULT(mult);
426
+		csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
363
427
 
364
428
 		csr2 = RX_FIFOADDR(fifo_addr >> 4);
365
429
 		csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
..
..
@@ -488,7 +552,7 @@
488
552
 	mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
489
553
 
490
554
 	/* Enable EP0 interrupt */
491
-	mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR);
555
+	mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
492
556
 }
493
557
 
494
558
 static int mtu3_mem_alloc(struct mtu3 *mtu)
..
..
@@ -545,63 +609,22 @@
545
609
 	kfree(mtu->ep_array);
546
610
 }
547
611
 
548
-static void mtu3_set_speed(struct mtu3 *mtu)
549
-{
550
-	void __iomem *mbase = mtu->mac_base;
551
-
552
-	if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
553
-		mtu->max_speed = USB_SPEED_HIGH;
554
-
555
-	if (mtu->max_speed == USB_SPEED_FULL) {
556
-		/* disable U3 SS function */
557
-		mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
558
-		/* disable HS function */
559
-		mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
560
-	} else if (mtu->max_speed == USB_SPEED_HIGH) {
561
-		mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
562
-		/* HS/FS detected by HW */
563
-		mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
564
-	} else if (mtu->max_speed == USB_SPEED_SUPER) {
565
-		mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
566
-			     SSUSB_U3_PORT_SSP_SPEED);
567
-	}
568
-
569
-	dev_info(mtu->dev, "max_speed: %s\n",
570
-		usb_speed_string(mtu->max_speed));
571
-}
572
-
573
612
 static void mtu3_regs_init(struct mtu3 *mtu)
574
613
 {
575
-
576
614
 	void __iomem *mbase = mtu->mac_base;
577
615
 
578
616
 	/* be sure interrupts are disabled before registration of ISR */
579
617
 	mtu3_intr_disable(mtu);
580
-	mtu3_intr_status_clear(mtu);
581
618
 
582
-	if (mtu->is_u3_ip) {
583
-		/* disable LGO_U1/U2 by default */
584
-		mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
585
-				SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
586
-		/* enable accept LGO_U1/U2 link command from host */
587
-		mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
588
-				SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
589
-		/* device responses to u3_exit from host automatically */
590
-		mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
591
-		/* automatically build U2 link when U3 detect fail */
592
-		mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
593
-	}
619
+	mtu3_csr_init(mtu);
594
620
 
595
-	mtu3_set_speed(mtu);
596
-
597
-	/* delay about 0.1us from detecting reset to send chirp-K */
598
-	mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
599
621
 	/* U2/U3 detected by HW */
600
622
 	mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
601
-	/* enable QMU 16B checksum */
602
-	mtu3_setbits(mbase, U3D_QCR0, QMU_CS16B_EN);
603
623
 	/* vbus detected by HW */
604
624
 	mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
625
+	/* use new QMU format when HW version >= 0x1003 */
626
+	if (mtu->gen2cp)
627
+		mtu3_writel(mbase, U3D_QFCR, ~0x0);
605
628
 }
606
629
 
607
630
 static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
..
..
@@ -652,6 +675,8 @@
652
675
 		break;
653
676
 	}
654
677
 	dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
678
+	mtu3_dbg_trace(mtu->dev, "link speed %s",
679
+		       usb_speed_string(udev_speed));
655
680
 
656
681
 	mtu->g.speed = udev_speed;
657
682
 	mtu->g.ep0->maxpacket = maxpkt;
..
..
@@ -674,6 +699,7 @@
674
699
 	ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
675
700
 	mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
676
701
 	dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
702
+	trace_mtu3_u3_ltssm_isr(ltssm);
677
703
 
678
704
 	if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
679
705
 		mtu3_gadget_reset(mtu);
..
..
@@ -704,6 +730,7 @@
704
730
 	u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
705
731
 	mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
706
732
 	dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
733
+	trace_mtu3_u2_common_isr(u2comm);
707
734
 
708
735
 	if (u2comm & SUSPEND_INTR)
709
736
 		mtu3_gadget_suspend(mtu);
..
..
@@ -713,12 +740,6 @@
713
740
 
714
741
 	if (u2comm & RESET_INTR)
715
742
 		mtu3_gadget_reset(mtu);
716
-
717
-	if (u2comm & LPM_RESUME_INTR) {
718
-		if (!(mtu3_readl(mbase, U3D_POWER_MANAGEMENT) & LPM_HRWE))
719
-			mtu3_setbits(mbase, U3D_USB20_MISC_CONTROL,
720
-				     LPM_U3_ACK_EN);
721
-	}
722
743
 
723
744
 	return IRQ_HANDLED;
724
745
 }
..
..
@@ -755,18 +776,50 @@
755
776
 	return IRQ_HANDLED;
756
777
 }
757
778
 
779
+static void mtu3_check_params(struct mtu3 *mtu)
780
+{
781
+	/* check the max_speed parameter */
782
+	switch (mtu->max_speed) {
783
+	case USB_SPEED_FULL:
784
+	case USB_SPEED_HIGH:
785
+	case USB_SPEED_SUPER:
786
+	case USB_SPEED_SUPER_PLUS:
787
+		break;
788
+	default:
789
+		dev_err(mtu->dev, "invalid max_speed: %s\n",
790
+			usb_speed_string(mtu->max_speed));
791
+		fallthrough;
792
+	case USB_SPEED_UNKNOWN:
793
+		/* default as SSP */
794
+		mtu->max_speed = USB_SPEED_SUPER_PLUS;
795
+		break;
796
+	}
797
+
798
+	if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
799
+		mtu->max_speed = USB_SPEED_HIGH;
800
+
801
+	mtu->speed = mtu->max_speed;
802
+
803
+	dev_info(mtu->dev, "max_speed: %s\n",
804
+		 usb_speed_string(mtu->max_speed));
805
+}
806
+
758
807
 static int mtu3_hw_init(struct mtu3 *mtu)
759
808
 {
760
-	u32 cap_dev;
809
+	u32 value;
761
810
 	int ret;
762
811
 
763
-	mtu->hw_version = mtu3_readl(mtu->ippc_base, U3D_SSUSB_HW_ID);
812
+	value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
813
+	mtu->hw_version = IP_TRUNK_VERS(value);
814
+	mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
764
815
 
765
-	cap_dev = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
766
-	mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(cap_dev);
816
+	value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
817
+	mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
767
818
 
768
819
 	dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
769
820
 		mtu->is_u3_ip ? "U3" : "U2");
821
+
822
+	mtu3_check_params(mtu);
770
823
 
771
824
 	mtu3_device_reset(mtu);
772
825
 
..
..
@@ -791,7 +844,7 @@
791
844
 	mtu3_mem_free(mtu);
792
845
 }
793
846
 
794
-/**
847
+/*
795
848
  * we set 32-bit DMA mask by default, here check whether the controller
796
849
  * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
797
850
  */
..
..
@@ -822,7 +875,6 @@
822
875
 	struct device *dev = ssusb->dev;
823
876
 	struct platform_device *pdev = to_platform_device(dev);
824
877
 	struct mtu3 *mtu = NULL;
825
-	struct resource *res;
826
878
 	int ret = -ENOMEM;
827
879
 
828
880
 	mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
..
..
@@ -830,14 +882,11 @@
830
882
 		return -ENOMEM;
831
883
 
832
884
 	mtu->irq = platform_get_irq(pdev, 0);
833
-	if (mtu->irq < 0) {
834
-		dev_err(dev, "fail to get irq number\n");
885
+	if (mtu->irq < 0)
835
886
 		return mtu->irq;
836
-	}
837
887
 	dev_info(dev, "irq %d\n", mtu->irq);
838
888
 
839
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
840
-	mtu->mac_base = devm_ioremap_resource(dev, res);
889
+	mtu->mac_base = devm_platform_ioremap_resource_byname(pdev, "mac");
841
890
 	if (IS_ERR(mtu->mac_base)) {
842
891
 		dev_err(dev, "error mapping memory for dev mac\n");
843
892
 		return PTR_ERR(mtu->mac_base);
..
..
@@ -850,23 +899,6 @@
850
899
 	ssusb->u3d = mtu;
851
900
 	mtu->ssusb = ssusb;
852
901
 	mtu->max_speed = usb_get_maximum_speed(dev);
853
-
854
-	/* check the max_speed parameter */
855
-	switch (mtu->max_speed) {
856
-	case USB_SPEED_FULL:
857
-	case USB_SPEED_HIGH:
858
-	case USB_SPEED_SUPER:
859
-	case USB_SPEED_SUPER_PLUS:
860
-		break;
861
-	default:
862
-		dev_err(dev, "invalid max_speed: %s\n",
863
-			usb_speed_string(mtu->max_speed));
864
-		/* fall through */
865
-	case USB_SPEED_UNKNOWN:
866
-		/* default as SSP */
867
-		mtu->max_speed = USB_SPEED_SUPER_PLUS;
868
-		break;
869
-	}
870
902
 
871
903
 	dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
872
904
 		mtu->mac_base, mtu->ippc_base);
..
..
@@ -901,6 +933,8 @@
901
933
 	if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
902
934
 		mtu3_stop(mtu);
903
935
 
936
+	ssusb_dev_debugfs_init(ssusb);
937
+
904
938
 	dev_dbg(dev, " %s() done...\n", __func__);
905
939
 
906
940
 	return 0;