~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0
1	2	/*
2	3	* Intel Core SoC Power Management Controller Driver
3	4	*
..	..	@@ -6,44 +7,50 @@
6	7	*
7	8	* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
8	9	* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
9		- *
10		- * This program is free software; you can redistribute it and/or modify it
11		- * under the terms and conditions of the GNU General Public License,
12		- * version 2, as published by the Free Software Foundation.
13		- *
14		- * This program is distributed in the hope it will be useful, but WITHOUT
15		- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16		- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17		- * more details.
18		- *
19	10	*/
20	11
21	12	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22	13
23	14	#include <linux/acpi.h>
	15	+#include <linux/bitfield.h>
24	16	#include <linux/debugfs.h>
25	17	#include <linux/delay.h>
	18	+#include <linux/dmi.h>
26	19	#include <linux/io.h>
27	20	#include <linux/module.h>
28	21	#include <linux/pci.h>
	22	+#include <linux/platform_device.h>
	23	+#include <linux/slab.h>
	24	+#include <linux/suspend.h>
29	25	#include <linux/uaccess.h>
30	26
31	27	#include <asm/cpu_device_id.h>
32	28	#include <asm/intel-family.h>
	29	+#include <asm/msr.h>
	30	+#include <asm/tsc.h>
33	31
34	32	#include "intel_pmc_core.h"
35	33
36		-#define ICPU(model, data) \
37		- { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (kernel_ulong_t)data }
38		-
39	34	static struct pmc_dev pmc;
	35	+
	36	+/* PKGC MSRs are common across Intel Core SoCs */
	37	+static const struct pmc_bit_map msr_map[] = {
	38	+ {"Package C2", MSR_PKG_C2_RESIDENCY},
	39	+ {"Package C3", MSR_PKG_C3_RESIDENCY},
	40	+ {"Package C6", MSR_PKG_C6_RESIDENCY},
	41	+ {"Package C7", MSR_PKG_C7_RESIDENCY},
	42	+ {"Package C8", MSR_PKG_C8_RESIDENCY},
	43	+ {"Package C9", MSR_PKG_C9_RESIDENCY},
	44	+ {"Package C10", MSR_PKG_C10_RESIDENCY},
	45	+ {}
	46	+};
40	47
41	48	static const struct pmc_bit_map spt_pll_map[] = {
42	49	{"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
43	50	{"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
44	51	{"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
45	52	{"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
46		- {},
	53	+ {}
47	54	};
48	55
49	56	static const struct pmc_bit_map spt_mphy_map[] = {
..	..	@@ -63,7 +70,7 @@
63	70	{"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
64	71	{"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
65	72	{"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
66		- {},
	73	+ {}
67	74	};
68	75
69	76	static const struct pmc_bit_map spt_pfear_map[] = {
..	..	@@ -107,23 +114,62 @@
107	114	{"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
108	115	{"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
109	116	{"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
110		- {},
	117	+ {}
	118	+};
	119	+
	120	+static const struct pmc_bit_map *ext_spt_pfear_map[] = {
	121	+ /*
	122	+ * Check intel_pmc_core_ids[] users of spt_reg_map for
	123	+ * a list of core SoCs using this.
	124	+ */
	125	+ spt_pfear_map,
	126	+ NULL
	127	+};
	128	+
	129	+static const struct pmc_bit_map spt_ltr_show_map[] = {
	130	+ {"SOUTHPORT_A", SPT_PMC_LTR_SPA},
	131	+ {"SOUTHPORT_B", SPT_PMC_LTR_SPB},
	132	+ {"SATA", SPT_PMC_LTR_SATA},
	133	+ {"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
	134	+ {"XHCI", SPT_PMC_LTR_XHCI},
	135	+ {"Reserved", SPT_PMC_LTR_RESERVED},
	136	+ {"ME", SPT_PMC_LTR_ME},
	137	+ /* EVA is Enterprise Value Add, doesn't really exist on PCH */
	138	+ {"EVA", SPT_PMC_LTR_EVA},
	139	+ {"SOUTHPORT_C", SPT_PMC_LTR_SPC},
	140	+ {"HD_AUDIO", SPT_PMC_LTR_AZ},
	141	+ {"LPSS", SPT_PMC_LTR_LPSS},
	142	+ {"SOUTHPORT_D", SPT_PMC_LTR_SPD},
	143	+ {"SOUTHPORT_E", SPT_PMC_LTR_SPE},
	144	+ {"CAMERA", SPT_PMC_LTR_CAM},
	145	+ {"ESPI", SPT_PMC_LTR_ESPI},
	146	+ {"SCC", SPT_PMC_LTR_SCC},
	147	+ {"ISH", SPT_PMC_LTR_ISH},
	148	+ /* Below two cannot be used for LTR_IGNORE */
	149	+ {"CURRENT_PLATFORM", SPT_PMC_LTR_CUR_PLT},
	150	+ {"AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
	151	+ {}
111	152	};
112	153
113	154	static const struct pmc_reg_map spt_reg_map = {
114		- .pfear_sts = spt_pfear_map,
	155	+ .pfear_sts = ext_spt_pfear_map,
115	156	.mphy_sts = spt_mphy_map,
116	157	.pll_sts = spt_pll_map,
	158	+ .ltr_show_sts = spt_ltr_show_map,
	159	+ .msr_sts = msr_map,
117	160	.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
	161	+ .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
118	162	.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
119	163	.regmap_length = SPT_PMC_MMIO_REG_LEN,
120	164	.ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
121	165	.ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
122	166	.pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
123	167	.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
	168	+ .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
	169	+ .pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
124	170	};
125	171
126		-/* Cannonlake: PGD PFET Enable Ack Status Register(s) bitmap */
	172	+/* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
127	173	static const struct pmc_bit_map cnp_pfear_map[] = {
128	174	{"PMC", BIT(0)},
129	175	{"OPI-DMI", BIT(1)},
..	..	@@ -150,25 +196,25 @@
150	196	{"SDX", BIT(4)},
151	197	{"SPE", BIT(5)},
152	198	{"Fuse", BIT(6)},
153		- {"Res_23", BIT(7)},
	199	+ {"SBR8", BIT(7)},
154	200
155	201	{"CSME_FSC", BIT(0)},
156	202	{"USB3_OTG", BIT(1)},
157	203	{"EXI", BIT(2)},
158	204	{"CSE", BIT(3)},
159		- {"csme_kvm", BIT(4)},
160		- {"csme_pmt", BIT(5)},
161		- {"csme_clink", BIT(6)},
162		- {"csme_ptio", BIT(7)},
	205	+ {"CSME_KVM", BIT(4)},
	206	+ {"CSME_PMT", BIT(5)},
	207	+ {"CSME_CLINK", BIT(6)},
	208	+ {"CSME_PTIO", BIT(7)},
163	209
164		- {"csme_usbr", BIT(0)},
165		- {"csme_susram", BIT(1)},
166		- {"csme_smt1", BIT(2)},
	210	+ {"CSME_USBR", BIT(0)},
	211	+ {"CSME_SUSRAM", BIT(1)},
	212	+ {"CSME_SMT1", BIT(2)},
167	213	{"CSME_SMT4", BIT(3)},
168		- {"csme_sms2", BIT(4)},
169		- {"csme_sms1", BIT(5)},
170		- {"csme_rtc", BIT(6)},
171		- {"csme_psf", BIT(7)},
	214	+ {"CSME_SMS2", BIT(4)},
	215	+ {"CSME_SMS1", BIT(5)},
	216	+ {"CSME_RTC", BIT(6)},
	217	+ {"CSME_PSF", BIT(7)},
172	218
173	219	{"SBR0", BIT(0)},
174	220	{"SBR1", BIT(1)},
..	..	@@ -193,7 +239,62 @@
193	239	{"HDA_PGD4", BIT(2)},
194	240	{"HDA_PGD5", BIT(3)},
195	241	{"HDA_PGD6", BIT(4)},
	242	+ {"PSF6", BIT(5)},
	243	+ {"PSF7", BIT(6)},
	244	+ {"PSF8", BIT(7)},
196	245	{}
	246	+};
	247	+
	248	+static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
	249	+ /*
	250	+ * Check intel_pmc_core_ids[] users of cnp_reg_map for
	251	+ * a list of core SoCs using this.
	252	+ */
	253	+ cnp_pfear_map,
	254	+ NULL
	255	+};
	256	+
	257	+static const struct pmc_bit_map icl_pfear_map[] = {
	258	+ {"RES_65", BIT(0)},
	259	+ {"RES_66", BIT(1)},
	260	+ {"RES_67", BIT(2)},
	261	+ {"TAM", BIT(3)},
	262	+ {"GBETSN", BIT(4)},
	263	+ {"TBTLSX", BIT(5)},
	264	+ {"RES_71", BIT(6)},
	265	+ {"RES_72", BIT(7)},
	266	+ {}
	267	+};
	268	+
	269	+static const struct pmc_bit_map *ext_icl_pfear_map[] = {
	270	+ /*
	271	+ * Check intel_pmc_core_ids[] users of icl_reg_map for
	272	+ * a list of core SoCs using this.
	273	+ */
	274	+ cnp_pfear_map,
	275	+ icl_pfear_map,
	276	+ NULL
	277	+};
	278	+
	279	+static const struct pmc_bit_map tgl_pfear_map[] = {
	280	+ {"PSF9", BIT(0)},
	281	+ {"RES_66", BIT(1)},
	282	+ {"RES_67", BIT(2)},
	283	+ {"RES_68", BIT(3)},
	284	+ {"RES_69", BIT(4)},
	285	+ {"RES_70", BIT(5)},
	286	+ {"TBTLSX", BIT(6)},
	287	+ {}
	288	+};
	289	+
	290	+static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
	291	+ /*
	292	+ * Check intel_pmc_core_ids[] users of tgl_reg_map for
	293	+ * a list of core SoCs using this.
	294	+ */
	295	+ cnp_pfear_map,
	296	+ tgl_pfear_map,
	297	+ NULL
197	298	};
198	299
199	300	static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
..	..	@@ -249,13 +350,49 @@
249	350	cnp_slps0_dbg0_map,
250	351	cnp_slps0_dbg1_map,
251	352	cnp_slps0_dbg2_map,
252		- NULL,
	353	+ NULL
	354	+};
	355	+
	356	+static const struct pmc_bit_map cnp_ltr_show_map[] = {
	357	+ {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
	358	+ {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
	359	+ {"SATA", CNP_PMC_LTR_SATA},
	360	+ {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
	361	+ {"XHCI", CNP_PMC_LTR_XHCI},
	362	+ {"Reserved", CNP_PMC_LTR_RESERVED},
	363	+ {"ME", CNP_PMC_LTR_ME},
	364	+ /* EVA is Enterprise Value Add, doesn't really exist on PCH */
	365	+ {"EVA", CNP_PMC_LTR_EVA},
	366	+ {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
	367	+ {"HD_AUDIO", CNP_PMC_LTR_AZ},
	368	+ {"CNV", CNP_PMC_LTR_CNV},
	369	+ {"LPSS", CNP_PMC_LTR_LPSS},
	370	+ {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
	371	+ {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
	372	+ {"CAMERA", CNP_PMC_LTR_CAM},
	373	+ {"ESPI", CNP_PMC_LTR_ESPI},
	374	+ {"SCC", CNP_PMC_LTR_SCC},
	375	+ {"ISH", CNP_PMC_LTR_ISH},
	376	+ {"UFSX2", CNP_PMC_LTR_UFSX2},
	377	+ {"EMMC", CNP_PMC_LTR_EMMC},
	378	+ /*
	379	+ * Check intel_pmc_core_ids[] users of cnp_reg_map for
	380	+ * a list of core SoCs using this.
	381	+ */
	382	+ {"WIGIG", ICL_PMC_LTR_WIGIG},
	383	+ /* Below two cannot be used for LTR_IGNORE */
	384	+ {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
	385	+ {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
	386	+ {}
253	387	};
254	388
255	389	static const struct pmc_reg_map cnp_reg_map = {
256		- .pfear_sts = cnp_pfear_map,
	390	+ .pfear_sts = ext_cnp_pfear_map,
257	391	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
	392	+ .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
258	393	.slps0_dbg_maps = cnp_slps0_dbg_maps,
	394	+ .ltr_show_sts = cnp_ltr_show_map,
	395	+ .msr_sts = msr_map,
259	396	.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
260	397	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
261	398	.regmap_length = CNP_PMC_MMIO_REG_LEN,
..	..	@@ -263,27 +400,207 @@
263	400	.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
264	401	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
265	402	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
	403	+ .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
266	404	};
267	405
268		-static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
269		-{
270		- return readb(pmcdev->regbase + offset);
271		-}
	406	+static const struct pmc_reg_map icl_reg_map = {
	407	+ .pfear_sts = ext_icl_pfear_map,
	408	+ .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
	409	+ .slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,
	410	+ .slps0_dbg_maps = cnp_slps0_dbg_maps,
	411	+ .ltr_show_sts = cnp_ltr_show_map,
	412	+ .msr_sts = msr_map,
	413	+ .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
	414	+ .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
	415	+ .regmap_length = CNP_PMC_MMIO_REG_LEN,
	416	+ .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
	417	+ .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
	418	+ .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
	419	+ .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
	420	+ .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
	421	+};
	422	+
	423	+static const struct pmc_bit_map tgl_clocksource_status_map[] = {
	424	+ {"USB2PLL_OFF_STS", BIT(18)},
	425	+ {"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)},
	426	+ {"PCIe_Gen3PLL_OFF_STS", BIT(20)},
	427	+ {"OPIOPLL_OFF_STS", BIT(21)},
	428	+ {"OCPLL_OFF_STS", BIT(22)},
	429	+ {"MainPLL_OFF_STS", BIT(23)},
	430	+ {"MIPIPLL_OFF_STS", BIT(24)},
	431	+ {"Fast_XTAL_Osc_OFF_STS", BIT(25)},
	432	+ {"AC_Ring_Osc_OFF_STS", BIT(26)},
	433	+ {"MC_Ring_Osc_OFF_STS", BIT(27)},
	434	+ {"SATAPLL_OFF_STS", BIT(29)},
	435	+ {"XTAL_USB2PLL_OFF_STS", BIT(31)},
	436	+ {}
	437	+};
	438	+
	439	+static const struct pmc_bit_map tgl_power_gating_status_map[] = {
	440	+ {"CSME_PG_STS", BIT(0)},
	441	+ {"SATA_PG_STS", BIT(1)},
	442	+ {"xHCI_PG_STS", BIT(2)},
	443	+ {"UFSX2_PG_STS", BIT(3)},
	444	+ {"OTG_PG_STS", BIT(5)},
	445	+ {"SPA_PG_STS", BIT(6)},
	446	+ {"SPB_PG_STS", BIT(7)},
	447	+ {"SPC_PG_STS", BIT(8)},
	448	+ {"SPD_PG_STS", BIT(9)},
	449	+ {"SPE_PG_STS", BIT(10)},
	450	+ {"SPF_PG_STS", BIT(11)},
	451	+ {"LSX_PG_STS", BIT(13)},
	452	+ {"P2SB_PG_STS", BIT(14)},
	453	+ {"PSF_PG_STS", BIT(15)},
	454	+ {"SBR_PG_STS", BIT(16)},
	455	+ {"OPIDMI_PG_STS", BIT(17)},
	456	+ {"THC0_PG_STS", BIT(18)},
	457	+ {"THC1_PG_STS", BIT(19)},
	458	+ {"GBETSN_PG_STS", BIT(20)},
	459	+ {"GBE_PG_STS", BIT(21)},
	460	+ {"LPSS_PG_STS", BIT(22)},
	461	+ {"MMP_UFSX2_PG_STS", BIT(23)},
	462	+ {"MMP_UFSX2B_PG_STS", BIT(24)},
	463	+ {"FIA_PG_STS", BIT(25)},
	464	+ {}
	465	+};
	466	+
	467	+static const struct pmc_bit_map tgl_d3_status_map[] = {
	468	+ {"ADSP_D3_STS", BIT(0)},
	469	+ {"SATA_D3_STS", BIT(1)},
	470	+ {"xHCI0_D3_STS", BIT(2)},
	471	+ {"xDCI1_D3_STS", BIT(5)},
	472	+ {"SDX_D3_STS", BIT(6)},
	473	+ {"EMMC_D3_STS", BIT(7)},
	474	+ {"IS_D3_STS", BIT(8)},
	475	+ {"THC0_D3_STS", BIT(9)},
	476	+ {"THC1_D3_STS", BIT(10)},
	477	+ {"GBE_D3_STS", BIT(11)},
	478	+ {"GBE_TSN_D3_STS", BIT(12)},
	479	+ {}
	480	+};
	481	+
	482	+static const struct pmc_bit_map tgl_vnn_req_status_map[] = {
	483	+ {"GPIO_COM0_VNN_REQ_STS", BIT(1)},
	484	+ {"GPIO_COM1_VNN_REQ_STS", BIT(2)},
	485	+ {"GPIO_COM2_VNN_REQ_STS", BIT(3)},
	486	+ {"GPIO_COM3_VNN_REQ_STS", BIT(4)},
	487	+ {"GPIO_COM4_VNN_REQ_STS", BIT(5)},
	488	+ {"GPIO_COM5_VNN_REQ_STS", BIT(6)},
	489	+ {"Audio_VNN_REQ_STS", BIT(7)},
	490	+ {"ISH_VNN_REQ_STS", BIT(8)},
	491	+ {"CNVI_VNN_REQ_STS", BIT(9)},
	492	+ {"eSPI_VNN_REQ_STS", BIT(10)},
	493	+ {"Display_VNN_REQ_STS", BIT(11)},
	494	+ {"DTS_VNN_REQ_STS", BIT(12)},
	495	+ {"SMBUS_VNN_REQ_STS", BIT(14)},
	496	+ {"CSME_VNN_REQ_STS", BIT(15)},
	497	+ {"SMLINK0_VNN_REQ_STS", BIT(16)},
	498	+ {"SMLINK1_VNN_REQ_STS", BIT(17)},
	499	+ {"CLINK_VNN_REQ_STS", BIT(20)},
	500	+ {"DCI_VNN_REQ_STS", BIT(21)},
	501	+ {"ITH_VNN_REQ_STS", BIT(22)},
	502	+ {"CSME_VNN_REQ_STS", BIT(24)},
	503	+ {"GBE_VNN_REQ_STS", BIT(25)},
	504	+ {}
	505	+};
	506	+
	507	+static const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
	508	+ {"CPU_C10_REQ_STS_0", BIT(0)},
	509	+ {"PCIe_LPM_En_REQ_STS_3", BIT(3)},
	510	+ {"ITH_REQ_STS_5", BIT(5)},
	511	+ {"CNVI_REQ_STS_6", BIT(6)},
	512	+ {"ISH_REQ_STS_7", BIT(7)},
	513	+ {"USB2_SUS_PG_Sys_REQ_STS_10", BIT(10)},
	514	+ {"PCIe_Clk_REQ_STS_12", BIT(12)},
	515	+ {"MPHY_Core_DL_REQ_STS_16", BIT(16)},
	516	+ {"Break-even_En_REQ_STS_17", BIT(17)},
	517	+ {"Auto-demo_En_REQ_STS_18", BIT(18)},
	518	+ {"MPHY_SUS_REQ_STS_22", BIT(22)},
	519	+ {"xDCI_attached_REQ_STS_24", BIT(24)},
	520	+ {}
	521	+};
	522	+
	523	+static const struct pmc_bit_map tgl_signal_status_map[] = {
	524	+ {"LSX_Wake0_En_STS", BIT(0)},
	525	+ {"LSX_Wake0_Pol_STS", BIT(1)},
	526	+ {"LSX_Wake1_En_STS", BIT(2)},
	527	+ {"LSX_Wake1_Pol_STS", BIT(3)},
	528	+ {"LSX_Wake2_En_STS", BIT(4)},
	529	+ {"LSX_Wake2_Pol_STS", BIT(5)},
	530	+ {"LSX_Wake3_En_STS", BIT(6)},
	531	+ {"LSX_Wake3_Pol_STS", BIT(7)},
	532	+ {"LSX_Wake4_En_STS", BIT(8)},
	533	+ {"LSX_Wake4_Pol_STS", BIT(9)},
	534	+ {"LSX_Wake5_En_STS", BIT(10)},
	535	+ {"LSX_Wake5_Pol_STS", BIT(11)},
	536	+ {"LSX_Wake6_En_STS", BIT(12)},
	537	+ {"LSX_Wake6_Pol_STS", BIT(13)},
	538	+ {"LSX_Wake7_En_STS", BIT(14)},
	539	+ {"LSX_Wake7_Pol_STS", BIT(15)},
	540	+ {"Intel_Se_IO_Wake0_En_STS", BIT(16)},
	541	+ {"Intel_Se_IO_Wake0_Pol_STS", BIT(17)},
	542	+ {"Intel_Se_IO_Wake1_En_STS", BIT(18)},
	543	+ {"Intel_Se_IO_Wake1_Pol_STS", BIT(19)},
	544	+ {"Int_Timer_SS_Wake0_En_STS", BIT(20)},
	545	+ {"Int_Timer_SS_Wake0_Pol_STS", BIT(21)},
	546	+ {"Int_Timer_SS_Wake1_En_STS", BIT(22)},
	547	+ {"Int_Timer_SS_Wake1_Pol_STS", BIT(23)},
	548	+ {"Int_Timer_SS_Wake2_En_STS", BIT(24)},
	549	+ {"Int_Timer_SS_Wake2_Pol_STS", BIT(25)},
	550	+ {"Int_Timer_SS_Wake3_En_STS", BIT(26)},
	551	+ {"Int_Timer_SS_Wake3_Pol_STS", BIT(27)},
	552	+ {"Int_Timer_SS_Wake4_En_STS", BIT(28)},
	553	+ {"Int_Timer_SS_Wake4_Pol_STS", BIT(29)},
	554	+ {"Int_Timer_SS_Wake5_En_STS", BIT(30)},
	555	+ {"Int_Timer_SS_Wake5_Pol_STS", BIT(31)},
	556	+ {}
	557	+};
	558	+
	559	+static const struct pmc_bit_map *tgl_lpm_maps[] = {
	560	+ tgl_clocksource_status_map,
	561	+ tgl_power_gating_status_map,
	562	+ tgl_d3_status_map,
	563	+ tgl_vnn_req_status_map,
	564	+ tgl_vnn_misc_status_map,
	565	+ tgl_signal_status_map,
	566	+ NULL
	567	+};
	568	+
	569	+static const struct pmc_reg_map tgl_reg_map = {
	570	+ .pfear_sts = ext_tgl_pfear_map,
	571	+ .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
	572	+ .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
	573	+ .ltr_show_sts = cnp_ltr_show_map,
	574	+ .msr_sts = msr_map,
	575	+ .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
	576	+ .regmap_length = CNP_PMC_MMIO_REG_LEN,
	577	+ .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
	578	+ .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
	579	+ .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
	580	+ .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
	581	+ .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
	582	+ .lpm_modes = tgl_lpm_modes,
	583	+ .lpm_en_offset = TGL_LPM_EN_OFFSET,
	584	+ .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
	585	+ .lpm_sts = tgl_lpm_maps,
	586	+ .lpm_status_offset = TGL_LPM_STATUS_OFFSET,
	587	+ .lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET,
	588	+};
272	589
273	590	static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
274	591	{
275	592	return readl(pmcdev->regbase + reg_offset);
276	593	}
277	594
278		-static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
279		- reg_offset, u32 val)
	595	+static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
	596	+ u32 val)
280	597	{
281	598	writel(val, pmcdev->regbase + reg_offset);
282	599	}
283	600
284		-static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
	601	+static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
285	602	{
286		- return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
	603	+ return (u64)value * pmcdev->map->slp_s0_res_counter_step;
287	604	}
288	605
289	606	static int pmc_core_dev_state_get(void data, u64 val)
..	..	@@ -293,7 +610,7 @@
293	610	u32 value;
294	611
295	612	value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
296		- *val = pmc_core_adjust_slp_s0_step(value);
	613	+ *val = pmc_core_adjust_slp_s0_step(pmcdev, value);
297	614
298	615	return 0;
299	616	}
..	..	@@ -309,23 +626,105 @@
309	626	return value & BIT(pmcdev->map->pm_read_disable_bit);
310	627	}
311	628
312		-#if IS_ENABLED(CONFIG_DEBUG_FS)
313		-static bool slps0_dbg_latch;
314		-
315		-static void pmc_core_display_map(struct seq_file *s, int index,
316		- u8 pf_reg, const struct pmc_bit_map *pf_map)
	629	+static void pmc_core_slps0_display(struct pmc_dev pmcdev, struct device dev,
	630	+ struct seq_file *s)
317	631	{
318		- seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
319		- index, pf_map[index].name,
320		- pf_map[index].bit_mask & pf_reg ? "Off" : "On");
	632	+ const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
	633	+ const struct pmc_bit_map *map;
	634	+ int offset = pmcdev->map->slps0_dbg_offset;
	635	+ u32 data;
	636	+
	637	+ while (*maps) {
	638	+ map = *maps;
	639	+ data = pmc_core_reg_read(pmcdev, offset);
	640	+ offset += 4;
	641	+ while (map->name) {
	642	+ if (dev)
	643	+ dev_info(dev, "SLP_S0_DBG: %-32s\tState: %s\n",
	644	+ map->name,
	645	+ data & map->bit_mask ? "Yes" : "No");
	646	+ if (s)
	647	+ seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
	648	+ map->name,
	649	+ data & map->bit_mask ? "Yes" : "No");
	650	+ ++map;
	651	+ }
	652	+ ++maps;
	653	+ }
321	654	}
322	655
323		-static int pmc_core_ppfear_sts_show(struct seq_file s, void unused)
	656	+static int pmc_core_lpm_get_arr_size(const struct pmc_bit_map **maps)
	657	+{
	658	+ int idx;
	659	+
	660	+ for (idx = 0; maps[idx]; idx++)
	661	+ ;/* Nothing */
	662	+
	663	+ return idx;
	664	+}
	665	+
	666	+static void pmc_core_lpm_display(struct pmc_dev pmcdev, struct device dev,
	667	+ struct seq_file *s, u32 offset,
	668	+ const char *str,
	669	+ const struct pmc_bit_map **maps)
	670	+{
	671	+ int index, idx, len = 32, bit_mask, arr_size;
	672	+ u32 *lpm_regs;
	673	+
	674	+ arr_size = pmc_core_lpm_get_arr_size(maps);
	675	+ lpm_regs = kmalloc_array(arr_size, sizeof(*lpm_regs), GFP_KERNEL);
	676	+ if (!lpm_regs)
	677	+ return;
	678	+
	679	+ for (index = 0; index < arr_size; index++) {
	680	+ lpm_regs[index] = pmc_core_reg_read(pmcdev, offset);
	681	+ offset += 4;
	682	+ }
	683	+
	684	+ for (idx = 0; idx < arr_size; idx++) {
	685	+ if (dev)
	686	+ dev_info(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx,
	687	+ lpm_regs[idx]);
	688	+ if (s)
	689	+ seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx,
	690	+ lpm_regs[idx]);
	691	+ for (index = 0; maps[idx][index].name && index < len; index++) {
	692	+ bit_mask = maps[idx][index].bit_mask;
	693	+ if (dev)
	694	+ dev_info(dev, "%-30s %-30d\n",
	695	+ maps[idx][index].name,
	696	+ lpm_regs[idx] & bit_mask ? 1 : 0);
	697	+ if (s)
	698	+ seq_printf(s, "%-30s %-30d\n",
	699	+ maps[idx][index].name,
	700	+ lpm_regs[idx] & bit_mask ? 1 : 0);
	701	+ }
	702	+ }
	703	+
	704	+ kfree(lpm_regs);
	705	+}
	706	+
	707	+static bool slps0_dbg_latch;
	708	+
	709	+static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
	710	+{
	711	+ return readb(pmcdev->regbase + offset);
	712	+}
	713	+
	714	+static void pmc_core_display_map(struct seq_file *s, int index, int idx, int ip,
	715	+ u8 pf_reg, const struct pmc_bit_map **pf_map)
	716	+{
	717	+ seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
	718	+ ip, pf_map[idx][index].name,
	719	+ pf_map[idx][index].bit_mask & pf_reg ? "Off" : "On");
	720	+}
	721	+
	722	+static int pmc_core_ppfear_show(struct seq_file s, void unused)
324	723	{
325	724	struct pmc_dev *pmcdev = s->private;
326		- const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
	725	+ const struct pmc_bit_map **maps = pmcdev->map->pfear_sts;
327	726	u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
328		- int index, iter;
	727	+ int index, iter, idx, ip = 0;
329	728
330	729	iter = pmcdev->map->ppfear0_offset;
331	730
..	..	@@ -333,24 +732,16 @@
333	732	index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
334	733	pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
335	734
336		- for (index = 0; map[index].name &&
337		- index < pmcdev->map->ppfear_buckets * 8; index++)
338		- pmc_core_display_map(s, index, pf_regs[index / 8], map);
	735	+ for (idx = 0; maps[idx]; idx++) {
	736	+ for (index = 0; maps[idx][index].name &&
	737	+ index < pmcdev->map->ppfear_buckets * 8; ip++, index++)
	738	+ pmc_core_display_map(s, index, idx, ip,
	739	+ pf_regs[index / 8], maps);
	740	+ }
339	741
340	742	return 0;
341	743	}
342		-
343		-static int pmc_core_ppfear_sts_open(struct inode inode, struct file file)
344		-{
345		- return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
346		-}
347		-
348		-static const struct file_operations pmc_core_ppfear_ops = {
349		- .open = pmc_core_ppfear_sts_open,
350		- .read = seq_read,
351		- .llseek = seq_lseek,
352		- .release = single_release,
353		-};
	744	+DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear);
354	745
355	746	/* This function should return link status, 0 means ready */
356	747	static int pmc_core_mtpmc_link_status(void)
..	..	@@ -382,7 +773,7 @@
382	773	return 0;
383	774	}
384	775
385		-static int pmc_core_mphy_pg_sts_show(struct seq_file s, void unused)
	776	+static int pmc_core_mphy_pg_show(struct seq_file s, void unused)
386	777	{
387	778	struct pmc_dev *pmcdev = s->private;
388	779	const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
..	..	@@ -416,7 +807,7 @@
416	807	msleep(10);
417	808	val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
418	809
419		- for (index = 0; map[index].name && index < 8; index++) {
	810	+ for (index = 0; index < 8 && map[index].name; index++) {
420	811	seq_printf(s, "%-32s\tState: %s\n",
421	812	map[index].name,
422	813	map[index].bit_mask & val_low ? "Not power gated" :
..	..	@@ -434,18 +825,7 @@
434	825	mutex_unlock(&pmcdev->lock);
435	826	return err;
436	827	}
437		-
438		-static int pmc_core_mphy_pg_sts_open(struct inode inode, struct file file)
439		-{
440		- return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
441		-}
442		-
443		-static const struct file_operations pmc_core_mphy_pg_ops = {
444		- .open = pmc_core_mphy_pg_sts_open,
445		- .read = seq_read,
446		- .llseek = seq_lseek,
447		- .release = single_release,
448		-};
	828	+DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg);
449	829
450	830	static int pmc_core_pll_show(struct seq_file s, void unused)
451	831	{
..	..	@@ -481,46 +861,47 @@
481	861	mutex_unlock(&pmcdev->lock);
482	862	return err;
483	863	}
	864	+DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
484	865
485		-static int pmc_core_pll_open(struct inode inode, struct file file)
486		-{
487		- return single_open(file, pmc_core_pll_show, inode->i_private);
488		-}
489		-
490		-static const struct file_operations pmc_core_pll_ops = {
491		- .open = pmc_core_pll_open,
492		- .read = seq_read,
493		- .llseek = seq_lseek,
494		- .release = single_release,
495		-};
496		-
497		-static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
498		-userbuf, size_t count, loff_t ppos)
	866	+static int pmc_core_send_ltr_ignore(u32 value)
499	867	{
500	868	struct pmc_dev *pmcdev = &pmc;
501	869	const struct pmc_reg_map *map = pmcdev->map;
502		- u32 val, buf_size, fd;
	870	+ u32 reg;
503	871	int err = 0;
504	872
505		- buf_size = count < 64 ? count : 64;
506	873	mutex_lock(&pmcdev->lock);
507	874
508		- if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
509		- err = -EFAULT;
510		- goto out_unlock;
511		- }
512		-
513		- if (val > NUM_IP_IGN_ALLOWED) {
	875	+ if (value > map->ltr_ignore_max) {
514	876	err = -EINVAL;
515	877	goto out_unlock;
516	878	}
517	879
518		- fd = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
519		- fd \|= (1U << val);
520		- pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);
	880	+ reg = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
	881	+ reg \|= BIT(value);
	882	+ pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, reg);
521	883
522	884	out_unlock:
523	885	mutex_unlock(&pmcdev->lock);
	886	+
	887	+ return err;
	888	+}
	889	+
	890	+static ssize_t pmc_core_ltr_ignore_write(struct file *file,
	891	+ const char __user *userbuf,
	892	+ size_t count, loff_t *ppos)
	893	+{
	894	+ u32 buf_size, value;
	895	+ int err;
	896	+
	897	+ buf_size = min_t(u32, count, 64);
	898	+
	899	+ err = kstrtou32_from_user(userbuf, buf_size, 10, &value);
	900	+ if (err)
	901	+ return err;
	902	+
	903	+ err = pmc_core_send_ltr_ignore(value);
	904	+
524	905	return err == 0 ? count : err;
525	906	}
526	907
..	..	@@ -568,63 +949,187 @@
568	949	static int pmc_core_slps0_dbg_show(struct seq_file s, void unused)
569	950	{
570	951	struct pmc_dev *pmcdev = s->private;
571		- const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
572		- const struct pmc_bit_map *map;
573		- int offset;
574		- u32 data;
575	952
576	953	pmc_core_slps0_dbg_latch(pmcdev, false);
577		- offset = pmcdev->map->slps0_dbg_offset;
578		- while (*maps) {
579		- map = *maps;
580		- data = pmc_core_reg_read(pmcdev, offset);
581		- offset += 4;
582		- while (map->name) {
583		- seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
584		- map->name,
585		- data & map->bit_mask ?
586		- "Yes" : "No");
587		- ++map;
588		- }
589		- ++maps;
590		- }
	954	+ pmc_core_slps0_display(pmcdev, NULL, s);
591	955	pmc_core_slps0_dbg_latch(pmcdev, true);
	956	+
592	957	return 0;
593	958	}
594	959	DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
	960	+
	961	+static u32 convert_ltr_scale(u32 val)
	962	+{
	963	+ /*
	964	+ * As per PCIE specification supporting document
	965	+ * ECN_LatencyTolnReporting_14Aug08.pdf the Latency
	966	+ * Tolerance Reporting data payload is encoded in a
	967	+ * 3 bit scale and 10 bit value fields. Values are
	968	+ * multiplied by the indicated scale to yield an absolute time
	969	+ * value, expressible in a range from 1 nanosecond to
	970	+ * 2^25*(2^10-1) = 34,326,183,936 nanoseconds.
	971	+ *
	972	+ * scale encoding is as follows:
	973	+ *
	974	+ * ----------------------------------------------
	975	+ * \|scale factor \| Multiplier (ns) \|
	976	+ * ----------------------------------------------
	977	+ * \| 0 \| 1 \|
	978	+ * \| 1 \| 32 \|
	979	+ * \| 2 \| 1024 \|
	980	+ * \| 3 \| 32768 \|
	981	+ * \| 4 \| 1048576 \|
	982	+ * \| 5 \| 33554432 \|
	983	+ * \| 6 \| Invalid \|
	984	+ * \| 7 \| Invalid \|
	985	+ * ----------------------------------------------
	986	+ */
	987	+ if (val > 5) {
	988	+ pr_warn("Invalid LTR scale factor.\n");
	989	+ return 0;
	990	+ }
	991	+
	992	+ return 1U << (5 * val);
	993	+}
	994	+
	995	+static int pmc_core_ltr_show(struct seq_file s, void unused)
	996	+{
	997	+ struct pmc_dev *pmcdev = s->private;
	998	+ const struct pmc_bit_map *map = pmcdev->map->ltr_show_sts;
	999	+ u64 decoded_snoop_ltr, decoded_non_snoop_ltr;
	1000	+ u32 ltr_raw_data, scale, val;
	1001	+ u16 snoop_ltr, nonsnoop_ltr;
	1002	+ int index;
	1003	+
	1004	+ for (index = 0; map[index].name ; index++) {
	1005	+ decoded_snoop_ltr = decoded_non_snoop_ltr = 0;
	1006	+ ltr_raw_data = pmc_core_reg_read(pmcdev,
	1007	+ map[index].bit_mask);
	1008	+ snoop_ltr = ltr_raw_data & ~MTPMC_MASK;
	1009	+ nonsnoop_ltr = (ltr_raw_data >> 0x10) & ~MTPMC_MASK;
	1010	+
	1011	+ if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) {
	1012	+ scale = FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr);
	1013	+ val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr);
	1014	+ decoded_non_snoop_ltr = val * convert_ltr_scale(scale);
	1015	+ }
	1016	+
	1017	+ if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) {
	1018	+ scale = FIELD_GET(LTR_DECODED_SCALE, snoop_ltr);
	1019	+ val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr);
	1020	+ decoded_snoop_ltr = val * convert_ltr_scale(scale);
	1021	+ }
	1022	+
	1023	+ seq_printf(s, "%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(ns): %-16llu\n",
	1024	+ map[index].name, ltr_raw_data,
	1025	+ decoded_non_snoop_ltr,
	1026	+ decoded_snoop_ltr);
	1027	+ }
	1028	+ return 0;
	1029	+}
	1030	+DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
	1031	+
	1032	+static int pmc_core_substate_res_show(struct seq_file s, void unused)
	1033	+{
	1034	+ struct pmc_dev *pmcdev = s->private;
	1035	+ const char **lpm_modes = pmcdev->map->lpm_modes;
	1036	+ u32 offset = pmcdev->map->lpm_residency_offset;
	1037	+ u32 lpm_en;
	1038	+ int index;
	1039	+
	1040	+ lpm_en = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_en_offset);
	1041	+ seq_printf(s, "status substate residency\n");
	1042	+ for (index = 0; lpm_modes[index]; index++) {
	1043	+ seq_printf(s, "%7s %7s %-15u\n",
	1044	+ BIT(index) & lpm_en ? "Enabled" : " ",
	1045	+ lpm_modes[index], pmc_core_reg_read(pmcdev, offset));
	1046	+ offset += 4;
	1047	+ }
	1048	+
	1049	+ return 0;
	1050	+}
	1051	+DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res);
	1052	+
	1053	+static int pmc_core_substate_sts_regs_show(struct seq_file s, void unused)
	1054	+{
	1055	+ struct pmc_dev *pmcdev = s->private;
	1056	+ const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
	1057	+ u32 offset = pmcdev->map->lpm_status_offset;
	1058	+
	1059	+ pmc_core_lpm_display(pmcdev, NULL, s, offset, "STATUS", maps);
	1060	+
	1061	+ return 0;
	1062	+}
	1063	+DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs);
	1064	+
	1065	+static int pmc_core_substate_l_sts_regs_show(struct seq_file s, void unused)
	1066	+{
	1067	+ struct pmc_dev *pmcdev = s->private;
	1068	+ const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
	1069	+ u32 offset = pmcdev->map->lpm_live_status_offset;
	1070	+
	1071	+ pmc_core_lpm_display(pmcdev, NULL, s, offset, "LIVE_STATUS", maps);
	1072	+
	1073	+ return 0;
	1074	+}
	1075	+DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs);
	1076	+
	1077	+static int pmc_core_pkgc_show(struct seq_file s, void unused)
	1078	+{
	1079	+ struct pmc_dev *pmcdev = s->private;
	1080	+ const struct pmc_bit_map *map = pmcdev->map->msr_sts;
	1081	+ u64 pcstate_count;
	1082	+ int index;
	1083	+
	1084	+ for (index = 0; map[index].name ; index++) {
	1085	+ if (rdmsrl_safe(map[index].bit_mask, &pcstate_count))
	1086	+ continue;
	1087	+
	1088	+ pcstate_count *= 1000;
	1089	+ do_div(pcstate_count, tsc_khz);
	1090	+ seq_printf(s, "%-8s : %llu\n", map[index].name,
	1091	+ pcstate_count);
	1092	+ }
	1093	+
	1094	+ return 0;
	1095	+}
	1096	+DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc);
595	1097
596	1098	static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
597	1099	{
598	1100	debugfs_remove_recursive(pmcdev->dbgfs_dir);
599	1101	}
600	1102
601		-static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
	1103	+static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
602	1104	{
603	1105	struct dentry *dir;
604	1106
605	1107	dir = debugfs_create_dir("pmc_core", NULL);
606		- if (!dir)
607		- return -ENOMEM;
608		-
609	1108	pmcdev->dbgfs_dir = dir;
610	1109
611	1110	debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
612	1111	&pmc_core_dev_state);
613	1112
614		- debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev,
615		- &pmc_core_ppfear_ops);
	1113	+ if (pmcdev->map->pfear_sts)
	1114	+ debugfs_create_file("pch_ip_power_gating_status", 0444, dir,
	1115	+ pmcdev, &pmc_core_ppfear_fops);
616	1116
617	1117	debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
618	1118	&pmc_core_ltr_ignore_ops);
619	1119
	1120	+ debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops);
	1121	+
	1122	+ debugfs_create_file("package_cstate_show", 0444, dir, pmcdev,
	1123	+ &pmc_core_pkgc_fops);
	1124	+
620	1125	if (pmcdev->map->pll_sts)
621	1126	debugfs_create_file("pll_status", 0444, dir, pmcdev,
622		- &pmc_core_pll_ops);
	1127	+ &pmc_core_pll_fops);
623	1128
624	1129	if (pmcdev->map->mphy_sts)
625	1130	debugfs_create_file("mphy_core_lanes_power_gating_status",
626	1131	0444, dir, pmcdev,
627		- &pmc_core_mphy_pg_ops);
	1132	+ &pmc_core_mphy_pg_fops);
628	1133
629	1134	if (pmcdev->map->slps0_dbg_maps) {
630	1135	debugfs_create_file("slp_s0_debug_status", 0444,
..	..	@@ -635,41 +1140,100 @@
635	1140	dir, &slps0_dbg_latch);
636	1141	}
637	1142
638		- return 0;
639		-}
640		-#else
641		-static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
642		-{
643		- return 0;
644		-}
	1143	+ if (pmcdev->map->lpm_en_offset) {
	1144	+ debugfs_create_file("substate_residencies", 0444,
	1145	+ pmcdev->dbgfs_dir, pmcdev,
	1146	+ &pmc_core_substate_res_fops);
	1147	+ }
645	1148
646		-static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
647		-{
	1149	+ if (pmcdev->map->lpm_status_offset) {
	1150	+ debugfs_create_file("substate_status_registers", 0444,
	1151	+ pmcdev->dbgfs_dir, pmcdev,
	1152	+ &pmc_core_substate_sts_regs_fops);
	1153	+ debugfs_create_file("substate_live_status_registers", 0444,
	1154	+ pmcdev->dbgfs_dir, pmcdev,
	1155	+ &pmc_core_substate_l_sts_regs_fops);
	1156	+ }
648	1157	}
649		-#endif /* CONFIG_DEBUG_FS */
650	1158
651	1159	static const struct x86_cpu_id intel_pmc_core_ids[] = {
652		- ICPU(INTEL_FAM6_SKYLAKE_MOBILE, &spt_reg_map),
653		- ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map),
654		- ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map),
655		- ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map),
656		- ICPU(INTEL_FAM6_CANNONLAKE_MOBILE, &cnp_reg_map),
	1160	+ X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &spt_reg_map),
	1161	+ X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &spt_reg_map),
	1162	+ X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &spt_reg_map),
	1163	+ X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &spt_reg_map),
	1164	+ X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, &cnp_reg_map),
	1165	+ X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_reg_map),
	1166	+ X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, &icl_reg_map),
	1167	+ X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &cnp_reg_map),
	1168	+ X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &cnp_reg_map),
	1169	+ X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &tgl_reg_map),
	1170	+ X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_reg_map),
	1171	+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &tgl_reg_map),
	1172	+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map),
	1173	+ X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &tgl_reg_map),
657	1174	{}
658	1175	};
659	1176
660	1177	MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
661	1178
662	1179	static const struct pci_device_id pmc_pci_ids[] = {
663		- { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), 0},
664		- { 0, },
	1180	+ { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) },
	1181	+ { }
665	1182	};
666	1183
667		-static int __init pmc_core_probe(void)
	1184	+/*
	1185	+ * This quirk can be used on those platforms where
	1186	+ * the platform BIOS enforces 24Mhz crystal to shutdown
	1187	+ * before PMC can assert SLP_S0#.
	1188	+ */
	1189	+static bool xtal_ignore;
	1190	+static int quirk_xtal_ignore(const struct dmi_system_id *id)
668	1191	{
	1192	+ xtal_ignore = true;
	1193	+ return 0;
	1194	+}
	1195	+
	1196	+static void pmc_core_xtal_ignore(struct pmc_dev *pmcdev)
	1197	+{
	1198	+ u32 value;
	1199	+
	1200	+ value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_vric1_offset);
	1201	+ /* 24MHz Crystal Shutdown Qualification Disable */
	1202	+ value \|= SPT_PMC_VRIC1_XTALSDQDIS;
	1203	+ /* Low Voltage Mode Enable */
	1204	+ value &= ~SPT_PMC_VRIC1_SLPS0LVEN;
	1205	+ pmc_core_reg_write(pmcdev, pmcdev->map->pm_vric1_offset, value);
	1206	+}
	1207	+
	1208	+static const struct dmi_system_id pmc_core_dmi_table[] = {
	1209	+ {
	1210	+ .callback = quirk_xtal_ignore,
	1211	+ .ident = "HP Elite x2 1013 G3",
	1212	+ .matches = {
	1213	+ DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	1214	+ DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite x2 1013 G3"),
	1215	+ },
	1216	+ },
	1217	+ {}
	1218	+};
	1219	+
	1220	+static void pmc_core_do_dmi_quirks(struct pmc_dev *pmcdev)
	1221	+{
	1222	+ dmi_check_system(pmc_core_dmi_table);
	1223	+
	1224	+ if (xtal_ignore)
	1225	+ pmc_core_xtal_ignore(pmcdev);
	1226	+}
	1227	+
	1228	+static int pmc_core_probe(struct platform_device *pdev)
	1229	+{
	1230	+ static bool device_initialized;
669	1231	struct pmc_dev *pmcdev = &pmc;
670	1232	const struct x86_cpu_id *cpu_id;
671	1233	u64 slp_s0_addr;
672		- int err;
	1234	+
	1235	+ if (device_initialized)
	1236	+ return -ENODEV;
673	1237
674	1238	cpu_id = x86_match_cpu(intel_pmc_core_ids);
675	1239	if (!cpu_id)
..	..	@@ -678,8 +1242,8 @@
678	1242	pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
679	1243
680	1244	/*
681		- * Coffeelake has CPU ID of Kabylake and Cannonlake PCH. So here
682		- * Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap
	1245	+ * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here
	1246	+ * Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap
683	1247	* in this case.
684	1248	*/
685	1249	if (pmcdev->map == &spt_reg_map && !pci_dev_present(pmc_pci_ids))
..	..	@@ -700,29 +1264,145 @@
700	1264	return -ENOMEM;
701	1265
702	1266	mutex_init(&pmcdev->lock);
	1267	+ platform_set_drvdata(pdev, pmcdev);
703	1268	pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
	1269	+ pmc_core_do_dmi_quirks(pmcdev);
704	1270
705		- err = pmc_core_dbgfs_register(pmcdev);
706		- if (err < 0) {
707		- pr_warn(" debugfs register failed.\n");
708		- iounmap(pmcdev->regbase);
709		- return err;
	1271	+ /*
	1272	+ * On TGL, due to a hardware limitation, the GBE LTR blocks PC10 when
	1273	+ * a cable is attached. Tell the PMC to ignore it.
	1274	+ */
	1275	+ if (pmcdev->map == &tgl_reg_map) {
	1276	+ dev_dbg(&pdev->dev, "ignoring GBE LTR\n");
	1277	+ pmc_core_send_ltr_ignore(3);
710	1278	}
711	1279
712		- pr_info(" initialized\n");
	1280	+ pmc_core_dbgfs_register(pmcdev);
	1281	+
	1282	+ device_initialized = true;
	1283	+ dev_info(&pdev->dev, " initialized\n");
	1284	+
713	1285	return 0;
714	1286	}
715		-module_init(pmc_core_probe)
716	1287
717		-static void __exit pmc_core_remove(void)
	1288	+static int pmc_core_remove(struct platform_device *pdev)
718	1289	{
719		- struct pmc_dev *pmcdev = &pmc;
	1290	+ struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
720	1291
721	1292	pmc_core_dbgfs_unregister(pmcdev);
	1293	+ platform_set_drvdata(pdev, NULL);
722	1294	mutex_destroy(&pmcdev->lock);
723	1295	iounmap(pmcdev->regbase);
	1296	+ return 0;
724	1297	}
725		-module_exit(pmc_core_remove)
	1298	+
	1299	+static bool warn_on_s0ix_failures;
	1300	+module_param(warn_on_s0ix_failures, bool, 0644);
	1301	+MODULE_PARM_DESC(warn_on_s0ix_failures, "Check and warn for S0ix failures");
	1302	+
	1303	+static __maybe_unused int pmc_core_suspend(struct device *dev)
	1304	+{
	1305	+ struct pmc_dev *pmcdev = dev_get_drvdata(dev);
	1306	+
	1307	+ pmcdev->check_counters = false;
	1308	+
	1309	+ /* No warnings on S0ix failures */
	1310	+ if (!warn_on_s0ix_failures)
	1311	+ return 0;
	1312	+
	1313	+ /* Check if the syspend will actually use S0ix */
	1314	+ if (pm_suspend_via_firmware())
	1315	+ return 0;
	1316	+
	1317	+ /* Save PC10 residency for checking later */
	1318	+ if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pmcdev->pc10_counter))
	1319	+ return -EIO;
	1320	+
	1321	+ /* Save S0ix residency for checking later */
	1322	+ if (pmc_core_dev_state_get(pmcdev, &pmcdev->s0ix_counter))
	1323	+ return -EIO;
	1324	+
	1325	+ pmcdev->check_counters = true;
	1326	+ return 0;
	1327	+}
	1328	+
	1329	+static inline bool pmc_core_is_pc10_failed(struct pmc_dev *pmcdev)
	1330	+{
	1331	+ u64 pc10_counter;
	1332	+
	1333	+ if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pc10_counter))
	1334	+ return false;
	1335	+
	1336	+ if (pc10_counter == pmcdev->pc10_counter)
	1337	+ return true;
	1338	+
	1339	+ return false;
	1340	+}
	1341	+
	1342	+static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev)
	1343	+{
	1344	+ u64 s0ix_counter;
	1345	+
	1346	+ if (pmc_core_dev_state_get(pmcdev, &s0ix_counter))
	1347	+ return false;
	1348	+
	1349	+ if (s0ix_counter == pmcdev->s0ix_counter)
	1350	+ return true;
	1351	+
	1352	+ return false;
	1353	+}
	1354	+
	1355	+static __maybe_unused int pmc_core_resume(struct device *dev)
	1356	+{
	1357	+ struct pmc_dev *pmcdev = dev_get_drvdata(dev);
	1358	+ const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
	1359	+ int offset = pmcdev->map->lpm_status_offset;
	1360	+
	1361	+ if (!pmcdev->check_counters)
	1362	+ return 0;
	1363	+
	1364	+ if (!pmc_core_is_s0ix_failed(pmcdev))
	1365	+ return 0;
	1366	+
	1367	+ if (pmc_core_is_pc10_failed(pmcdev)) {
	1368	+ /* S0ix failed because of PC10 entry failure */
	1369	+ dev_info(dev, "CPU did not enter PC10!!! (PC10 cnt=0x%llx)\n",
	1370	+ pmcdev->pc10_counter);
	1371	+ return 0;
	1372	+ }
	1373	+
	1374	+ /* The real interesting case - S0ix failed - lets ask PMC why. */
	1375	+ dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=%llu)\n",
	1376	+ pmcdev->s0ix_counter);
	1377	+ if (pmcdev->map->slps0_dbg_maps)
	1378	+ pmc_core_slps0_display(pmcdev, dev, NULL);
	1379	+ if (pmcdev->map->lpm_sts)
	1380	+ pmc_core_lpm_display(pmcdev, dev, NULL, offset, "STATUS", maps);
	1381	+
	1382	+ return 0;
	1383	+}
	1384	+
	1385	+static const struct dev_pm_ops pmc_core_pm_ops = {
	1386	+ SET_LATE_SYSTEM_SLEEP_PM_OPS(pmc_core_suspend, pmc_core_resume)
	1387	+};
	1388	+
	1389	+static const struct acpi_device_id pmc_core_acpi_ids[] = {
	1390	+ {"INT33A1", 0}, /* _HID for Intel Power Engine, _CID PNP0D80*/
	1391	+ { }
	1392	+};
	1393	+MODULE_DEVICE_TABLE(acpi, pmc_core_acpi_ids);
	1394	+
	1395	+static struct platform_driver pmc_core_driver = {
	1396	+ .driver = {
	1397	+ .name = "intel_pmc_core",
	1398	+ .acpi_match_table = ACPI_PTR(pmc_core_acpi_ids),
	1399	+ .pm = &pmc_core_pm_ops,
	1400	+ },
	1401	+ .probe = pmc_core_probe,
	1402	+ .remove = pmc_core_remove,
	1403	+};
	1404	+
	1405	+module_platform_driver(pmc_core_driver);
726	1406
727	1407	MODULE_LICENSE("GPL v2");
728	1408	MODULE_DESCRIPTION("Intel PMC Core Driver");