~hc/RK356X_SDK_RELEASE.git

..	..	@@ -13,8 +13,8 @@
13	13	#include <linux/delay.h>
14	14	#include <linux/dmi.h>
15	15	#include <linux/init.h>
	16	+#include <linux/msi.h>
16	17	#include <linux/of.h>
17		-#include <linux/of_pci.h>
18	18	#include <linux/pci.h>
19	19	#include <linux/pm.h>
20	20	#include <linux/slab.h>
..	..	@@ -29,10 +29,11 @@
29	29	#include <linux/pm_runtime.h>
30	30	#include <linux/pci_hotplug.h>
31	31	#include <linux/vmalloc.h>
32		-#include <linux/pci-ats.h>
33		-#include <asm/setup.h>
34	32	#include <asm/dma.h>
35	33	#include <linux/aer.h>
	34	+#ifndef __GENKSYMS__
	35	+#include <trace/hooks/pci.h>
	36	+#endif
36	37	#include "pci.h"
37	38
38	39	DEFINE_MUTEX(pci_slot_mutex);
..	..	@@ -48,7 +49,7 @@
48	49	int pci_pci_problems;
49	50	EXPORT_SYMBOL(pci_pci_problems);
50	51
51		-unsigned int pci_pm_d3_delay;
	52	+unsigned int pci_pm_d3hot_delay;
52	53
53	54	static void pci_pme_list_scan(struct work_struct *work);
54	55
..	..	@@ -65,13 +66,17 @@
65	66
66	67	static void pci_dev_d3_sleep(struct pci_dev *dev)
67	68	{
68		- unsigned int delay = dev->d3_delay;
	69	+ unsigned int delay = dev->d3hot_delay;
	70	+ int err = -EOPNOTSUPP;
69	71
70		- if (delay < pci_pm_d3_delay)
71		- delay = pci_pm_d3_delay;
	72	+ if (delay < pci_pm_d3hot_delay)
	73	+ delay = pci_pm_d3hot_delay;
72	74
73		- if (delay)
74		- msleep(delay);
	75	+ if (delay) {
	76	+ trace_android_rvh_pci_d3_sleep(dev, delay, &err);
	77	+ if (err == -EOPNOTSUPP)
	78	+ msleep(delay);
	79	+ }
75	80	}
76	81
77	82	#ifdef CONFIG_PCI_DOMAINS
..	..	@@ -85,15 +90,34 @@
85	90	unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
86	91
87	92	#define DEFAULT_HOTPLUG_IO_SIZE (256)
88		-#define DEFAULT_HOTPLUG_MEM_SIZE (210241024)
89		-/* pci=hpmemsize=nnM,hpiosize=nn can override this */
	93	+#define DEFAULT_HOTPLUG_MMIO_SIZE (210241024)
	94	+#define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (210241024)
	95	+/* hpiosize=nn can override this */
90	96	unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
91		-unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
	97	+/*
	98	+ * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
	99	+ * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
	100	+ * pci=hpmemsize=nnM overrides both
	101	+ */
	102	+unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
	103	+unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
92	104
93	105	#define DEFAULT_HOTPLUG_BUS_SIZE 1
94	106	unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
95	107
	108	+
	109	+/* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
	110	+#ifdef CONFIG_PCIE_BUS_TUNE_OFF
	111	+enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
	112	+#elif defined CONFIG_PCIE_BUS_SAFE
	113	+enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
	114	+#elif defined CONFIG_PCIE_BUS_PERFORMANCE
	115	+enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
	116	+#elif defined CONFIG_PCIE_BUS_PEER2PEER
	117	+enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
	118	+#else
96	119	enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
	120	+#endif
97	121
98	122	/*
99	123	* The default CLS is used if arch didn't set CLS explicitly and not
..	..	@@ -123,6 +147,7 @@
123	147	{
124	148	return pcie_ats_disabled;
125	149	}
	150	+EXPORT_SYMBOL_GPL(pci_ats_disabled);
126	151
127	152	/* Disable bridge_d3 for all PCIe ports */
128	153	static bool pci_bridge_d3_disable;
..	..	@@ -164,6 +189,29 @@
164	189	}
165	190	EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
166	191
	192	+/**
	193	+ * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
	194	+ * @pdev: the PCI device
	195	+ *
	196	+ * Returns error bits set in PCI_STATUS and clears them.
	197	+ */
	198	+int pci_status_get_and_clear_errors(struct pci_dev *pdev)
	199	+{
	200	+ u16 status;
	201	+ int ret;
	202	+
	203	+ ret = pci_read_config_word(pdev, PCI_STATUS, &status);
	204	+ if (ret != PCIBIOS_SUCCESSFUL)
	205	+ return -EIO;
	206	+
	207	+ status &= PCI_STATUS_ERROR_BITS;
	208	+ if (status)
	209	+ pci_write_config_word(pdev, PCI_STATUS, status);
	210	+
	211	+ return status;
	212	+}
	213	+EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
	214	+
167	215	#ifdef CONFIG_HAS_IOMEM
168	216	void __iomem pci_ioremap_bar(struct pci_dev pdev, int bar)
169	217	{
..	..	@@ -176,7 +224,7 @@
176	224	pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
177	225	return NULL;
178	226	}
179		- return ioremap_nocache(res->start, resource_size(res));
	227	+ return ioremap(res->start, resource_size(res));
180	228	}
181	229	EXPORT_SYMBOL_GPL(pci_ioremap_bar);
182	230
..	..	@@ -197,8 +245,8 @@
197	245
198	246	/**
199	247	* pci_dev_str_match_path - test if a path string matches a device
200		- * @dev: the PCI device to test
201		- * @p: string to match the device against
	248	+ * @dev: the PCI device to test
	249	+ * @path: string to match the device against
202	250	* @endptr: pointer to the string after the match
203	251	*
204	252	* Test if a string (typically from a kernel parameter) formatted as a
..	..	@@ -280,8 +328,8 @@
280	328
281	329	/**
282	330	* pci_dev_str_match - test if a string matches a device
283		- * @dev: the PCI device to test
284		- * @p: string to match the device against
	331	+ * @dev: the PCI device to test
	332	+ * @p: string to match the device against
285	333	* @endptr: pointer to the string after the match
286	334	*
287	335	* Test if a string (typically from a kernel parameter) matches a specified
..	..	@@ -341,7 +389,7 @@
341	389	} else {
342	390	/*
343	391	* PCI Bus, Device, Function IDs are specified
344		- * (optionally, may include a path of devfns following it)
	392	+ * (optionally, may include a path of devfns following it)
345	393	*/
346	394	ret = pci_dev_str_match_path(dev, p, &p);
347	395	if (ret < 0)
..	..	@@ -425,7 +473,7 @@
425	473	* Tell if a device supports a given PCI capability.
426	474	* Returns the address of the requested capability structure within the
427	475	* device's PCI configuration space or 0 in case the device does not
428		- * support it. Possible values for @cap:
	476	+ * support it. Possible values for @cap include:
429	477	*
430	478	* %PCI_CAP_ID_PM Power Management
431	479	* %PCI_CAP_ID_AGP Accelerated Graphics Port
..	..	@@ -450,11 +498,11 @@
450	498
451	499	/**
452	500	* pci_bus_find_capability - query for devices' capabilities
453		- * @bus: the PCI bus to query
	501	+ * @bus: the PCI bus to query
454	502	* @devfn: PCI device to query
455		- * @cap: capability code
	503	+ * @cap: capability code
456	504	*
457		- * Like pci_find_capability() but works for pci devices that do not have a
	505	+ * Like pci_find_capability() but works for PCI devices that do not have a
458	506	* pci_dev structure set up yet.
459	507	*
460	508	* Returns the address of the requested capability structure within the
..	..	@@ -535,7 +583,7 @@
535	583	*
536	584	* Returns the address of the requested extended capability structure
537	585	* within the device's PCI configuration space or 0 if the device does
538		- * not support it. Possible values for @cap:
	586	+ * not support it. Possible values for @cap include:
539	587	*
540	588	* %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
541	589	* %PCI_EXT_CAP_ID_VC Virtual Channel
..	..	@@ -547,6 +595,40 @@
547	595	return pci_find_next_ext_capability(dev, 0, cap);
548	596	}
549	597	EXPORT_SYMBOL_GPL(pci_find_ext_capability);
	598	+
	599	+/**
	600	+ * pci_get_dsn - Read and return the 8-byte Device Serial Number
	601	+ * @dev: PCI device to query
	602	+ *
	603	+ * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
	604	+ * Number.
	605	+ *
	606	+ * Returns the DSN, or zero if the capability does not exist.
	607	+ */
	608	+u64 pci_get_dsn(struct pci_dev *dev)
	609	+{
	610	+ u32 dword;
	611	+ u64 dsn;
	612	+ int pos;
	613	+
	614	+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
	615	+ if (!pos)
	616	+ return 0;
	617	+
	618	+ /*
	619	+ * The Device Serial Number is two dwords offset 4 bytes from the
	620	+ * capability position. The specification says that the first dword is
	621	+ * the lower half, and the second dword is the upper half.
	622	+ */
	623	+ pos += 4;
	624	+ pci_read_config_dword(dev, pos, &dword);
	625	+ dsn = (u64)dword;
	626	+ pci_read_config_dword(dev, pos + 4, &dword);
	627	+ dsn \|= ((u64)dword) << 32;
	628	+
	629	+ return dsn;
	630	+}
	631	+EXPORT_SYMBOL_GPL(pci_get_dsn);
550	632
551	633	static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
552	634	{
..	..	@@ -618,12 +700,13 @@
618	700	EXPORT_SYMBOL_GPL(pci_find_ht_capability);
619	701
620	702	/**
621		- * pci_find_parent_resource - return resource region of parent bus of given region
	703	+ * pci_find_parent_resource - return resource region of parent bus of given
	704	+ * region
622	705	* @dev: PCI device structure contains resources to be searched
623	706	* @res: child resource record for which parent is sought
624	707	*
625		- * For given resource region of given device, return the resource
626		- * region of parent bus the given region is contained in.
	708	+ * For given resource region of given device, return the resource region of
	709	+ * parent bus the given region is contained in.
627	710	*/
628	711	struct resource pci_find_parent_resource(const struct pci_dev dev,
629	712	struct resource *res)
..	..	@@ -673,7 +756,7 @@
673	756	{
674	757	int i;
675	758
676		- for (i = 0; i < PCI_ROM_RESOURCE; i++) {
	759	+ for (i = 0; i < PCI_STD_NUM_BARS; i++) {
677	760	struct resource *r = &dev->resource[i];
678	761
679	762	if (r->start && resource_contains(r, res))
..	..	@@ -683,30 +766,6 @@
683	766	return NULL;
684	767	}
685	768	EXPORT_SYMBOL(pci_find_resource);
686		-
687		-/**
688		- * pci_find_pcie_root_port - return PCIe Root Port
689		- * @dev: PCI device to query
690		- *
691		- * Traverse up the parent chain and return the PCIe Root Port PCI Device
692		- * for a given PCI Device.
693		- */
694		-struct pci_dev pci_find_pcie_root_port(struct pci_dev dev)
695		-{
696		- struct pci_dev bridge, highest_pcie_bridge = dev;
697		-
698		- bridge = pci_upstream_bridge(dev);
699		- while (bridge && pci_is_pcie(bridge)) {
700		- highest_pcie_bridge = bridge;
701		- bridge = pci_upstream_bridge(bridge);
702		- }
703		-
704		- if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
705		- return NULL;
706		-
707		- return highest_pcie_bridge;
708		-}
709		-EXPORT_SYMBOL(pci_find_pcie_root_port);
710	769
711	770	/**
712	771	* pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
..	..	@@ -732,6 +791,137 @@
732	791	}
733	792
734	793	return 0;
	794	+}
	795	+
	796	+static int pci_acs_enable;
	797	+
	798	+/**
	799	+ * pci_request_acs - ask for ACS to be enabled if supported
	800	+ */
	801	+void pci_request_acs(void)
	802	+{
	803	+ pci_acs_enable = 1;
	804	+}
	805	+
	806	+static const char *disable_acs_redir_param;
	807	+
	808	+/**
	809	+ * pci_disable_acs_redir - disable ACS redirect capabilities
	810	+ * @dev: the PCI device
	811	+ *
	812	+ * For only devices specified in the disable_acs_redir parameter.
	813	+ */
	814	+static void pci_disable_acs_redir(struct pci_dev *dev)
	815	+{
	816	+ int ret = 0;
	817	+ const char *p;
	818	+ int pos;
	819	+ u16 ctrl;
	820	+
	821	+ if (!disable_acs_redir_param)
	822	+ return;
	823	+
	824	+ p = disable_acs_redir_param;
	825	+ while (*p) {
	826	+ ret = pci_dev_str_match(dev, p, &p);
	827	+ if (ret < 0) {
	828	+ pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
	829	+ disable_acs_redir_param);
	830	+
	831	+ break;
	832	+ } else if (ret == 1) {
	833	+ /* Found a match */
	834	+ break;
	835	+ }
	836	+
	837	+ if (p != ';' && p != ',') {
	838	+ /* End of param or invalid format */
	839	+ break;
	840	+ }
	841	+ p++;
	842	+ }
	843	+
	844	+ if (ret != 1)
	845	+ return;
	846	+
	847	+ if (!pci_dev_specific_disable_acs_redir(dev))
	848	+ return;
	849	+
	850	+ pos = dev->acs_cap;
	851	+ if (!pos) {
	852	+ pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
	853	+ return;
	854	+ }
	855	+
	856	+ pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
	857	+
	858	+ /* P2P Request & Completion Redirect */
	859	+ ctrl &= ~(PCI_ACS_RR \| PCI_ACS_CR \| PCI_ACS_EC);
	860	+
	861	+ pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
	862	+
	863	+ pci_info(dev, "disabled ACS redirect\n");
	864	+}
	865	+
	866	+/**
	867	+ * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
	868	+ * @dev: the PCI device
	869	+ */
	870	+static void pci_std_enable_acs(struct pci_dev *dev)
	871	+{
	872	+ int pos;
	873	+ u16 cap;
	874	+ u16 ctrl;
	875	+
	876	+ pos = dev->acs_cap;
	877	+ if (!pos)
	878	+ return;
	879	+
	880	+ pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
	881	+ pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
	882	+
	883	+ /* Source Validation */
	884	+ ctrl \|= (cap & PCI_ACS_SV);
	885	+
	886	+ /* P2P Request Redirect */
	887	+ ctrl \|= (cap & PCI_ACS_RR);
	888	+
	889	+ /* P2P Completion Redirect */
	890	+ ctrl \|= (cap & PCI_ACS_CR);
	891	+
	892	+ /* Upstream Forwarding */
	893	+ ctrl \|= (cap & PCI_ACS_UF);
	894	+
	895	+ /* Enable Translation Blocking for external devices */
	896	+ if (dev->external_facing \|\| dev->untrusted)
	897	+ ctrl \|= (cap & PCI_ACS_TB);
	898	+
	899	+ pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
	900	+}
	901	+
	902	+/**
	903	+ * pci_enable_acs - enable ACS if hardware support it
	904	+ * @dev: the PCI device
	905	+ */
	906	+static void pci_enable_acs(struct pci_dev *dev)
	907	+{
	908	+ if (!pci_acs_enable)
	909	+ goto disable_acs_redir;
	910	+
	911	+ if (!pci_dev_specific_enable_acs(dev))
	912	+ goto disable_acs_redir;
	913	+
	914	+ pci_std_enable_acs(dev);
	915	+
	916	+disable_acs_redir:
	917	+ /*
	918	+ * Note: pci_disable_acs_redir() must be called even if ACS was not
	919	+ * enabled by the kernel because it may have been enabled by
	920	+ * platform firmware. So if we are told to disable it, we should
	921	+ * always disable it after setting the kernel's default
	922	+ * preferences.
	923	+ */
	924	+ pci_disable_acs_redir(dev);
735	925	}
736	926
737	927	/**
..	..	@@ -776,6 +966,12 @@
776	966	return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
777	967	}
778	968
	969	+static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
	970	+{
	971	+ if (pci_platform_pm && pci_platform_pm->refresh_state)
	972	+ pci_platform_pm->refresh_state(dev);
	973	+}
	974	+
779	975	static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
780	976	{
781	977	return pci_platform_pm ?
..	..	@@ -793,9 +989,16 @@
793	989	return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
794	990	}
795	991
	992	+static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
	993	+{
	994	+ if (pci_platform_pm && pci_platform_pm->bridge_d3)
	995	+ return pci_platform_pm->bridge_d3(dev);
	996	+ return false;
	997	+}
	998	+
796	999	/**
797	1000	* pci_raw_set_power_state - Use PCI PM registers to set the power state of
798		- * given PCI device
	1001	+ * given PCI device
799	1002	* @dev: PCI device to handle.
800	1003	* @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
801	1004	*
..	..	@@ -821,25 +1024,35 @@
821	1024	if (state < PCI_D0 \|\| state > PCI_D3hot)
822	1025	return -EINVAL;
823	1026
824		- /* Validate current state:
825		- * Can enter D0 from any state, but if we can only go deeper
826		- * to sleep if we're already in a low power state
	1027	+ /*
	1028	+ * Validate transition: We can enter D0 from any state, but if
	1029	+ * we're already in a low-power state, we can only go deeper. E.g.,
	1030	+ * we can go from D1 to D3, but we can't go directly from D3 to D1;
	1031	+ * we'd have to go from D3 to D0, then to D1.
827	1032	*/
828	1033	if (state != PCI_D0 && dev->current_state <= PCI_D3cold
829	1034	&& dev->current_state > state) {
830		- pci_err(dev, "invalid power transition (from state %d to %d)\n",
831		- dev->current_state, state);
	1035	+ pci_err(dev, "invalid power transition (from %s to %s)\n",
	1036	+ pci_power_name(dev->current_state),
	1037	+ pci_power_name(state));
832	1038	return -EINVAL;
833	1039	}
834	1040
835		- /* check if this device supports the desired state */
	1041	+ /* Check if this device supports the desired state */
836	1042	if ((state == PCI_D1 && !dev->d1_support)
837	1043	\|\| (state == PCI_D2 && !dev->d2_support))
838	1044	return -EIO;
839	1045
840	1046	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
	1047	+ if (pmcsr == (u16) ~0) {
	1048	+ pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
	1049	+ pci_power_name(dev->current_state),
	1050	+ pci_power_name(state));
	1051	+ return -EIO;
	1052	+ }
841	1053
842		- /* If we're (effectively) in D3, force entire word to 0.
	1054	+ /*
	1055	+ * If we're (effectively) in D3, force entire word to 0.
843	1056	* This doesn't affect PME_Status, disables PME_En, and
844	1057	* sets PowerState to 0.
845	1058	*/
..	..	@@ -856,17 +1069,19 @@
856	1069	if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
857	1070	&& !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
858	1071	need_restore = true;
859		- /* Fall-through: force to D0 */
	1072	+ fallthrough; /* force to D0 */
860	1073	default:
861	1074	pmcsr = 0;
862	1075	break;
863	1076	}
864	1077
865		- /* enter specified state */
	1078	+ /* Enter specified state */
866	1079	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
867	1080
868		- /* Mandatory power management transition delays */
869		- /* see PCI PM 1.1 5.6.1 table 18 */
	1081	+ /*
	1082	+ * Mandatory power management transition delays; see PCI PM 1.1
	1083	+ * 5.6.1 table 18
	1084	+ */
870	1085	if (state == PCI_D3hot \|\| dev->current_state == PCI_D3hot)
871	1086	pci_dev_d3_sleep(dev);
872	1087	else if (state == PCI_D2 \|\| dev->current_state == PCI_D2)
..	..	@@ -874,9 +1089,10 @@
874	1089
875	1090	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
876	1091	dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
877		- if (dev->current_state != state && printk_ratelimit())
878		- pci_info(dev, "Refused to change power state, currently in D%d\n",
879		- dev->current_state);
	1092	+ if (dev->current_state != state)
	1093	+ pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
	1094	+ pci_power_name(dev->current_state),
	1095	+ pci_power_name(state));
880	1096
881	1097	/*
882	1098	* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
..	..	@@ -928,11 +1144,26 @@
928	1144	}
929	1145
930	1146	/**
	1147	+ * pci_refresh_power_state - Refresh the given device's power state data
	1148	+ * @dev: Target PCI device.
	1149	+ *
	1150	+ * Ask the platform to refresh the devices power state information and invoke
	1151	+ * pci_update_current_state() to update its current PCI power state.
	1152	+ */
	1153	+void pci_refresh_power_state(struct pci_dev *dev)
	1154	+{
	1155	+ if (platform_pci_power_manageable(dev))
	1156	+ platform_pci_refresh_power_state(dev);
	1157	+
	1158	+ pci_update_current_state(dev, dev->current_state);
	1159	+}
	1160	+
	1161	+/**
931	1162	* pci_platform_power_transition - Use platform to change device power state
932	1163	* @dev: PCI device to handle.
933	1164	* @state: State to put the device into.
934	1165	*/
935		-static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
	1166	+int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
936	1167	{
937	1168	int error;
938	1169
..	..	@@ -948,6 +1179,7 @@
948	1179
949	1180	return error;
950	1181	}
	1182	+EXPORT_SYMBOL_GPL(pci_platform_power_transition);
951	1183
952	1184	/**
953	1185	* pci_wakeup - Wake up a PCI device
..	..	@@ -971,34 +1203,70 @@
971	1203	pci_walk_bus(bus, pci_wakeup, NULL);
972	1204	}
973	1205
974		-/**
975		- * __pci_start_power_transition - Start power transition of a PCI device
976		- * @dev: PCI device to handle.
977		- * @state: State to put the device into.
978		- */
979		-static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
	1206	+static int pci_dev_wait(struct pci_dev dev, char reset_type, int timeout)
980	1207	{
981		- if (state == PCI_D0) {
982		- pci_platform_power_transition(dev, PCI_D0);
983		- /*
984		- * Mandatory power management transition delays, see
985		- * PCI Express Base Specification Revision 2.0 Section
986		- * 6.6.1: Conventional Reset. Do not delay for
987		- * devices powered on/off by corresponding bridge,
988		- * because have already delayed for the bridge.
989		- */
990		- if (dev->runtime_d3cold) {
991		- if (dev->d3cold_delay)
992		- msleep(dev->d3cold_delay);
993		- /*
994		- * When powering on a bridge from D3cold, the
995		- * whole hierarchy may be powered on into
996		- * D0uninitialized state, resume them to give
997		- * them a chance to suspend again
998		- */
999		- pci_wakeup_bus(dev->subordinate);
	1208	+ int delay = 1;
	1209	+ u32 id;
	1210	+
	1211	+ /*
	1212	+ * After reset, the device should not silently discard config
	1213	+ * requests, but it may still indicate that it needs more time by
	1214	+ * responding to them with CRS completions. The Root Port will
	1215	+ * generally synthesize ~0 data to complete the read (except when
	1216	+ * CRS SV is enabled and the read was for the Vendor ID; in that
	1217	+ * case it synthesizes 0x0001 data).
	1218	+ *
	1219	+ * Wait for the device to return a non-CRS completion. Read the
	1220	+ * Command register instead of Vendor ID so we don't have to
	1221	+ * contend with the CRS SV value.
	1222	+ */
	1223	+ pci_read_config_dword(dev, PCI_COMMAND, &id);
	1224	+ while (id == ~0) {
	1225	+ if (delay > timeout) {
	1226	+ pci_warn(dev, "not ready %dms after %s; giving up\n",
	1227	+ delay - 1, reset_type);
	1228	+ return -ENOTTY;
1000	1229	}
	1230	+
	1231	+ if (delay > 1000)
	1232	+ pci_info(dev, "not ready %dms after %s; waiting\n",
	1233	+ delay - 1, reset_type);
	1234	+
	1235	+ msleep(delay);
	1236	+ delay *= 2;
	1237	+ pci_read_config_dword(dev, PCI_COMMAND, &id);
1001	1238	}
	1239	+
	1240	+ if (delay > 1000)
	1241	+ pci_info(dev, "ready %dms after %s\n", delay - 1,
	1242	+ reset_type);
	1243	+
	1244	+ return 0;
	1245	+}
	1246	+
	1247	+/**
	1248	+ * pci_power_up - Put the given device into D0
	1249	+ * @dev: PCI device to power up
	1250	+ */
	1251	+int pci_power_up(struct pci_dev *dev)
	1252	+{
	1253	+ pci_platform_power_transition(dev, PCI_D0);
	1254	+
	1255	+ /*
	1256	+ * Mandatory power management transition delays are handled in
	1257	+ * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
	1258	+ * corresponding bridge.
	1259	+ */
	1260	+ if (dev->runtime_d3cold) {
	1261	+ /*
	1262	+ * When powering on a bridge from D3cold, the whole hierarchy
	1263	+ * may be powered on into D0uninitialized state, resume them to
	1264	+ * give them a chance to suspend again
	1265	+ */
	1266	+ pci_wakeup_bus(dev->subordinate);
	1267	+ }
	1268	+
	1269	+ return pci_raw_set_power_state(dev, PCI_D0);
1002	1270	}
1003	1271
1004	1272	/**
..	..	@@ -1026,27 +1294,6 @@
1026	1294	}
1027	1295
1028	1296	/**
1029		- * __pci_complete_power_transition - Complete power transition of a PCI device
1030		- * @dev: PCI device to handle.
1031		- * @state: State to put the device into.
1032		- *
1033		- * This function should not be called directly by device drivers.
1034		- */
1035		-int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
1036		-{
1037		- int ret;
1038		-
1039		- if (state <= PCI_D0)
1040		- return -EINVAL;
1041		- ret = pci_platform_power_transition(dev, state);
1042		- /* Power off the bridge may power off the whole hierarchy */
1043		- if (!ret && state == PCI_D3cold)
1044		- pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1045		- return ret;
1046		-}
1047		-EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
1048		-
1049		-/**
1050	1297	* pci_set_power_state - Set the power state of a PCI device
1051	1298	* @dev: PCI device to handle.
1052	1299	* @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
..	..	@@ -1067,16 +1314,18 @@
1067	1314	{
1068	1315	int error;
1069	1316
1070		- /* bound the state we're entering */
	1317	+ /* Bound the state we're entering */
1071	1318	if (state > PCI_D3cold)
1072	1319	state = PCI_D3cold;
1073	1320	else if (state < PCI_D0)
1074	1321	state = PCI_D0;
1075	1322	else if ((state == PCI_D1 \|\| state == PCI_D2) && pci_no_d1d2(dev))
	1323	+
1076	1324	/*
1077		- * If the device or the parent bridge do not support PCI PM,
1078		- * ignore the request if we're doing anything other than putting
1079		- * it into D0 (which would only happen on boot).
	1325	+ * If the device or the parent bridge do not support PCI
	1326	+ * PM, ignore the request if we're doing anything other
	1327	+ * than putting it into D0 (which would only happen on
	1328	+ * boot).
1080	1329	*/
1081	1330	return 0;
1082	1331
..	..	@@ -1084,10 +1333,13 @@
1084	1333	if (dev->current_state == state)
1085	1334	return 0;
1086	1335
1087		- __pci_start_power_transition(dev, state);
	1336	+ if (state == PCI_D0)
	1337	+ return pci_power_up(dev);
1088	1338
1089		- /* This device is quirked not to be put into D3, so
1090		- don't put it in D3 */
	1339	+ /*
	1340	+ * This device is quirked not to be put into D3, so don't put it in
	1341	+ * D3
	1342	+ */
1091	1343	if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1092	1344	return 0;
1093	1345
..	..	@@ -1098,34 +1350,26 @@
1098	1350	error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1099	1351	PCI_D3hot : state);
1100	1352
1101		- if (!__pci_complete_power_transition(dev, state))
1102		- error = 0;
	1353	+ if (pci_platform_power_transition(dev, state))
	1354	+ return error;
1103	1355
1104		- return error;
	1356	+ /* Powering off a bridge may power off the whole hierarchy */
	1357	+ if (state == PCI_D3cold)
	1358	+ pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
	1359	+
	1360	+ return 0;
1105	1361	}
1106	1362	EXPORT_SYMBOL(pci_set_power_state);
1107		-
1108		-/**
1109		- * pci_power_up - Put the given device into D0 forcibly
1110		- * @dev: PCI device to power up
1111		- */
1112		-void pci_power_up(struct pci_dev *dev)
1113		-{
1114		- __pci_start_power_transition(dev, PCI_D0);
1115		- pci_raw_set_power_state(dev, PCI_D0);
1116		- pci_update_current_state(dev, PCI_D0);
1117		-}
1118	1363
1119	1364	/**
1120	1365	* pci_choose_state - Choose the power state of a PCI device
1121	1366	* @dev: PCI device to be suspended
1122	1367	* @state: target sleep state for the whole system. This is the value
1123		- * that is passed to suspend() function.
	1368	+ * that is passed to suspend() function.
1124	1369	*
1125	1370	* Returns PCI power state suitable for given device and given system
1126	1371	* message.
1127	1372	*/
1128		-
1129	1373	pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1130	1374	{
1131	1375	pci_power_t ret;
..	..	@@ -1226,7 +1470,6 @@
1226	1470	pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1227	1471	}
1228	1472
1229		-
1230	1473	static int pci_save_pcix_state(struct pci_dev *dev)
1231	1474	{
1232	1475	int pos;
..	..	@@ -1263,17 +1506,60 @@
1263	1506	pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1264	1507	}
1265	1508
	1509	+static void pci_save_ltr_state(struct pci_dev *dev)
	1510	+{
	1511	+ int ltr;
	1512	+ struct pci_cap_saved_state *save_state;
	1513	+ u16 *cap;
	1514	+
	1515	+ if (!pci_is_pcie(dev))
	1516	+ return;
	1517	+
	1518	+ ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
	1519	+ if (!ltr)
	1520	+ return;
	1521	+
	1522	+ save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
	1523	+ if (!save_state) {
	1524	+ pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
	1525	+ return;
	1526	+ }
	1527	+
	1528	+ cap = (u16 *)&save_state->cap.data[0];
	1529	+ pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
	1530	+ pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
	1531	+}
	1532	+
	1533	+static void pci_restore_ltr_state(struct pci_dev *dev)
	1534	+{
	1535	+ struct pci_cap_saved_state *save_state;
	1536	+ int ltr;
	1537	+ u16 *cap;
	1538	+
	1539	+ save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
	1540	+ ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
	1541	+ if (!save_state \|\| !ltr)
	1542	+ return;
	1543	+
	1544	+ cap = (u16 *)&save_state->cap.data[0];
	1545	+ pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
	1546	+ pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
	1547	+}
1266	1548
1267	1549	/**
1268		- * pci_save_state - save the PCI configuration space of a device before suspending
1269		- * @dev: - PCI device that we're dealing with
	1550	+ * pci_save_state - save the PCI configuration space of a device before
	1551	+ * suspending
	1552	+ * @dev: PCI device that we're dealing with
1270	1553	*/
1271	1554	int pci_save_state(struct pci_dev *dev)
1272	1555	{
1273	1556	int i;
1274	1557	/* XXX: 100% dword access ok here? */
1275		- for (i = 0; i < 16; i++)
	1558	+ for (i = 0; i < 16; i++) {
1276	1559	pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
	1560	+ pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
	1561	+ i * 4, dev->saved_config_space[i]);
	1562	+ }
1277	1563	dev->state_saved = true;
1278	1564
1279	1565	i = pci_save_pcie_state(dev);
..	..	@@ -1284,6 +1570,9 @@
1284	1570	if (i != 0)
1285	1571	return i;
1286	1572
	1573	+ pci_save_ltr_state(dev);
	1574	+ pci_save_dpc_state(dev);
	1575	+ pci_save_aer_state(dev);
1287	1576	return pci_save_vc_state(dev);
1288	1577	}
1289	1578	EXPORT_SYMBOL(pci_save_state);
..	..	@@ -1375,22 +1664,29 @@
1375	1664
1376	1665	/**
1377	1666	* pci_restore_state - Restore the saved state of a PCI device
1378		- * @dev: - PCI device that we're dealing with
	1667	+ * @dev: PCI device that we're dealing with
1379	1668	*/
1380	1669	void pci_restore_state(struct pci_dev *dev)
1381	1670	{
1382	1671	if (!dev->state_saved)
1383	1672	return;
1384	1673
1385		- /* PCI Express register must be restored first */
	1674	+ /*
	1675	+ * Restore max latencies (in the LTR capability) before enabling
	1676	+ * LTR itself (in the PCIe capability).
	1677	+ */
	1678	+ pci_restore_ltr_state(dev);
	1679	+
1386	1680	pci_restore_pcie_state(dev);
1387	1681	pci_restore_pasid_state(dev);
1388	1682	pci_restore_pri_state(dev);
1389	1683	pci_restore_ats_state(dev);
1390	1684	pci_restore_vc_state(dev);
1391	1685	pci_restore_rebar_state(dev);
	1686	+ pci_restore_dpc_state(dev);
1392	1687
1393		- pci_cleanup_aer_error_status_regs(dev);
	1688	+ pci_aer_clear_status(dev);
	1689	+ pci_restore_aer_state(dev);
1394	1690
1395	1691	pci_restore_config_space(dev);
1396	1692
..	..	@@ -1407,7 +1703,7 @@
1407	1703
1408	1704	struct pci_saved_state {
1409	1705	u32 config_space[16];
1410		- struct pci_cap_saved_data cap[0];
	1706	+ struct pci_cap_saved_data cap[];
1411	1707	};
1412	1708
1413	1709	/**
..	..	@@ -1546,8 +1842,8 @@
1546	1842	* pci_reenable_device - Resume abandoned device
1547	1843	* @dev: PCI device to be resumed
1548	1844	*
1549		- * Note this function is a backend of pci_default_resume and is not supposed
1550		- * to be called by normal code, write proper resume handler and use it instead.
	1845	+ * NOTE: This function is a backend of pci_default_resume() and is not supposed
	1846	+ * to be called by normal code, write proper resume handler and use it instead.
1551	1847	*/
1552	1848	int pci_reenable_device(struct pci_dev *dev)
1553	1849	{
..	..	@@ -1618,9 +1914,9 @@
1618	1914	* pci_enable_device_io - Initialize a device for use with IO space
1619	1915	* @dev: PCI device to be initialized
1620	1916	*
1621		- * Initialize device before it's used by a driver. Ask low-level code
1622		- * to enable I/O resources. Wake up the device if it was suspended.
1623		- * Beware, this function can fail.
	1917	+ * Initialize device before it's used by a driver. Ask low-level code
	1918	+ * to enable I/O resources. Wake up the device if it was suspended.
	1919	+ * Beware, this function can fail.
1624	1920	*/
1625	1921	int pci_enable_device_io(struct pci_dev *dev)
1626	1922	{
..	..	@@ -1632,9 +1928,9 @@
1632	1928	* pci_enable_device_mem - Initialize a device for use with Memory space
1633	1929	* @dev: PCI device to be initialized
1634	1930	*
1635		- * Initialize device before it's used by a driver. Ask low-level code
1636		- * to enable Memory resources. Wake up the device if it was suspended.
1637		- * Beware, this function can fail.
	1931	+ * Initialize device before it's used by a driver. Ask low-level code
	1932	+ * to enable Memory resources. Wake up the device if it was suspended.
	1933	+ * Beware, this function can fail.
1638	1934	*/
1639	1935	int pci_enable_device_mem(struct pci_dev *dev)
1640	1936	{
..	..	@@ -1646,12 +1942,12 @@
1646	1942	* pci_enable_device - Initialize device before it's used by a driver.
1647	1943	* @dev: PCI device to be initialized
1648	1944	*
1649		- * Initialize device before it's used by a driver. Ask low-level code
1650		- * to enable I/O and memory. Wake up the device if it was suspended.
1651		- * Beware, this function can fail.
	1945	+ * Initialize device before it's used by a driver. Ask low-level code
	1946	+ * to enable I/O and memory. Wake up the device if it was suspended.
	1947	+ * Beware, this function can fail.
1652	1948	*
1653		- * Note we don't actually enable the device many times if we call
1654		- * this function repeatedly (we just increment the count).
	1949	+ * Note we don't actually enable the device many times if we call
	1950	+ * this function repeatedly (we just increment the count).
1655	1951	*/
1656	1952	int pci_enable_device(struct pci_dev *dev)
1657	1953	{
..	..	@@ -1660,8 +1956,8 @@
1660	1956	EXPORT_SYMBOL(pci_enable_device);
1661	1957
1662	1958	/*
1663		- * Managed PCI resources. This manages device on/off, intx/msi/msix
1664		- * on/off and BAR regions. pci_dev itself records msi/msix status, so
	1959	+ * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
	1960	+ * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1665	1961	* there's no need to track it separately. pci_devres is initialized
1666	1962	* when a device is enabled using managed PCI device enable interface.
1667	1963	*/
..	..	@@ -1779,7 +2075,8 @@
1779	2075	}
1780	2076
1781	2077	/**
1782		- * pcibios_release_device - provide arch specific hooks when releasing device dev
	2078	+ * pcibios_release_device - provide arch specific hooks when releasing
	2079	+ * device dev
1783	2080	* @dev: the PCI device being released
1784	2081	*
1785	2082	* Permits the platform to provide architecture specific functionality when
..	..	@@ -1870,8 +2167,7 @@
1870	2167	* @dev: the PCIe device reset
1871	2168	* @state: Reset state to enter into
1872	2169	*
1873		- *
1874		- * Sets the PCIe reset state for the device. This is the default
	2170	+ * Set the PCIe reset state for the device. This is the default
1875	2171	* implementation. Architecture implementations can override this.
1876	2172	*/
1877	2173	int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
..	..	@@ -1885,7 +2181,6 @@
1885	2181	* @dev: the PCIe device reset
1886	2182	* @state: Reset state to enter into
1887	2183	*
1888		- *
1889	2184	* Sets the PCI reset state for the device.
1890	2185	*/
1891	2186	int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
..	..	@@ -1893,6 +2188,14 @@
1893	2188	return pcibios_set_pcie_reset_state(dev, state);
1894	2189	}
1895	2190	EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
	2191	+
	2192	+void pcie_clear_device_status(struct pci_dev *dev)
	2193	+{
	2194	+ u16 sta;
	2195	+
	2196	+ pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
	2197	+ pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
	2198	+}
1896	2199
1897	2200	/**
1898	2201	* pcie_clear_root_pme_status - Clear root port PME interrupt status.
..	..	@@ -2147,10 +2450,13 @@
2147	2450	int ret = 0;
2148	2451
2149	2452	/*
2150		- * Bridges can only signal wakeup on behalf of subordinate devices,
2151		- * but that is set up elsewhere, so skip them.
	2453	+ * Bridges that are not power-manageable directly only signal
	2454	+ * wakeup on behalf of subordinate devices which is set up
	2455	+ * elsewhere, so skip them. However, bridges that are
	2456	+ * power-manageable may signal wakeup for themselves (for example,
	2457	+ * on a hotplug event) and they need to be covered here.
2152	2458	*/
2153		- if (pci_has_subordinate(dev))
	2459	+ if (!pci_power_manageable(dev))
2154	2460	return 0;
2155	2461
2156	2462	/* Don't do the same thing twice in a row for one device. */
..	..	@@ -2258,7 +2564,7 @@
2258	2564	case PCI_D2:
2259	2565	if (pci_no_d1d2(dev))
2260	2566	break;
2261		- /* else: fall through */
	2567	+ fallthrough;
2262	2568	default:
2263	2569	target_state = state;
2264	2570	}
..	..	@@ -2297,7 +2603,8 @@
2297	2603	}
2298	2604
2299	2605	/**
2300		- * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
	2606	+ * pci_prepare_to_sleep - prepare PCI device for system-wide transition
	2607	+ * into a sleep state
2301	2608	* @dev: Device to handle.
2302	2609	*
2303	2610	* Choose the power state appropriate for the device depending on whether
..	..	@@ -2325,7 +2632,8 @@
2325	2632	EXPORT_SYMBOL(pci_prepare_to_sleep);
2326	2633
2327	2634	/**
2328		- * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
	2635	+ * pci_back_from_sleep - turn PCI device on during system-wide transition
	2636	+ * into working state
2329	2637	* @dev: Device to handle.
2330	2638	*
2331	2639	* Disable device's system wake-up capability and put it into D0.
..	..	@@ -2407,45 +2715,56 @@
2407	2715	EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2408	2716
2409	2717	/**
2410		- * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
	2718	+ * pci_dev_need_resume - Check if it is necessary to resume the device.
2411	2719	* @pci_dev: Device to check.
2412	2720	*
2413		- * Return 'true' if the device is runtime-suspended, it doesn't have to be
	2721	+ * Return 'true' if the device is not runtime-suspended or it has to be
2414	2722	* reconfigured due to wakeup settings difference between system and runtime
2415		- * suspend and the current power state of it is suitable for the upcoming
2416		- * (system) transition.
2417		- *
2418		- * If the device is not configured for system wakeup, disable PME for it before
2419		- * returning 'true' to prevent it from waking up the system unnecessarily.
	2723	+ * suspend, or the current power state of it is not suitable for the upcoming
	2724	+ * (system-wide) transition.
2420	2725	*/
2421		-bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
	2726	+bool pci_dev_need_resume(struct pci_dev *pci_dev)
2422	2727	{
2423	2728	struct device *dev = &pci_dev->dev;
2424		- bool wakeup = device_may_wakeup(dev);
	2729	+ pci_power_t target_state;
2425	2730
2426		- if (!pm_runtime_suspended(dev)
2427		- \|\| pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2428		- \|\| platform_pci_need_resume(pci_dev))
2429		- return false;
	2731	+ if (!pm_runtime_suspended(dev) \|\| platform_pci_need_resume(pci_dev))
	2732	+ return true;
	2733	+
	2734	+ target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2430	2735
2431	2736	/*
2432		- * At this point the device is good to go unless it's been configured
2433		- * to generate PME at the runtime suspend time, but it is not supposed
2434		- * to wake up the system. In that case, simply disable PME for it
2435		- * (it will have to be re-enabled on exit from system resume).
2436		- *
2437		- * If the device's power state is D3cold and the platform check above
2438		- * hasn't triggered, the device's configuration is suitable and we don't
2439		- * need to manipulate it at all.
	2737	+ * If the earlier platform check has not triggered, D3cold is just power
	2738	+ * removal on top of D3hot, so no need to resume the device in that
	2739	+ * case.
2440	2740	*/
	2741	+ return target_state != pci_dev->current_state &&
	2742	+ target_state != PCI_D3cold &&
	2743	+ pci_dev->current_state != PCI_D3hot;
	2744	+}
	2745	+
	2746	+/**
	2747	+ * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
	2748	+ * @pci_dev: Device to check.
	2749	+ *
	2750	+ * If the device is suspended and it is not configured for system wakeup,
	2751	+ * disable PME for it to prevent it from waking up the system unnecessarily.
	2752	+ *
	2753	+ * Note that if the device's power state is D3cold and the platform check in
	2754	+ * pci_dev_need_resume() has not triggered, the device's configuration need not
	2755	+ * be changed.
	2756	+ */
	2757	+void pci_dev_adjust_pme(struct pci_dev *pci_dev)
	2758	+{
	2759	+ struct device *dev = &pci_dev->dev;
	2760	+
2441	2761	spin_lock_irq(&dev->power.lock);
2442	2762
2443		- if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2444		- !wakeup)
	2763	+ if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
	2764	+ pci_dev->current_state < PCI_D3cold)
2445	2765	__pci_pme_active(pci_dev, false);
2446	2766
2447	2767	spin_unlock_irq(&dev->power.lock);
2448		- return true;
2449	2768	}
2450	2769
2451	2770	/**
..	..	@@ -2518,6 +2837,18 @@
2518	2837	DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2519	2838	},
2520	2839	},
	2840	+ {
	2841	+ /*
	2842	+ * Downstream device is not accessible after putting a root port
	2843	+ * into D3cold and back into D0 on Elo i2.
	2844	+ */
	2845	+ .ident = "Elo i2",
	2846	+ .matches = {
	2847	+ DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"),
	2848	+ DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"),
	2849	+ DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"),
	2850	+ },
	2851	+ },
2521	2852	#endif
2522	2853	{ }
2523	2854	};
..	..	@@ -2553,6 +2884,10 @@
2553	2884
2554	2885	/* Even the oldest 2010 Thunderbolt controller supports D3. */
2555	2886	if (bridge->is_thunderbolt)
	2887	+ return true;
	2888	+
	2889	+ /* Platform might know better if the bridge supports D3 */
	2890	+ if (platform_pci_bridge_d3(bridge))
2556	2891	return true;
2557	2892
2558	2893	/*
..	..	@@ -2691,6 +3026,7 @@
2691	3026	void pci_pm_init(struct pci_dev *dev)
2692	3027	{
2693	3028	int pm;
	3029	+ u16 status;
2694	3030	u16 pmc;
2695	3031
2696	3032	pm_runtime_forbid(&dev->dev);
..	..	@@ -2716,7 +3052,7 @@
2716	3052	}
2717	3053
2718	3054	dev->pm_cap = pm;
2719		- dev->d3_delay = PCI_PM_D3_WAIT;
	3055	+ dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
2720	3056	dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2721	3057	dev->bridge_d3 = pci_bridge_d3_possible(dev);
2722	3058	dev->d3cold_allowed = true;
..	..	@@ -2730,18 +3066,18 @@
2730	3066	dev->d2_support = true;
2731	3067
2732	3068	if (dev->d1_support \|\| dev->d2_support)
2733		- pci_printk(KERN_DEBUG, dev, "supports%s%s\n",
	3069	+ pci_info(dev, "supports%s%s\n",
2734	3070	dev->d1_support ? " D1" : "",
2735	3071	dev->d2_support ? " D2" : "");
2736	3072	}
2737	3073
2738	3074	pmc &= PCI_PM_CAP_PME_MASK;
2739	3075	if (pmc) {
2740		- pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n",
	3076	+ pci_info(dev, "PME# supported from%s%s%s%s%s\n",
2741	3077	(pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2742	3078	(pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2743	3079	(pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2744		- (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
	3080	+ (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
2745	3081	(pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2746	3082	dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2747	3083	dev->pme_poll = true;
..	..	@@ -2753,6 +3089,10 @@
2753	3089	/* Disable the PME# generation functionality */
2754	3090	pci_pme_active(dev, false);
2755	3091	}
	3092	+
	3093	+ pci_read_config_word(dev, PCI_STATUS, &status);
	3094	+ if (status & PCI_STATUS_IMM_READY)
	3095	+ dev->imm_ready = 1;
2756	3096	}
2757	3097
2758	3098	static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
..	..	@@ -2901,16 +3241,16 @@
2901	3241	res->flags = flags;
2902	3242
2903	3243	if (bei <= PCI_EA_BEI_BAR5)
2904		- pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
	3244	+ pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2905	3245	bei, res, prop);
2906	3246	else if (bei == PCI_EA_BEI_ROM)
2907		- pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
	3247	+ pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2908	3248	res, prop);
2909	3249	else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2910		- pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
	3250	+ pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2911	3251	bei - PCI_EA_BEI_VF_BAR0, res, prop);
2912	3252	else
2913		- pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
	3253	+ pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2914	3254	bei, res, prop);
2915	3255
2916	3256	out:
..	..	@@ -2954,7 +3294,7 @@
2954	3294
2955	3295	/**
2956	3296	* _pci_add_cap_save_buffer - allocate buffer for saving given
2957		- * capability registers
	3297	+ * capability registers
2958	3298	* @dev: the PCI device
2959	3299	* @cap: the capability to allocate the buffer for
2960	3300	* @extended: Standard or Extended capability ID
..	..	@@ -3013,6 +3353,11 @@
3013	3353	if (error)
3014	3354	pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3015	3355
	3356	+ error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
	3357	+ 2 * sizeof(u16));
	3358	+ if (error)
	3359	+ pci_err(dev, "unable to allocate suspend buffer for LTR\n");
	3360	+
3016	3361	pci_allocate_vc_save_buffers(dev);
3017	3362	}
3018	3363
..	..	@@ -3059,140 +3404,12 @@
3059	3404	}
3060	3405	}
3061	3406
3062		-static int pci_acs_enable;
3063		-
3064		-/**
3065		- * pci_request_acs - ask for ACS to be enabled if supported
3066		- */
3067		-void pci_request_acs(void)
3068		-{
3069		- pci_acs_enable = 1;
3070		-}
3071		-EXPORT_SYMBOL_GPL(pci_request_acs);
3072		-
3073		-static const char *disable_acs_redir_param;
3074		-
3075		-/**
3076		- * pci_disable_acs_redir - disable ACS redirect capabilities
3077		- * @dev: the PCI device
3078		- *
3079		- * For only devices specified in the disable_acs_redir parameter.
3080		- */
3081		-static void pci_disable_acs_redir(struct pci_dev *dev)
3082		-{
3083		- int ret = 0;
3084		- const char *p;
3085		- int pos;
3086		- u16 ctrl;
3087		-
3088		- if (!disable_acs_redir_param)
3089		- return;
3090		-
3091		- p = disable_acs_redir_param;
3092		- while (*p) {
3093		- ret = pci_dev_str_match(dev, p, &p);
3094		- if (ret < 0) {
3095		- pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
3096		- disable_acs_redir_param);
3097		-
3098		- break;
3099		- } else if (ret == 1) {
3100		- /* Found a match */
3101		- break;
3102		- }
3103		-
3104		- if (p != ';' && p != ',') {
3105		- /* End of param or invalid format */
3106		- break;
3107		- }
3108		- p++;
3109		- }
3110		-
3111		- if (ret != 1)
3112		- return;
3113		-
3114		- if (!pci_dev_specific_disable_acs_redir(dev))
3115		- return;
3116		-
3117		- pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3118		- if (!pos) {
3119		- pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
3120		- return;
3121		- }
3122		-
3123		- pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
3124		-
3125		- /* P2P Request & Completion Redirect */
3126		- ctrl &= ~(PCI_ACS_RR \| PCI_ACS_CR \| PCI_ACS_EC);
3127		-
3128		- pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
3129		-
3130		- pci_info(dev, "disabled ACS redirect\n");
3131		-}
3132		-
3133		-/**
3134		- * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
3135		- * @dev: the PCI device
3136		- */
3137		-static void pci_std_enable_acs(struct pci_dev *dev)
3138		-{
3139		- int pos;
3140		- u16 cap;
3141		- u16 ctrl;
3142		-
3143		- pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3144		- if (!pos)
3145		- return;
3146		-
3147		- pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
3148		- pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
3149		-
3150		- /* Source Validation */
3151		- ctrl \|= (cap & PCI_ACS_SV);
3152		-
3153		- /* P2P Request Redirect */
3154		- ctrl \|= (cap & PCI_ACS_RR);
3155		-
3156		- /* P2P Completion Redirect */
3157		- ctrl \|= (cap & PCI_ACS_CR);
3158		-
3159		- /* Upstream Forwarding */
3160		- ctrl \|= (cap & PCI_ACS_UF);
3161		-
3162		- pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
3163		-}
3164		-
3165		-/**
3166		- * pci_enable_acs - enable ACS if hardware support it
3167		- * @dev: the PCI device
3168		- */
3169		-void pci_enable_acs(struct pci_dev *dev)
3170		-{
3171		- if (!pci_acs_enable)
3172		- goto disable_acs_redir;
3173		-
3174		- if (!pci_dev_specific_enable_acs(dev))
3175		- goto disable_acs_redir;
3176		-
3177		- pci_std_enable_acs(dev);
3178		-
3179		-disable_acs_redir:
3180		- /*
3181		- * Note: pci_disable_acs_redir() must be called even if ACS was not
3182		- * enabled by the kernel because it may have been enabled by
3183		- * platform firmware. So if we are told to disable it, we should
3184		- * always disable it after setting the kernel's default
3185		- * preferences.
3186		- */
3187		- pci_disable_acs_redir(dev);
3188		-}
3189		-
3190	3407	static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3191	3408	{
3192	3409	int pos;
3193	3410	u16 cap, ctrl;
3194	3411
3195		- pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
	3412	+ pos = pdev->acs_cap;
3196	3413	if (!pos)
3197	3414	return false;
3198	3415
..	..	@@ -3315,6 +3532,23 @@
3315	3532	} while (pdev != end);
3316	3533
3317	3534	return true;
	3535	+}
	3536	+
	3537	+/**
	3538	+ * pci_acs_init - Initialize ACS if hardware supports it
	3539	+ * @dev: the PCI device
	3540	+ */
	3541	+void pci_acs_init(struct pci_dev *dev)
	3542	+{
	3543	+ dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	3544	+
	3545	+ /*
	3546	+ * Attempt to enable ACS regardless of capability because some Root
	3547	+ * Ports (e.g. those quirked with _intel_pch_acs_) do not have
	3548	+ * the standard ACS capability but still support ACS via those
	3549	+ * quirks.
	3550	+ */
	3551	+ pci_enable_acs(dev);
3318	3552	}
3319	3553
3320	3554	/**
..	..	@@ -3484,7 +3718,7 @@
3484	3718	}
3485	3719
3486	3720	/* Ensure upstream ports don't block AtomicOps on egress */
3487		- if (!bridge->has_secondary_link) {
	3721	+ if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3488	3722	pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3489	3723	&ctl2);
3490	3724	if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
..	..	@@ -3561,13 +3795,14 @@
3561	3795	EXPORT_SYMBOL_GPL(pci_common_swizzle);
3562	3796
3563	3797	/**
3564		- * pci_release_region - Release a PCI bar
3565		- * @pdev: PCI device whose resources were previously reserved by pci_request_region
3566		- * @bar: BAR to release
	3798	+ * pci_release_region - Release a PCI bar
	3799	+ * @pdev: PCI device whose resources were previously reserved by
	3800	+ * pci_request_region()
	3801	+ * @bar: BAR to release
3567	3802	*
3568		- * Releases the PCI I/O and memory resources previously reserved by a
3569		- * successful call to pci_request_region. Call this function only
3570		- * after all use of the PCI regions has ceased.
	3803	+ * Releases the PCI I/O and memory resources previously reserved by a
	3804	+ * successful call to pci_request_region(). Call this function only
	3805	+ * after all use of the PCI regions has ceased.
3571	3806	*/
3572	3807	void pci_release_region(struct pci_dev *pdev, int bar)
3573	3808	{
..	..	@@ -3589,23 +3824,23 @@
3589	3824	EXPORT_SYMBOL(pci_release_region);
3590	3825
3591	3826	/**
3592		- * __pci_request_region - Reserved PCI I/O and memory resource
3593		- * @pdev: PCI device whose resources are to be reserved
3594		- * @bar: BAR to be reserved
3595		- * @res_name: Name to be associated with resource.
3596		- * @exclusive: whether the region access is exclusive or not
	3827	+ * __pci_request_region - Reserved PCI I/O and memory resource
	3828	+ * @pdev: PCI device whose resources are to be reserved
	3829	+ * @bar: BAR to be reserved
	3830	+ * @res_name: Name to be associated with resource.
	3831	+ * @exclusive: whether the region access is exclusive or not
3597	3832	*
3598		- * Mark the PCI region associated with PCI device @pdev BR @bar as
3599		- * being reserved by owner @res_name. Do not access any
3600		- * address inside the PCI regions unless this call returns
3601		- * successfully.
	3833	+ * Mark the PCI region associated with PCI device @pdev BAR @bar as
	3834	+ * being reserved by owner @res_name. Do not access any
	3835	+ * address inside the PCI regions unless this call returns
	3836	+ * successfully.
3602	3837	*
3603		- * If @exclusive is set, then the region is marked so that userspace
3604		- * is explicitly not allowed to map the resource via /dev/mem or
3605		- * sysfs MMIO access.
	3838	+ * If @exclusive is set, then the region is marked so that userspace
	3839	+ * is explicitly not allowed to map the resource via /dev/mem or
	3840	+ * sysfs MMIO access.
3606	3841	*
3607		- * Returns 0 on success, or %EBUSY on error. A warning
3608		- * message is also printed on failure.
	3842	+ * Returns 0 on success, or %EBUSY on error. A warning
	3843	+ * message is also printed on failure.
3609	3844	*/
3610	3845	static int __pci_request_region(struct pci_dev *pdev, int bar,
3611	3846	const char *res_name, int exclusive)
..	..	@@ -3639,49 +3874,24 @@
3639	3874	}
3640	3875
3641	3876	/**
3642		- * pci_request_region - Reserve PCI I/O and memory resource
3643		- * @pdev: PCI device whose resources are to be reserved
3644		- * @bar: BAR to be reserved
3645		- * @res_name: Name to be associated with resource
	3877	+ * pci_request_region - Reserve PCI I/O and memory resource
	3878	+ * @pdev: PCI device whose resources are to be reserved
	3879	+ * @bar: BAR to be reserved
	3880	+ * @res_name: Name to be associated with resource
3646	3881	*
3647		- * Mark the PCI region associated with PCI device @pdev BAR @bar as
3648		- * being reserved by owner @res_name. Do not access any
3649		- * address inside the PCI regions unless this call returns
3650		- * successfully.
	3882	+ * Mark the PCI region associated with PCI device @pdev BAR @bar as
	3883	+ * being reserved by owner @res_name. Do not access any
	3884	+ * address inside the PCI regions unless this call returns
	3885	+ * successfully.
3651	3886	*
3652		- * Returns 0 on success, or %EBUSY on error. A warning
3653		- * message is also printed on failure.
	3887	+ * Returns 0 on success, or %EBUSY on error. A warning
	3888	+ * message is also printed on failure.
3654	3889	*/
3655	3890	int pci_request_region(struct pci_dev pdev, int bar, const char res_name)
3656	3891	{
3657	3892	return __pci_request_region(pdev, bar, res_name, 0);
3658	3893	}
3659	3894	EXPORT_SYMBOL(pci_request_region);
3660		-
3661		-/**
3662		- * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3663		- * @pdev: PCI device whose resources are to be reserved
3664		- * @bar: BAR to be reserved
3665		- * @res_name: Name to be associated with resource.
3666		- *
3667		- * Mark the PCI region associated with PCI device @pdev BR @bar as
3668		- * being reserved by owner @res_name. Do not access any
3669		- * address inside the PCI regions unless this call returns
3670		- * successfully.
3671		- *
3672		- * Returns 0 on success, or %EBUSY on error. A warning
3673		- * message is also printed on failure.
3674		- *
3675		- * The key difference that _exclusive makes it that userspace is
3676		- * explicitly not allowed to map the resource via /dev/mem or
3677		- * sysfs.
3678		- */
3679		-int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3680		- const char *res_name)
3681		-{
3682		- return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3683		-}
3684		-EXPORT_SYMBOL(pci_request_region_exclusive);
3685	3895
3686	3896	/**
3687	3897	* pci_release_selected_regions - Release selected PCI I/O and memory resources
..	..	@@ -3695,7 +3905,7 @@
3695	3905	{
3696	3906	int i;
3697	3907
3698		- for (i = 0; i < 6; i++)
	3908	+ for (i = 0; i < PCI_STD_NUM_BARS; i++)
3699	3909	if (bars & (1 << i))
3700	3910	pci_release_region(pdev, i);
3701	3911	}
..	..	@@ -3706,7 +3916,7 @@
3706	3916	{
3707	3917	int i;
3708	3918
3709		- for (i = 0; i < 6; i++)
	3919	+ for (i = 0; i < PCI_STD_NUM_BARS; i++)
3710	3920	if (bars & (1 << i))
3711	3921	if (__pci_request_region(pdev, i, res_name, excl))
3712	3922	goto err_out;
..	..	@@ -3743,65 +3953,66 @@
3743	3953	EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3744	3954
3745	3955	/**
3746		- * pci_release_regions - Release reserved PCI I/O and memory resources
3747		- * @pdev: PCI device whose resources were previously reserved by pci_request_regions
	3956	+ * pci_release_regions - Release reserved PCI I/O and memory resources
	3957	+ * @pdev: PCI device whose resources were previously reserved by
	3958	+ * pci_request_regions()
3748	3959	*
3749		- * Releases all PCI I/O and memory resources previously reserved by a
3750		- * successful call to pci_request_regions. Call this function only
3751		- * after all use of the PCI regions has ceased.
	3960	+ * Releases all PCI I/O and memory resources previously reserved by a
	3961	+ * successful call to pci_request_regions(). Call this function only
	3962	+ * after all use of the PCI regions has ceased.
3752	3963	*/
3753	3964
3754	3965	void pci_release_regions(struct pci_dev *pdev)
3755	3966	{
3756		- pci_release_selected_regions(pdev, (1 << 6) - 1);
	3967	+ pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
3757	3968	}
3758	3969	EXPORT_SYMBOL(pci_release_regions);
3759	3970
3760	3971	/**
3761		- * pci_request_regions - Reserved PCI I/O and memory resources
3762		- * @pdev: PCI device whose resources are to be reserved
3763		- * @res_name: Name to be associated with resource.
	3972	+ * pci_request_regions - Reserve PCI I/O and memory resources
	3973	+ * @pdev: PCI device whose resources are to be reserved
	3974	+ * @res_name: Name to be associated with resource.
3764	3975	*
3765		- * Mark all PCI regions associated with PCI device @pdev as
3766		- * being reserved by owner @res_name. Do not access any
3767		- * address inside the PCI regions unless this call returns
3768		- * successfully.
	3976	+ * Mark all PCI regions associated with PCI device @pdev as
	3977	+ * being reserved by owner @res_name. Do not access any
	3978	+ * address inside the PCI regions unless this call returns
	3979	+ * successfully.
3769	3980	*
3770		- * Returns 0 on success, or %EBUSY on error. A warning
3771		- * message is also printed on failure.
	3981	+ * Returns 0 on success, or %EBUSY on error. A warning
	3982	+ * message is also printed on failure.
3772	3983	*/
3773	3984	int pci_request_regions(struct pci_dev pdev, const char res_name)
3774	3985	{
3775		- return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
	3986	+ return pci_request_selected_regions(pdev,
	3987	+ ((1 << PCI_STD_NUM_BARS) - 1), res_name);
3776	3988	}
3777	3989	EXPORT_SYMBOL(pci_request_regions);
3778	3990
3779	3991	/**
3780		- * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3781		- * @pdev: PCI device whose resources are to be reserved
3782		- * @res_name: Name to be associated with resource.
	3992	+ * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
	3993	+ * @pdev: PCI device whose resources are to be reserved
	3994	+ * @res_name: Name to be associated with resource.
3783	3995	*
3784		- * Mark all PCI regions associated with PCI device @pdev as
3785		- * being reserved by owner @res_name. Do not access any
3786		- * address inside the PCI regions unless this call returns
3787		- * successfully.
	3996	+ * Mark all PCI regions associated with PCI device @pdev as being reserved
	3997	+ * by owner @res_name. Do not access any address inside the PCI regions
	3998	+ * unless this call returns successfully.
3788	3999	*
3789		- * pci_request_regions_exclusive() will mark the region so that
3790		- * /dev/mem and the sysfs MMIO access will not be allowed.
	4000	+ * pci_request_regions_exclusive() will mark the region so that /dev/mem
	4001	+ * and the sysfs MMIO access will not be allowed.
3791	4002	*
3792		- * Returns 0 on success, or %EBUSY on error. A warning
3793		- * message is also printed on failure.
	4003	+ * Returns 0 on success, or %EBUSY on error. A warning message is also
	4004	+ * printed on failure.
3794	4005	*/
3795	4006	int pci_request_regions_exclusive(struct pci_dev pdev, const char res_name)
3796	4007	{
3797	4008	return pci_request_selected_regions_exclusive(pdev,
3798		- ((1 << 6) - 1), res_name);
	4009	+ ((1 << PCI_STD_NUM_BARS) - 1), res_name);
3799	4010	}
3800	4011	EXPORT_SYMBOL(pci_request_regions_exclusive);
3801	4012
3802	4013	/*
3803	4014	* Record the PCI IO range (expressed as CPU physical address + size).
3804		- * Return a negative value if an error has occured, zero otherwise
	4015	+ * Return a negative value if an error has occurred, zero otherwise
3805	4016	*/
3806	4017	int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
3807	4018	resource_size_t size)
..	..	@@ -3847,6 +4058,7 @@
3847	4058
3848	4059	return address;
3849	4060	}
	4061	+EXPORT_SYMBOL_GPL(pci_pio_to_address);
3850	4062
3851	4063	unsigned long __weak pci_address_to_pio(phys_addr_t address)
3852	4064	{
..	..	@@ -3861,14 +4073,14 @@
3861	4073	}
3862	4074
3863	4075	/**
3864		- * pci_remap_iospace - Remap the memory mapped I/O space
3865		- * @res: Resource describing the I/O space
3866		- * @phys_addr: physical address of range to be mapped
	4076	+ * pci_remap_iospace - Remap the memory mapped I/O space
	4077	+ * @res: Resource describing the I/O space
	4078	+ * @phys_addr: physical address of range to be mapped
3867	4079	*
3868		- * Remap the memory mapped I/O space described by the @res
3869		- * and the CPU physical address @phys_addr into virtual address space.
3870		- * Only architectures that have memory mapped IO functions defined
3871		- * (and the PCI_IOBASE value defined) should call this function.
	4080	+ * Remap the memory mapped I/O space described by the @res and the CPU
	4081	+ * physical address @phys_addr into virtual address space. Only
	4082	+ * architectures that have memory mapped IO functions defined (and the
	4083	+ * PCI_IOBASE value defined) should call this function.
3872	4084	*/
3873	4085	int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3874	4086	{
..	..	@@ -3884,8 +4096,10 @@
3884	4096	return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3885	4097	pgprot_device(PAGE_KERNEL));
3886	4098	#else
3887		- /* this architecture does not have memory mapped I/O space,
3888		- so this function should never be called */
	4099	+ /*
	4100	+ * This architecture does not have memory mapped I/O space,
	4101	+ * so this function should never be called
	4102	+ */
3889	4103	WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3890	4104	return -ENODEV;
3891	4105	#endif
..	..	@@ -3893,12 +4107,12 @@
3893	4107	EXPORT_SYMBOL(pci_remap_iospace);
3894	4108
3895	4109	/**
3896		- * pci_unmap_iospace - Unmap the memory mapped I/O space
3897		- * @res: resource to be unmapped
	4110	+ * pci_unmap_iospace - Unmap the memory mapped I/O space
	4111	+ * @res: resource to be unmapped
3898	4112	*
3899		- * Unmap the CPU virtual address @res from virtual address space.
3900		- * Only architectures that have memory mapped IO functions defined
3901		- * (and the PCI_IOBASE value defined) should call this function.
	4113	+ * Unmap the CPU virtual address @res from virtual address space. Only
	4114	+ * architectures that have memory mapped IO functions defined (and the
	4115	+ * PCI_IOBASE value defined) should call this function.
3902	4116	*/
3903	4117	void pci_unmap_iospace(struct resource *res)
3904	4118	{
..	..	@@ -4141,7 +4355,7 @@
4141	4355	if (cacheline_size == pci_cache_line_size)
4142	4356	return 0;
4143	4357
4144		- pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n",
	4358	+ pci_info(dev, "cache line size of %d is not supported\n",
4145	4359	pci_cache_line_size << 2);
4146	4360
4147	4361	return -EINVAL;
..	..	@@ -4244,7 +4458,7 @@
4244	4458	* @pdev: the PCI device to operate on
4245	4459	* @enable: boolean: whether to enable or disable PCI INTx
4246	4460	*
4247		- * Enables/disables PCI INTx for device dev
	4461	+ * Enables/disables PCI INTx for device @pdev
4248	4462	*/
4249	4463	void pci_intx(struct pci_dev *pdev, int enable)
4250	4464	{
..	..	@@ -4320,9 +4534,8 @@
4320	4534	* pci_check_and_mask_intx - mask INTx on pending interrupt
4321	4535	* @dev: the PCI device to operate on
4322	4536	*
4323		- * Check if the device dev has its INTx line asserted, mask it and
4324		- * return true in that case. False is returned if no interrupt was
4325		- * pending.
	4537	+ * Check if the device dev has its INTx line asserted, mask it and return
	4538	+ * true in that case. False is returned if no interrupt was pending.
4326	4539	*/
4327	4540	bool pci_check_and_mask_intx(struct pci_dev *dev)
4328	4541	{
..	..	@@ -4334,9 +4547,9 @@
4334	4547	* pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4335	4548	* @dev: the PCI device to operate on
4336	4549	*
4337		- * Check if the device dev has its INTx line asserted, unmask it if not
4338		- * and return true. False is returned and the mask remains active if
4339		- * there was still an interrupt pending.
	4550	+ * Check if the device dev has its INTx line asserted, unmask it if not and
	4551	+ * return true. False is returned and the mask remains active if there was
	4552	+ * still an interrupt pending.
4340	4553	*/
4341	4554	bool pci_check_and_unmask_intx(struct pci_dev *dev)
4342	4555	{
..	..	@@ -4345,7 +4558,7 @@
4345	4558	EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4346	4559
4347	4560	/**
4348		- * pci_wait_for_pending_transaction - waits for pending transaction
	4561	+ * pci_wait_for_pending_transaction - wait for pending transaction
4349	4562	* @dev: the PCI device to operate on
4350	4563	*
4351	4564	* Return 0 if transaction is pending 1 otherwise.
..	..	@@ -4360,50 +4573,9 @@
4360	4573	}
4361	4574	EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4362	4575
4363		-static int pci_dev_wait(struct pci_dev dev, char reset_type, int timeout)
4364		-{
4365		- int delay = 1;
4366		- u32 id;
4367		-
4368		- /*
4369		- * After reset, the device should not silently discard config
4370		- * requests, but it may still indicate that it needs more time by
4371		- * responding to them with CRS completions. The Root Port will
4372		- * generally synthesize ~0 data to complete the read (except when
4373		- * CRS SV is enabled and the read was for the Vendor ID; in that
4374		- * case it synthesizes 0x0001 data).
4375		- *
4376		- * Wait for the device to return a non-CRS completion. Read the
4377		- * Command register instead of Vendor ID so we don't have to
4378		- * contend with the CRS SV value.
4379		- */
4380		- pci_read_config_dword(dev, PCI_COMMAND, &id);
4381		- while (id == ~0) {
4382		- if (delay > timeout) {
4383		- pci_warn(dev, "not ready %dms after %s; giving up\n",
4384		- delay - 1, reset_type);
4385		- return -ENOTTY;
4386		- }
4387		-
4388		- if (delay > 1000)
4389		- pci_info(dev, "not ready %dms after %s; waiting\n",
4390		- delay - 1, reset_type);
4391		-
4392		- msleep(delay);
4393		- delay *= 2;
4394		- pci_read_config_dword(dev, PCI_COMMAND, &id);
4395		- }
4396		-
4397		- if (delay > 1000)
4398		- pci_info(dev, "ready %dms after %s\n", delay - 1,
4399		- reset_type);
4400		-
4401		- return 0;
4402		-}
4403		-
4404	4576	/**
4405	4577	* pcie_has_flr - check if a device supports function level resets
4406		- * @dev: device to check
	4578	+ * @dev: device to check
4407	4579	*
4408	4580	* Returns true if the device advertises support for PCIe function level
4409	4581	* resets.
..	..	@@ -4422,7 +4594,7 @@
4422	4594
4423	4595	/**
4424	4596	* pcie_flr - initiate a PCIe function level reset
4425		- * @dev: device to reset
	4597	+ * @dev: device to reset
4426	4598	*
4427	4599	* Initiate a function level reset on @dev. The caller should ensure the
4428	4600	* device supports FLR before calling this function, e.g. by using the
..	..	@@ -4434,6 +4606,9 @@
4434	4606	pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4435	4607
4436	4608	pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
	4609	+
	4610	+ if (dev->imm_ready)
	4611	+ return 0;
4437	4612
4438	4613	/*
4439	4614	* Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
..	..	@@ -4467,7 +4642,7 @@
4467	4642
4468	4643	/*
4469	4644	* Wait for Transaction Pending bit to clear. A word-aligned test
4470		- * is used, so we use the conrol offset rather than status and shift
	4645	+ * is used, so we use the control offset rather than status and shift
4471	4646	* the test bit to match.
4472	4647	*/
4473	4648	if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
..	..	@@ -4475,6 +4650,9 @@
4475	4650	pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4476	4651
4477	4652	pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
	4653	+
	4654	+ if (dev->imm_ready)
	4655	+ return 0;
4478	4656
4479	4657	/*
4480	4658	* Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
..	..	@@ -4499,7 +4677,7 @@
4499	4677	*
4500	4678	* NOTE: This causes the caller to sleep for twice the device power transition
4501	4679	* cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4502		- * by default (i.e. unless the @dev's d3_delay field has a different value).
	4680	+ * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4503	4681	* Moreover, only devices in D0 can be reset by this function.
4504	4682	*/
4505	4683	static int pci_pm_reset(struct pci_dev *dev, int probe)
..	..	@@ -4529,8 +4707,60 @@
4529	4707	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4530	4708	pci_dev_d3_sleep(dev);
4531	4709
4532		- return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
	4710	+ return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4533	4711	}
	4712	+
	4713	+/**
	4714	+ * pcie_wait_for_link_delay - Wait until link is active or inactive
	4715	+ * @pdev: Bridge device
	4716	+ * @active: waiting for active or inactive?
	4717	+ * @delay: Delay to wait after link has become active (in ms)
	4718	+ *
	4719	+ * Use this to wait till link becomes active or inactive.
	4720	+ */
	4721	+static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
	4722	+ int delay)
	4723	+{
	4724	+ int timeout = 1000;
	4725	+ bool ret;
	4726	+ u16 lnk_status;
	4727	+
	4728	+ /*
	4729	+ * Some controllers might not implement link active reporting. In this
	4730	+ * case, we wait for 1000 ms + any delay requested by the caller.
	4731	+ */
	4732	+ if (!pdev->link_active_reporting) {
	4733	+ msleep(timeout + delay);
	4734	+ return true;
	4735	+ }
	4736	+
	4737	+ /*
	4738	+ * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
	4739	+ * after which we should expect an link active if the reset was
	4740	+ * successful. If so, software must wait a minimum 100ms before sending
	4741	+ * configuration requests to devices downstream this port.
	4742	+ *
	4743	+ * If the link fails to activate, either the device was physically
	4744	+ * removed or the link is permanently failed.
	4745	+ */
	4746	+ if (active)
	4747	+ msleep(20);
	4748	+ for (;;) {
	4749	+ pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
	4750	+ ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
	4751	+ if (ret == active)
	4752	+ break;
	4753	+ if (timeout <= 0)
	4754	+ break;
	4755	+ msleep(10);
	4756	+ timeout -= 10;
	4757	+ }
	4758	+ if (active && ret)
	4759	+ msleep(delay);
	4760	+
	4761	+ return ret == active;
	4762	+}
	4763	+
4534	4764	/**
4535	4765	* pcie_wait_for_link - Wait until link is active or inactive
4536	4766	* @pdev: Bridge device
..	..	@@ -4540,25 +4770,127 @@
4540	4770	*/
4541	4771	bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4542	4772	{
4543		- int timeout = 1000;
4544		- bool ret;
4545		- u16 lnk_status;
	4773	+ return pcie_wait_for_link_delay(pdev, active, 100);
	4774	+}
4546	4775
4547		- for (;;) {
4548		- pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4549		- ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4550		- if (ret == active)
4551		- return true;
4552		- if (timeout <= 0)
4553		- break;
4554		- msleep(10);
4555		- timeout -= 10;
	4776	+/*
	4777	+ * Find maximum D3cold delay required by all the devices on the bus. The
	4778	+ * spec says 100 ms, but firmware can lower it and we allow drivers to
	4779	+ * increase it as well.
	4780	+ *
	4781	+ * Called with @pci_bus_sem locked for reading.
	4782	+ */
	4783	+static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
	4784	+{
	4785	+ const struct pci_dev *pdev;
	4786	+ int min_delay = 100;
	4787	+ int max_delay = 0;
	4788	+
	4789	+ list_for_each_entry(pdev, &bus->devices, bus_list) {
	4790	+ if (pdev->d3cold_delay < min_delay)
	4791	+ min_delay = pdev->d3cold_delay;
	4792	+ if (pdev->d3cold_delay > max_delay)
	4793	+ max_delay = pdev->d3cold_delay;
4556	4794	}
4557	4795
4558		- pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
4559		- active ? "set" : "cleared");
	4796	+ return max(min_delay, max_delay);
	4797	+}
4560	4798
4561		- return false;
	4799	+/**
	4800	+ * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
	4801	+ * @dev: PCI bridge
	4802	+ *
	4803	+ * Handle necessary delays before access to the devices on the secondary
	4804	+ * side of the bridge are permitted after D3cold to D0 transition.
	4805	+ *
	4806	+ * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
	4807	+ * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
	4808	+ * 4.3.2.
	4809	+ */
	4810	+void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
	4811	+{
	4812	+ struct pci_dev *child;
	4813	+ int delay;
	4814	+
	4815	+ if (pci_dev_is_disconnected(dev))
	4816	+ return;
	4817	+
	4818	+ if (!pci_is_bridge(dev) \|\| !dev->bridge_d3)
	4819	+ return;
	4820	+
	4821	+ down_read(&pci_bus_sem);
	4822	+
	4823	+ /*
	4824	+ * We only deal with devices that are present currently on the bus.
	4825	+ * For any hot-added devices the access delay is handled in pciehp
	4826	+ * board_added(). In case of ACPI hotplug the firmware is expected
	4827	+ * to configure the devices before OS is notified.
	4828	+ */
	4829	+ if (!dev->subordinate \|\| list_empty(&dev->subordinate->devices)) {
	4830	+ up_read(&pci_bus_sem);
	4831	+ return;
	4832	+ }
	4833	+
	4834	+ /* Take d3cold_delay requirements into account */
	4835	+ delay = pci_bus_max_d3cold_delay(dev->subordinate);
	4836	+ if (!delay) {
	4837	+ up_read(&pci_bus_sem);
	4838	+ return;
	4839	+ }
	4840	+
	4841	+ child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
	4842	+ bus_list);
	4843	+ up_read(&pci_bus_sem);
	4844	+
	4845	+ /*
	4846	+ * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
	4847	+ * accessing the device after reset (that is 1000 ms + 100 ms). In
	4848	+ * practice this should not be needed because we don't do power
	4849	+ * management for them (see pci_bridge_d3_possible()).
	4850	+ */
	4851	+ if (!pci_is_pcie(dev)) {
	4852	+ pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
	4853	+ msleep(1000 + delay);
	4854	+ return;
	4855	+ }
	4856	+
	4857	+ /*
	4858	+ * For PCIe downstream and root ports that do not support speeds
	4859	+ * greater than 5 GT/s need to wait minimum 100 ms. For higher
	4860	+ * speeds (gen3) we need to wait first for the data link layer to
	4861	+ * become active.
	4862	+ *
	4863	+ * However, 100 ms is the minimum and the PCIe spec says the
	4864	+ * software must allow at least 1s before it can determine that the
	4865	+ * device that did not respond is a broken device. There is
	4866	+ * evidence that 100 ms is not always enough, for example certain
	4867	+ * Titan Ridge xHCI controller does not always respond to
	4868	+ * configuration requests if we only wait for 100 ms (see
	4869	+ * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
	4870	+ *
	4871	+ * Therefore we wait for 100 ms and check for the device presence.
	4872	+ * If it is still not present give it an additional 100 ms.
	4873	+ */
	4874	+ if (!pcie_downstream_port(dev))
	4875	+ return;
	4876	+
	4877	+ if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
	4878	+ pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
	4879	+ msleep(delay);
	4880	+ } else {
	4881	+ pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
	4882	+ delay);
	4883	+ if (!pcie_wait_for_link_delay(dev, true, delay)) {
	4884	+ /* Did not train, no need to wait any further */
	4885	+ pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
	4886	+ return;
	4887	+ }
	4888	+ }
	4889	+
	4890	+ if (!pci_device_is_present(child)) {
	4891	+ pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
	4892	+ msleep(delay);
	4893	+ }
4562	4894	}
4563	4895
4564	4896	void pci_reset_secondary_bus(struct pci_dev *dev)
..	..	@@ -4630,46 +4962,40 @@
4630	4962	{
4631	4963	int rc = -ENOTTY;
4632	4964
4633		- if (!hotplug \|\| !try_module_get(hotplug->ops->owner))
	4965	+ if (!hotplug \|\| !try_module_get(hotplug->owner))
4634	4966	return rc;
4635	4967
4636	4968	if (hotplug->ops->reset_slot)
4637	4969	rc = hotplug->ops->reset_slot(hotplug, probe);
4638	4970
4639		- module_put(hotplug->ops->owner);
	4971	+ module_put(hotplug->owner);
4640	4972
4641	4973	return rc;
4642	4974	}
4643	4975
4644	4976	static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4645	4977	{
4646		- struct pci_dev *pdev;
4647		-
4648		- if (dev->subordinate \|\| !dev->slot \|\|
	4978	+ if (dev->multifunction \|\| dev->subordinate \|\| !dev->slot \|\|
4649	4979	dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4650	4980	return -ENOTTY;
4651		-
4652		- list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4653		- if (pdev != dev && pdev->slot == dev->slot)
4654		- return -ENOTTY;
4655	4981
4656	4982	return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4657	4983	}
4658	4984
4659	4985	static void pci_dev_lock(struct pci_dev *dev)
4660	4986	{
4661		- pci_cfg_access_lock(dev);
4662	4987	/* block PM suspend, driver probe, etc. */
4663	4988	device_lock(&dev->dev);
	4989	+ pci_cfg_access_lock(dev);
4664	4990	}
4665	4991
4666	4992	/* Return 1 on successful lock, 0 on contention */
4667	4993	static int pci_dev_trylock(struct pci_dev *dev)
4668	4994	{
4669		- if (pci_cfg_access_trylock(dev)) {
4670		- if (device_trylock(&dev->dev))
	4995	+ if (device_trylock(&dev->dev)) {
	4996	+ if (pci_cfg_access_trylock(dev))
4671	4997	return 1;
4672		- pci_cfg_access_unlock(dev);
	4998	+ device_unlock(&dev->dev);
4673	4999	}
4674	5000
4675	5001	return 0;
..	..	@@ -4677,8 +5003,8 @@
4677	5003
4678	5004	static void pci_dev_unlock(struct pci_dev *dev)
4679	5005	{
4680		- device_unlock(&dev->dev);
4681	5006	pci_cfg_access_unlock(dev);
	5007	+ device_unlock(&dev->dev);
4682	5008	}
4683	5009
4684	5010	static void pci_dev_save_and_disable(struct pci_dev *dev)
..	..	@@ -4739,6 +5065,7 @@
4739	5065	*
4740	5066	* The device function is presumed to be unused and the caller is holding
4741	5067	* the device mutex lock when this function is called.
	5068	+ *
4742	5069	* Resetting the device will make the contents of PCI configuration space
4743	5070	* random, so any caller of this must be prepared to reinitialise the
4744	5071	* device including MSI, bus mastering, BARs, decoding IO and memory spaces,
..	..	@@ -5302,8 +5629,8 @@
5302	5629	* pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5303	5630	* @dev: PCI device to query
5304	5631	*
5305		- * Returns mmrbc: maximum designed memory read count in bytes
5306		- * or appropriate error value.
	5632	+ * Returns mmrbc: maximum designed memory read count in bytes or
	5633	+ * appropriate error value.
5307	5634	*/
5308	5635	int pcix_get_max_mmrbc(struct pci_dev *dev)
5309	5636	{
..	..	@@ -5325,8 +5652,8 @@
5325	5652	* pcix_get_mmrbc - get PCI-X maximum memory read byte count
5326	5653	* @dev: PCI device to query
5327	5654	*
5328		- * Returns mmrbc: maximum memory read count in bytes
5329		- * or appropriate error value.
	5655	+ * Returns mmrbc: maximum memory read count in bytes or appropriate error
	5656	+ * value.
5330	5657	*/
5331	5658	int pcix_get_mmrbc(struct pci_dev *dev)
5332	5659	{
..	..	@@ -5350,7 +5677,7 @@
5350	5677	* @mmrbc: maximum memory read count in bytes
5351	5678	* valid values are 512, 1024, 2048, 4096
5352	5679	*
5353		- * If possible sets maximum memory read byte count, some bridges have erratas
	5680	+ * If possible sets maximum memory read byte count, some bridges have errata
5354	5681	* that prevent this.
5355	5682	*/
5356	5683	int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
..	..	@@ -5395,8 +5722,7 @@
5395	5722	* pcie_get_readrq - get PCI Express read request size
5396	5723	* @dev: PCI device to query
5397	5724	*
5398		- * Returns maximum memory read request in bytes
5399		- * or appropriate error value.
	5725	+ * Returns maximum memory read request in bytes or appropriate error value.
5400	5726	*/
5401	5727	int pcie_get_readrq(struct pci_dev *dev)
5402	5728	{
..	..	@@ -5419,15 +5745,15 @@
5419	5745	int pcie_set_readrq(struct pci_dev *dev, int rq)
5420	5746	{
5421	5747	u16 v;
	5748	+ int ret;
5422	5749
5423	5750	if (rq < 128 \|\| rq > 4096 \|\| !is_power_of_2(rq))
5424	5751	return -EINVAL;
5425	5752
5426	5753	/*
5427		- * If using the "performance" PCIe config, we clamp the
5428		- * read rq size to the max packet size to prevent the
5429		- * host bridge generating requests larger than we can
5430		- * cope with
	5754	+ * If using the "performance" PCIe config, we clamp the read rq
	5755	+ * size to the max packet size to keep the host bridge from
	5756	+ * generating requests larger than we can cope with.
5431	5757	*/
5432	5758	if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5433	5759	int mps = pcie_get_mps(dev);
..	..	@@ -5438,8 +5764,10 @@
5438	5764
5439	5765	v = (ffs(rq) - 8) << 12;
5440	5766
5441		- return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
	5767	+ ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5442	5768	PCI_EXP_DEVCTL_READRQ, v);
	5769	+
	5770	+ return pcibios_err_to_errno(ret);
5443	5771	}
5444	5772	EXPORT_SYMBOL(pcie_set_readrq);
5445	5773
..	..	@@ -5470,6 +5798,7 @@
5470	5798	int pcie_set_mps(struct pci_dev *dev, int mps)
5471	5799	{
5472	5800	u16 v;
	5801	+ int ret;
5473	5802
5474	5803	if (mps < 128 \|\| mps > 4096 \|\| !is_power_of_2(mps))
5475	5804	return -EINVAL;
..	..	@@ -5479,8 +5808,10 @@
5479	5808	return -EINVAL;
5480	5809	v <<= 5;
5481	5810
5482		- return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
	5811	+ ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5483	5812	PCI_EXP_DEVCTL_PAYLOAD, v);
	5813	+
	5814	+ return pcibios_err_to_errno(ret);
5484	5815	}
5485	5816	EXPORT_SYMBOL(pcie_set_mps);
5486	5817
..	..	@@ -5563,17 +5894,10 @@
5563	5894	* where only 2.5 GT/s and 5.0 GT/s speeds were defined.
5564	5895	*/
5565	5896	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5566		- if (lnkcap2) { /* PCIe r3.0-compliant */
5567		- if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
5568		- return PCIE_SPEED_16_0GT;
5569		- else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
5570		- return PCIE_SPEED_8_0GT;
5571		- else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
5572		- return PCIE_SPEED_5_0GT;
5573		- else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
5574		- return PCIE_SPEED_2_5GT;
5575		- return PCI_SPEED_UNKNOWN;
5576		- }
	5897	+
	5898	+ /* PCIe r3.0-compliant */
	5899	+ if (lnkcap2)
	5900	+ return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
5577	5901
5578	5902	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5579	5903	if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
..	..	@@ -5649,14 +5973,14 @@
5649	5973	if (bw_avail >= bw_cap && verbose)
5650	5974	pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5651	5975	bw_cap / 1000, bw_cap % 1000,
5652		- PCIE_SPEED2STR(speed_cap), width_cap);
	5976	+ pci_speed_string(speed_cap), width_cap);
5653	5977	else if (bw_avail < bw_cap)
5654	5978	pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5655	5979	bw_avail / 1000, bw_avail % 1000,
5656		- PCIE_SPEED2STR(speed), width,
	5980	+ pci_speed_string(speed), width,
5657	5981	limiting_dev ? pci_name(limiting_dev) : "<unknown>",
5658	5982	bw_cap / 1000, bw_cap % 1000,
5659		- PCIE_SPEED2STR(speed_cap), width_cap);
	5983	+ pci_speed_string(speed_cap), width_cap);
5660	5984	}
5661	5985
5662	5986	/**
..	..	@@ -5730,7 +6054,7 @@
5730	6054
5731	6055	if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
5732	6056	pci_read_config_word(dev, PCI_COMMAND, &cmd);
5733		- if (decode == true)
	6057	+ if (decode)
5734	6058	cmd \|= command_bits;
5735	6059	else
5736	6060	cmd &= ~command_bits;
..	..	@@ -5746,7 +6070,7 @@
5746	6070	if (bridge) {
5747	6071	pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5748	6072	&cmd);
5749		- if (decode == true)
	6073	+ if (decode)
5750	6074	cmd \|= PCI_BRIDGE_CTL_VGA;
5751	6075	else
5752	6076	cmd &= ~PCI_BRIDGE_CTL_VGA;
..	..	@@ -5758,10 +6082,29 @@
5758	6082	return 0;
5759	6083	}
5760	6084
	6085	+#ifdef CONFIG_ACPI
	6086	+bool pci_pr3_present(struct pci_dev *pdev)
	6087	+{
	6088	+ struct acpi_device *adev;
	6089	+
	6090	+ if (acpi_disabled)
	6091	+ return false;
	6092	+
	6093	+ adev = ACPI_COMPANION(&pdev->dev);
	6094	+ if (!adev)
	6095	+ return false;
	6096	+
	6097	+ return adev->power.flags.power_resources &&
	6098	+ acpi_has_method(adev->handle, "_PR3");
	6099	+}
	6100	+EXPORT_SYMBOL_GPL(pci_pr3_present);
	6101	+#endif
	6102	+
5761	6103	/**
5762	6104	* pci_add_dma_alias - Add a DMA devfn alias for a device
5763	6105	* @dev: the PCI device for which alias is added
5764		- * @devfn: alias slot and function
	6106	+ * @devfn_from: alias slot and function
	6107	+ * @nr_devfns: number of subsequent devfns to alias
5765	6108	*
5766	6109	* This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
5767	6110	* which is used to program permissible bus-devfn source addresses for DMA
..	..	@@ -5777,19 +6120,29 @@
5777	6120	* cannot be left as a userspace activity). DMA aliases should therefore
5778	6121	* be configured via quirks, such as the PCI fixup header quirk.
5779	6122	*/
5780		-void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
	6123	+void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns)
5781	6124	{
	6125	+ int devfn_to;
	6126	+
	6127	+ nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from);
	6128	+ devfn_to = devfn_from + nr_devfns - 1;
	6129	+
5782	6130	if (!dev->dma_alias_mask)
5783		- dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5784		- sizeof(long), GFP_KERNEL);
	6131	+ dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
5785	6132	if (!dev->dma_alias_mask) {
5786	6133	pci_warn(dev, "Unable to allocate DMA alias mask\n");
5787	6134	return;
5788	6135	}
5789	6136
5790		- set_bit(devfn, dev->dma_alias_mask);
5791		- pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
5792		- PCI_SLOT(devfn), PCI_FUNC(devfn));
	6137	+ bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
	6138	+
	6139	+ if (nr_devfns == 1)
	6140	+ pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
	6141	+ PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
	6142	+ else if (nr_devfns > 1)
	6143	+ pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
	6144	+ PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
	6145	+ PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
5793	6146	}
5794	6147
5795	6148	bool pci_devs_are_dma_aliases(struct pci_dev dev1, struct pci_dev dev2)
..	..	@@ -5797,7 +6150,9 @@
5797	6150	return (dev1->dma_alias_mask &&
5798	6151	test_bit(dev2->devfn, dev1->dma_alias_mask)) \|\|
5799	6152	(dev2->dma_alias_mask &&
5800		- test_bit(dev1->devfn, dev2->dma_alias_mask));
	6153	+ test_bit(dev1->devfn, dev2->dma_alias_mask)) \|\|
	6154	+ pci_real_dma_dev(dev1) == dev2 \|\|
	6155	+ pci_real_dma_dev(dev2) == dev1;
5801	6156	}
5802	6157
5803	6158	bool pci_device_is_present(struct pci_dev *pdev)
..	..	@@ -5821,13 +6176,39 @@
5821	6176	}
5822	6177	EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5823	6178
	6179	+/**
	6180	+ * pci_real_dma_dev - Get PCI DMA device for PCI device
	6181	+ * @dev: the PCI device that may have a PCI DMA alias
	6182	+ *
	6183	+ * Permits the platform to provide architecture-specific functionality to
	6184	+ * devices needing to alias DMA to another PCI device on another PCI bus. If
	6185	+ * the PCI device is on the same bus, it is recommended to use
	6186	+ * pci_add_dma_alias(). This is the default implementation. Architecture
	6187	+ * implementations can override this.
	6188	+ */
	6189	+struct pci_dev __weak pci_real_dma_dev(struct pci_dev dev)
	6190	+{
	6191	+ return dev;
	6192	+}
	6193	+
5824	6194	resource_size_t __weak pcibios_default_alignment(void)
5825	6195	{
5826	6196	return 0;
5827	6197	}
5828	6198
5829		-#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5830		-static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
	6199	+/*
	6200	+ * Arches that don't want to expose struct resource to userland as-is in
	6201	+ * sysfs and /proc can implement their own pci_resource_to_user().
	6202	+ */
	6203	+void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
	6204	+ const struct resource *rsrc,
	6205	+ resource_size_t start, resource_size_t end)
	6206	+{
	6207	+ *start = rsrc->start;
	6208	+ *end = rsrc->end;
	6209	+}
	6210	+
	6211	+static char *resource_alignment_param;
5831	6212	static DEFINE_SPINLOCK(resource_alignment_lock);
5832	6213
5833	6214	/**
..	..	@@ -5848,7 +6229,7 @@
5848	6229
5849	6230	spin_lock(&resource_alignment_lock);
5850	6231	p = resource_alignment_param;
5851		- if (!*p && !align)
	6232	+ if (!p \|\| !*p)
5852	6233	goto out;
5853	6234	if (pci_has_flag(PCI_PROBE_ONLY)) {
5854	6235	align = 0;
..	..	@@ -6001,8 +6382,7 @@
6001	6382	* to enable the kernel to reassign new resource
6002	6383	* window later on.
6003	6384	*/
6004		- if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
6005		- (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
	6385	+ if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6006	6386	for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6007	6387	r = &dev->resource[i];
6008	6388	if (!(r->flags & IORESOURCE_MEM))
..	..	@@ -6015,39 +6395,44 @@
6015	6395	}
6016	6396	}
6017	6397
6018		-static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
	6398	+static ssize_t resource_alignment_show(struct bus_type bus, char buf)
6019	6399	{
6020		- if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
6021		- count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
	6400	+ size_t count = 0;
	6401	+
6022	6402	spin_lock(&resource_alignment_lock);
6023		- strncpy(resource_alignment_param, buf, count);
6024		- resource_alignment_param[count] = '\0';
	6403	+ if (resource_alignment_param)
	6404	+ count = scnprintf(buf, PAGE_SIZE, "%s", resource_alignment_param);
6025	6405	spin_unlock(&resource_alignment_lock);
	6406	+
	6407	+ /*
	6408	+ * When set by the command line, resource_alignment_param will not
	6409	+ * have a trailing line feed, which is ugly. So conditionally add
	6410	+ * it here.
	6411	+ */
	6412	+ if (count >= 2 && buf[count - 2] != '\n' && count < PAGE_SIZE - 1) {
	6413	+ buf[count - 1] = '\n';
	6414	+ buf[count++] = 0;
	6415	+ }
	6416	+
6026	6417	return count;
6027	6418	}
6028	6419
6029		-static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
6030		-{
6031		- size_t count;
6032		- spin_lock(&resource_alignment_lock);
6033		- count = snprintf(buf, size, "%s", resource_alignment_param);
6034		- spin_unlock(&resource_alignment_lock);
6035		- return count;
6036		-}
6037		-
6038		-static ssize_t pci_resource_alignment_show(struct bus_type bus, char buf)
6039		-{
6040		- return pci_get_resource_alignment_param(buf, PAGE_SIZE);
6041		-}
6042		-
6043		-static ssize_t pci_resource_alignment_store(struct bus_type *bus,
	6420	+static ssize_t resource_alignment_store(struct bus_type *bus,
6044	6421	const char *buf, size_t count)
6045	6422	{
6046		- return pci_set_resource_alignment_param(buf, count);
	6423	+ char *param = kstrndup(buf, count, GFP_KERNEL);
	6424	+
	6425	+ if (!param)
	6426	+ return -ENOMEM;
	6427	+
	6428	+ spin_lock(&resource_alignment_lock);
	6429	+ kfree(resource_alignment_param);
	6430	+ resource_alignment_param = param;
	6431	+ spin_unlock(&resource_alignment_lock);
	6432	+ return count;
6047	6433	}
6048	6434
6049		-static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
6050		- pci_resource_alignment_store);
	6435	+static BUS_ATTR_RW(resource_alignment);
6051	6436
6052	6437	static int __init pci_resource_alignment_sysfs_init(void)
6053	6438	{
..	..	@@ -6078,6 +6463,7 @@
6078	6463
6079	6464	if (parent)
6080	6465	domain = of_get_pci_domain_nr(parent->of_node);
	6466	+
6081	6467	/*
6082	6468	* Check DT domain and use_dt_domains values.
6083	6469	*
..	..	@@ -6172,14 +6558,18 @@
6172	6558	} else if (!strncmp(str, "cbmemsize=", 10)) {
6173	6559	pci_cardbus_mem_size = memparse(str + 10, &str);
6174	6560	} else if (!strncmp(str, "resource_alignment=", 19)) {
6175		- pci_set_resource_alignment_param(str + 19,
6176		- strlen(str + 19));
	6561	+ resource_alignment_param = str + 19;
6177	6562	} else if (!strncmp(str, "ecrc=", 5)) {
6178	6563	pcie_ecrc_get_policy(str + 5);
6179	6564	} else if (!strncmp(str, "hpiosize=", 9)) {
6180	6565	pci_hotplug_io_size = memparse(str + 9, &str);
	6566	+ } else if (!strncmp(str, "hpmmiosize=", 11)) {
	6567	+ pci_hotplug_mmio_size = memparse(str + 11, &str);
	6568	+ } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
	6569	+ pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6181	6570	} else if (!strncmp(str, "hpmemsize=", 10)) {
6182		- pci_hotplug_mem_size = memparse(str + 10, &str);
	6571	+ pci_hotplug_mmio_size = memparse(str + 10, &str);
	6572	+ pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6183	6573	} else if (!strncmp(str, "hpbussize=", 10)) {
6184	6574	pci_hotplug_bus_size =
6185	6575	simple_strtoul(str + 10, &str, 0);
..	..	@@ -6198,8 +6588,7 @@
6198	6588	} else if (!strncmp(str, "disable_acs_redir=", 18)) {
6199	6589	disable_acs_redir_param = str + 18;
6200	6590	} else {
6201		- printk(KERN_ERR "PCI: Unknown option `%s'\n",
6202		- str);
	6591	+ pr_err("PCI: Unknown option `%s'\n", str);
6203	6592	}
6204	6593	}
6205	6594	str = k;
..	..	@@ -6209,15 +6598,18 @@
6209	6598	early_param("pci", pci_setup);
6210	6599
6211	6600	/*
6212		- * 'disable_acs_redir_param' is initialized in pci_setup(), above, to point
6213		- * to data in the __initdata section which will be freed after the init
6214		- * sequence is complete. We can't allocate memory in pci_setup() because some
6215		- * architectures do not have any memory allocation service available during
6216		- * an early_param() call. So we allocate memory and copy the variable here
6217		- * before the init section is freed.
	6601	+ * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
	6602	+ * in pci_setup(), above, to point to data in the __initdata section which
	6603	+ * will be freed after the init sequence is complete. We can't allocate memory
	6604	+ * in pci_setup() because some architectures do not have any memory allocation
	6605	+ * service available during an early_param() call. So we allocate memory and
	6606	+ * copy the variable here before the init section is freed.
	6607	+ *
6218	6608	*/
6219	6609	static int __init pci_realloc_setup_params(void)
6220	6610	{
	6611	+ resource_alignment_param = kstrdup(resource_alignment_param,
	6612	+ GFP_KERNEL);
6221	6613	disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6222	6614
6223	6615	return 0;