forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/net/wireless/intel/iwlwifi/fw/api/rx.h
....@@ -5,10 +5,9 @@
55  *
66  * GPL LICENSE SUMMARY
77  *
8
- * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8
+ * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation. All rights reserved.
99  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
1010  * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
11
- * Copyright(c) 2018 Intel Corporation
1211  *
1312  * This program is free software; you can redistribute it and/or modify
1413  * it under the terms of version 2 of the GNU General Public License as
....@@ -28,10 +27,9 @@
2827  *
2928  * BSD LICENSE
3029  *
31
- * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
30
+ * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation. All rights reserved.
3231  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
3332  * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
34
- * Copyright(c) 2018 Intel Corporation
3533  * All rights reserved.
3634  *
3735  * Redistribution and use in source and binary forms, with or without
....@@ -209,8 +207,6 @@
209207  * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors
210208  * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask
211209  * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift
212
- * @RX_MPDU_RES_STATUS_FILTERING_MSK: filter status
213
- * @RX_MPDU_RES_STATUS2_FILTERING_MSK: filter status 2
214210  */
215211 enum iwl_mvm_rx_status {
216212 	RX_MPDU_RES_STATUS_CRC_OK			= BIT(0),
....@@ -238,8 +234,6 @@
238234 	RX_MPDU_RES_STATUS_CSUM_OK			= BIT(17),
239235 	RX_MDPU_RES_STATUS_STA_ID_SHIFT			= 24,
240236 	RX_MPDU_RES_STATUS_STA_ID_MSK			= 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT,
241
-	RX_MPDU_RES_STATUS_FILTERING_MSK		= (0xc00000),
242
-	RX_MPDU_RES_STATUS2_FILTERING_MSK		= (0xc0000000),
243237 };
244238 
245239 /* 9000 series API */
....@@ -263,6 +257,11 @@
263257 	IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK	= 0x7f,
264258 	IWL_RX_MPDU_AMSDU_LAST_SUBFRAME		= 0x80,
265259 };
260
+
261
+#define RX_MPDU_BAND_POS 6
262
+#define RX_MPDU_BAND_MASK 0xC0
263
+#define BAND_IN_RX_STATUS(_val) \
264
+	(((_val) & RX_MPDU_BAND_MASK) >> RX_MPDU_BAND_POS)
266265 
267266 enum iwl_rx_l3_proto_values {
268267 	IWL_RX_L3_TYPE_NONE,
....@@ -309,17 +308,11 @@
309308 	IWL_RX_MPDU_STATUS_EXT_IV_MATCH		= BIT(13),
310309 	IWL_RX_MPDU_STATUS_KEY_ID_MATCH		= BIT(14),
311310 	IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME	= BIT(15),
312
-};
313311 
314
-enum iwl_rx_mpdu_hash_filter {
315
-	IWL_RX_MPDU_HF_A1_HASH_MASK		= 0x3f,
316
-	IWL_RX_MPDU_HF_FILTER_STATUS_MASK	= 0xc0,
317
-};
312
+	IWL_RX_MPDU_STATUS_KEY			= 0x3f0000,
313
+	IWL_RX_MPDU_STATUS_DUPLICATE		= BIT(22),
318314 
319
-enum iwl_rx_mpdu_sta_id_flags {
320
-	IWL_RX_MPDU_SIF_STA_ID_MASK		= 0x1f,
321
-	IWL_RX_MPDU_SIF_RRF_ABORT		= 0x20,
322
-	IWL_RX_MPDU_SIF_FILTER_STATUS_MASK	= 0xc0,
315
+	IWL_RX_MPDU_STATUS_STA_ID		= 0x1f000000,
323316 };
324317 
325318 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f
....@@ -337,6 +330,8 @@
337330 	IWL_RX_MPDU_PHY_AMPDU		= BIT(5),
338331 	IWL_RX_MPDU_PHY_AMPDU_TOGGLE	= BIT(6),
339332 	IWL_RX_MPDU_PHY_SHORT_PREAMBLE	= BIT(7),
333
+	/* short preamble is only for CCK, for non-CCK overridden by this */
334
+	IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY	= BIT(7),
340335 	IWL_RX_MPDU_PHY_TSF_OVERLOAD	= BIT(8),
341336 };
342337 
....@@ -345,35 +340,98 @@
345340 	IWL_RX_MPDU_PHY_PHY_INDEX_MASK		= 0xf0,
346341 };
347342 
348
-/*
349
- * enum iwl_rx_he_phy - HE PHY data
350
- */
351
-enum iwl_rx_he_phy {
352
-	IWL_RX_HE_PHY_BEAM_CHNG			= BIT(0),
353
-	IWL_RX_HE_PHY_UPLINK			= BIT(1),
354
-	IWL_RX_HE_PHY_BSS_COLOR_MASK		= 0xfc,
355
-	IWL_RX_HE_PHY_SPATIAL_REUSE_MASK	= 0xf00,
356
-	IWL_RX_HE_PHY_SU_EXT_BW10		= BIT(12),
357
-	IWL_RX_HE_PHY_TXOP_DUR_MASK		= 0xfe000,
358
-	IWL_RX_HE_PHY_LDPC_EXT_SYM		= BIT(20),
359
-	IWL_RX_HE_PHY_PRE_FEC_PAD_MASK		= 0x600000,
360
-	IWL_RX_HE_PHY_PE_DISAMBIG		= BIT(23),
361
-	IWL_RX_HE_PHY_DOPPLER			= BIT(24),
362
-	/* 6 bits reserved */
363
-	IWL_RX_HE_PHY_DELIM_EOF			= BIT(31),
364
-
365
-	/* second dword - MU data */
366
-	IWL_RX_HE_PHY_SIGB_COMPRESSION		= BIT_ULL(32 + 0),
367
-	IWL_RX_HE_PHY_SIBG_SYM_OR_USER_NUM_MASK	= 0x1e00000000ULL,
368
-	IWL_RX_HE_PHY_HE_LTF_NUM_MASK		= 0xe000000000ULL,
369
-	IWL_RX_HE_PHY_RU_ALLOC_SEC80		= BIT_ULL(32 + 8),
370
-	/* trigger encoded */
371
-	IWL_RX_HE_PHY_RU_ALLOC_MASK		= 0xfe0000000000ULL,
372
-	IWL_RX_HE_PHY_SIGB_MCS_MASK		= 0xf000000000000ULL,
343
+/* TSF overload low dword */
344
+enum iwl_rx_phy_data0 {
345
+	/* info type: HE any */
346
+	IWL_RX_PHY_DATA0_HE_BEAM_CHNG				= 0x00000001,
347
+	IWL_RX_PHY_DATA0_HE_UPLINK				= 0x00000002,
348
+	IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK			= 0x000000fc,
349
+	IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK			= 0x00000f00,
373350 	/* 1 bit reserved */
374
-	IWL_RX_HE_PHY_SIGB_DCM			= BIT_ULL(32 + 21),
375
-	IWL_RX_HE_PHY_PREAMBLE_PUNC_TYPE_MASK	= 0xc0000000000000ULL,
376
-	/* 8 bits reserved */
351
+	IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK			= 0x000fe000,
352
+	IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM			= 0x00100000,
353
+	IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK			= 0x00600000,
354
+	IWL_RX_PHY_DATA0_HE_PE_DISAMBIG				= 0x00800000,
355
+	IWL_RX_PHY_DATA0_HE_DOPPLER				= 0x01000000,
356
+	/* 6 bits reserved */
357
+	IWL_RX_PHY_DATA0_HE_DELIM_EOF				= 0x80000000,
358
+};
359
+
360
+enum iwl_rx_phy_info_type {
361
+	IWL_RX_PHY_INFO_TYPE_NONE				= 0,
362
+	IWL_RX_PHY_INFO_TYPE_CCK				= 1,
363
+	IWL_RX_PHY_INFO_TYPE_OFDM_LGCY				= 2,
364
+	IWL_RX_PHY_INFO_TYPE_HT					= 3,
365
+	IWL_RX_PHY_INFO_TYPE_VHT_SU				= 4,
366
+	IWL_RX_PHY_INFO_TYPE_VHT_MU				= 5,
367
+	IWL_RX_PHY_INFO_TYPE_HE_SU				= 6,
368
+	IWL_RX_PHY_INFO_TYPE_HE_MU				= 7,
369
+	IWL_RX_PHY_INFO_TYPE_HE_TB				= 8,
370
+	IWL_RX_PHY_INFO_TYPE_HE_MU_EXT				= 9,
371
+	IWL_RX_PHY_INFO_TYPE_HE_TB_EXT				= 10,
372
+};
373
+
374
+/* TSF overload high dword */
375
+enum iwl_rx_phy_data1 {
376
+	/*
377
+	 * check this first - if TSF overload is set,
378
+	 * see &enum iwl_rx_phy_info_type
379
+	 */
380
+	IWL_RX_PHY_DATA1_INFO_TYPE_MASK				= 0xf0000000,
381
+
382
+	/* info type: HT/VHT/HE any */
383
+	IWL_RX_PHY_DATA1_LSIG_LEN_MASK				= 0x0fff0000,
384
+
385
+	/* info type: HE MU/MU-EXT */
386
+	IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION			= 0x00000001,
387
+	IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK	= 0x0000001e,
388
+
389
+	/* info type: HE any */
390
+	IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK			= 0x000000e0,
391
+	IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80			= 0x00000100,
392
+	/* trigger encoded */
393
+	IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK			= 0x0000fe00,
394
+
395
+	/* info type: HE TB/TX-EXT */
396
+	IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE			= 0x00000001,
397
+	IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK			= 0x0000000e,
398
+};
399
+
400
+/* goes into Metadata DW 7 */
401
+enum iwl_rx_phy_data2 {
402
+	/* info type: HE MU-EXT */
403
+	/* the a1/a2/... is what the PHY/firmware calls the values */
404
+	IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0		= 0x000000ff, /* a1 */
405
+	IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2		= 0x0000ff00, /* a2 */
406
+	IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0		= 0x00ff0000, /* b1 */
407
+	IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2		= 0xff000000, /* b2 */
408
+
409
+	/* info type: HE TB-EXT */
410
+	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1		= 0x0000000f,
411
+	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2		= 0x000000f0,
412
+	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3		= 0x00000f00,
413
+	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4		= 0x0000f000,
414
+};
415
+
416
+/* goes into Metadata DW 8 */
417
+enum iwl_rx_phy_data3 {
418
+	/* info type: HE MU-EXT */
419
+	IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1		= 0x000000ff, /* c1 */
420
+	IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3		= 0x0000ff00, /* c2 */
421
+	IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1		= 0x00ff0000, /* d1 */
422
+	IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3		= 0xff000000, /* d2 */
423
+};
424
+
425
+/* goes into Metadata DW 4 high 16 bits */
426
+enum iwl_rx_phy_data4 {
427
+	/* info type: HE MU-EXT */
428
+	IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU			= 0x0001,
429
+	IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU			= 0x0002,
430
+	IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK			= 0x0004,
431
+	IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK			= 0x0008,
432
+	IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK		= 0x00f0,
433
+	IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM			= 0x0100,
434
+	IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK	= 0x0600,
377435 };
378436 
379437 /**
....@@ -381,15 +439,31 @@
381439  */
382440 struct iwl_rx_mpdu_desc_v1 {
383441 	/* DW7 - carries rss_hash only when rpa_en == 1 */
384
-	/**
385
-	 * @rss_hash: RSS hash value
386
-	 */
387
-	__le32 rss_hash;
442
+	union {
443
+		/**
444
+		 * @rss_hash: RSS hash value
445
+		 */
446
+		__le32 rss_hash;
447
+
448
+		/**
449
+		 * @phy_data2: depends on info type (see @phy_data1)
450
+		 */
451
+		__le32 phy_data2;
452
+	};
453
+
388454 	/* DW8 - carries filter_match only when rpa_en == 1 */
389
-	/**
390
-	 * @filter_match: filter match value
391
-	 */
392
-	__le32 filter_match;
455
+	union {
456
+		/**
457
+		 * @filter_match: filter match value
458
+		 */
459
+		__le32 filter_match;
460
+
461
+		/**
462
+		 * @phy_data3: depends on info type (see @phy_data1)
463
+		 */
464
+		__le32 phy_data3;
465
+	};
466
+
393467 	/* DW9 */
394468 	/**
395469 	 * @rate_n_flags: RX rate/flags encoding
....@@ -425,12 +499,19 @@
425499 		 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set
426500 		 */
427501 		__le64 tsf_on_air_rise;
428
-		/**
429
-		 * @he_phy_data:
430
-		 * HE PHY data, see &enum iwl_rx_he_phy, valid
431
-		 * only if %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set
432
-		 */
433
-		__le64 he_phy_data;
502
+
503
+		struct {
504
+			/**
505
+			 * @phy_data0: depends on info_type, see @phy_data1
506
+			 */
507
+			__le32 phy_data0;
508
+			/**
509
+			 * @phy_data1: valid only if
510
+			 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set,
511
+			 * see &enum iwl_rx_phy_data1.
512
+			 */
513
+			__le32 phy_data1;
514
+		};
434515 	};
435516 } __packed;
436517 
....@@ -439,15 +520,30 @@
439520  */
440521 struct iwl_rx_mpdu_desc_v3 {
441522 	/* DW7 - carries filter_match only when rpa_en == 1 */
442
-	/**
443
-	 * @filter_match: filter match value
444
-	 */
445
-	__le32 filter_match;
523
+	union {
524
+		/**
525
+		 * @filter_match: filter match value
526
+		 */
527
+		__le32 filter_match;
528
+
529
+		/**
530
+		 * @phy_data3: depends on info type (see @phy_data1)
531
+		 */
532
+		__le32 phy_data3;
533
+	};
534
+
446535 	/* DW8 - carries rss_hash only when rpa_en == 1 */
447
-	/**
448
-	 * @rss_hash: RSS hash value
449
-	 */
450
-	__le32 rss_hash;
536
+	union {
537
+		/**
538
+		 * @rss_hash: RSS hash value
539
+		 */
540
+		__le32 rss_hash;
541
+
542
+		/**
543
+		 * @phy_data2: depends on info type (see @phy_data1)
544
+		 */
545
+		__le32 phy_data2;
546
+	};
451547 	/* DW9 */
452548 	/**
453549 	 * @partial_hash: 31:0 ip/tcp header hash
....@@ -458,7 +554,11 @@
458554 	/**
459555 	 * @raw_xsum: raw xsum value
460556 	 */
461
-	__le32 raw_xsum;
557
+	__be16 raw_xsum;
558
+	/**
559
+	 * @reserved_xsum: reserved high bits in the raw checksum
560
+	 */
561
+	__le16 reserved_xsum;
462562 	/* DW11 */
463563 	/**
464564 	 * @rate_n_flags: RX rate/flags encoding
....@@ -494,12 +594,19 @@
494594 		 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set
495595 		 */
496596 		__le64 tsf_on_air_rise;
497
-		/**
498
-		 * @he_phy_data:
499
-		 * HE PHY data, see &enum iwl_rx_he_phy, valid
500
-		 * only if %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set
501
-		 */
502
-		__le64 he_phy_data;
597
+
598
+		struct {
599
+			/**
600
+			 * @phy_data0: depends on info_type, see @phy_data1
601
+			 */
602
+			__le32 phy_data0;
603
+			/**
604
+			 * @phy_data1: valid only if
605
+			 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set,
606
+			 * see &enum iwl_rx_phy_data1.
607
+			 */
608
+			__le32 phy_data1;
609
+		};
503610 	};
504611 	/* DW16 & DW17 */
505612 	/**
....@@ -543,23 +650,24 @@
543650 	 * @raw_csum: raw checksum (alledgedly unreliable)
544651 	 */
545652 	__le16 raw_csum;
546
-	/**
547
-	 * @l3l4_flags: &enum iwl_rx_l3l4_flags
548
-	 */
549
-	__le16 l3l4_flags;
653
+
654
+	union {
655
+		/**
656
+		 * @l3l4_flags: &enum iwl_rx_l3l4_flags
657
+		 */
658
+		__le16 l3l4_flags;
659
+
660
+		/**
661
+		 * @phy_data4: depends on info type, see phy_data1
662
+		 */
663
+		__le16 phy_data4;
664
+	};
550665 	/* DW5 */
551666 	/**
552667 	 * @status: &enum iwl_rx_mpdu_status
553668 	 */
554
-	__le16 status;
555
-	/**
556
-	 * @hash_filter: hash filter value
557
-	 */
558
-	u8 hash_filter;
559
-	/**
560
-	 * @sta_id_flags: &enum iwl_rx_mpdu_sta_id_flags
561
-	 */
562
-	u8 sta_id_flags;
669
+	__le32 status;
670
+
563671 	/* DW6 */
564672 	/**
565673 	 * @reorder_data: &enum iwl_rx_mpdu_reorder_data
....@@ -574,74 +682,95 @@
574682 
575683 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1)
576684 
577
-#define IWL_CD_STTS_OPTIMIZED_POS	0
578
-#define IWL_CD_STTS_OPTIMIZED_MSK	0x01
579
-#define IWL_CD_STTS_TRANSFER_STATUS_POS	1
580
-#define IWL_CD_STTS_TRANSFER_STATUS_MSK	0x0E
581
-#define IWL_CD_STTS_WIFI_STATUS_POS	4
582
-#define IWL_CD_STTS_WIFI_STATUS_MSK	0xF0
685
+#define RX_NO_DATA_CHAIN_A_POS		0
686
+#define RX_NO_DATA_CHAIN_A_MSK		(0xff << RX_NO_DATA_CHAIN_A_POS)
687
+#define RX_NO_DATA_CHAIN_B_POS		8
688
+#define RX_NO_DATA_CHAIN_B_MSK		(0xff << RX_NO_DATA_CHAIN_B_POS)
689
+#define RX_NO_DATA_CHANNEL_POS		16
690
+#define RX_NO_DATA_CHANNEL_MSK		(0xff << RX_NO_DATA_CHANNEL_POS)
691
+
692
+#define RX_NO_DATA_INFO_TYPE_POS	0
693
+#define RX_NO_DATA_INFO_TYPE_MSK	(0xff << RX_NO_DATA_INFO_TYPE_POS)
694
+#define RX_NO_DATA_INFO_TYPE_NONE	0
695
+#define RX_NO_DATA_INFO_TYPE_RX_ERR	1
696
+#define RX_NO_DATA_INFO_TYPE_NDP	2
697
+#define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED	3
698
+#define RX_NO_DATA_INFO_TYPE_HE_TB_UNMATCHED	4
699
+
700
+#define RX_NO_DATA_INFO_ERR_POS		8
701
+#define RX_NO_DATA_INFO_ERR_MSK		(0xff << RX_NO_DATA_INFO_ERR_POS)
702
+#define RX_NO_DATA_INFO_ERR_NONE	0
703
+#define RX_NO_DATA_INFO_ERR_BAD_PLCP	1
704
+#define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE	2
705
+#define RX_NO_DATA_INFO_ERR_NO_DELIM		3
706
+#define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR	4
707
+
708
+#define RX_NO_DATA_FRAME_TIME_POS	0
709
+#define RX_NO_DATA_FRAME_TIME_MSK	(0xfffff << RX_NO_DATA_FRAME_TIME_POS)
710
+
711
+#define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK	0x03800000
712
+#define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK	0x38000000
583713 
584714 /**
585
- * enum iwl_completion_desc_transfer_status -  transfer status (bits 1-3)
586
- * @IWL_CD_STTS_UNUSED: unused
587
- * @IWL_CD_STTS_UNUSED_2: unused
588
- * @IWL_CD_STTS_END_TRANSFER: successful transfer complete.
589
- *	In sniffer mode, when split is used, set in last CD completion. (RX)
590
- * @IWL_CD_STTS_OVERFLOW: In sniffer mode, when using split - used for
591
- *	all CD completion. (RX)
592
- * @IWL_CD_STTS_ABORTED: CR abort / close flow. (RX)
593
- * @IWL_CD_STTS_ERROR: general error (RX)
715
+ * struct iwl_rx_no_data - RX no data descriptor
716
+ * @info: 7:0 frame type, 15:8 RX error type
717
+ * @rssi: 7:0 energy chain-A,
718
+ *	15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel
719
+ * @on_air_rise_time: GP2 during on air rise
720
+ * @fr_time: frame time
721
+ * @rate: rate/mcs of frame
722
+ * @phy_info: &enum iwl_rx_phy_data0 and &enum iwl_rx_phy_info_type
723
+ * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type.
724
+ *	for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT
725
+ *	for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT
594726  */
595
-enum iwl_completion_desc_transfer_status {
596
-	IWL_CD_STTS_UNUSED,
597
-	IWL_CD_STTS_UNUSED_2,
598
-	IWL_CD_STTS_END_TRANSFER,
599
-	IWL_CD_STTS_OVERFLOW,
600
-	IWL_CD_STTS_ABORTED,
601
-	IWL_CD_STTS_ERROR,
602
-};
603
-
604
-/**
605
- * enum iwl_completion_desc_wifi_status - wifi status (bits 4-7)
606
- * @IWL_CD_STTS_VALID: the packet is valid (RX)
607
- * @IWL_CD_STTS_FCS_ERR: frame check sequence error (RX)
608
- * @IWL_CD_STTS_SEC_KEY_ERR: error handling the security key of rx (RX)
609
- * @IWL_CD_STTS_DECRYPTION_ERR: error decrypting the frame (RX)
610
- * @IWL_CD_STTS_DUP: duplicate packet (RX)
611
- * @IWL_CD_STTS_ICV_MIC_ERR: MIC error (RX)
612
- * @IWL_CD_STTS_INTERNAL_SNAP_ERR: problems removing the snap (RX)
613
- * @IWL_CD_STTS_SEC_PORT_FAIL: security port fail (RX)
614
- * @IWL_CD_STTS_BA_OLD_SN: block ack received old SN (RX)
615
- * @IWL_CD_STTS_QOS_NULL: QoS null packet (RX)
616
- * @IWL_CD_STTS_MAC_HDR_ERR: MAC header conversion error (RX)
617
- * @IWL_CD_STTS_MAX_RETRANS: reached max number of retransmissions (TX)
618
- * @IWL_CD_STTS_EX_LIFETIME: exceeded lifetime (TX)
619
- * @IWL_CD_STTS_NOT_USED: completed but not used (RX)
620
- * @IWL_CD_STTS_REPLAY_ERR: pn check failed, replay error (RX)
621
- */
622
-enum iwl_completion_desc_wifi_status {
623
-	IWL_CD_STTS_VALID,
624
-	IWL_CD_STTS_FCS_ERR,
625
-	IWL_CD_STTS_SEC_KEY_ERR,
626
-	IWL_CD_STTS_DECRYPTION_ERR,
627
-	IWL_CD_STTS_DUP,
628
-	IWL_CD_STTS_ICV_MIC_ERR,
629
-	IWL_CD_STTS_INTERNAL_SNAP_ERR,
630
-	IWL_CD_STTS_SEC_PORT_FAIL,
631
-	IWL_CD_STTS_BA_OLD_SN,
632
-	IWL_CD_STTS_QOS_NULL,
633
-	IWL_CD_STTS_MAC_HDR_ERR,
634
-	IWL_CD_STTS_MAX_RETRANS,
635
-	IWL_CD_STTS_EX_LIFETIME,
636
-	IWL_CD_STTS_NOT_USED,
637
-	IWL_CD_STTS_REPLAY_ERR,
638
-};
727
+struct iwl_rx_no_data {
728
+	__le32 info;
729
+	__le32 rssi;
730
+	__le32 on_air_rise_time;
731
+	__le32 fr_time;
732
+	__le32 rate;
733
+	__le32 phy_info[2];
734
+	__le32 rx_vec[2];
735
+} __packed; /* RX_NO_DATA_NTFY_API_S_VER_1 */
639736 
640737 struct iwl_frame_release {
641738 	u8 baid;
642739 	u8 reserved;
643740 	__le16 nssn;
644741 };
742
+
743
+/**
744
+ * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release
745
+ * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask
746
+ * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask
747
+ */
748
+enum iwl_bar_frame_release_sta_tid {
749
+	IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f,
750
+	IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0,
751
+};
752
+
753
+/**
754
+ * enum iwl_bar_frame_release_ba_info - BA information for BAR release
755
+ * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask
756
+ * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver)
757
+ * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask
758
+ */
759
+enum iwl_bar_frame_release_ba_info {
760
+	IWL_BAR_FRAME_RELEASE_NSSN_MASK	= 0x00000fff,
761
+	IWL_BAR_FRAME_RELEASE_SN_MASK	= 0x00fff000,
762
+	IWL_BAR_FRAME_RELEASE_BAID_MASK	= 0x3f000000,
763
+};
764
+
765
+/**
766
+ * struct iwl_bar_frame_release - frame release from BAR info
767
+ * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid.
768
+ * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info.
769
+ */
770
+struct iwl_bar_frame_release {
771
+	__le32 sta_tid;
772
+	__le32 ba_info;
773
+} __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */
645774 
646775 enum iwl_rss_hash_func_en {
647776 	IWL_RSS_HASH_TYPE_IPV4_TCP,
....@@ -673,7 +802,6 @@
673802 	u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE];
674803 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */
675804 
676
-#define IWL_MULTI_QUEUE_SYNC_MSG_MAX_SIZE 128
677805 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0
678806 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf
679807 
....@@ -709,10 +837,12 @@
709837  *
710838  * @IWL_MVM_RXQ_EMPTY: empty sync notification
711839  * @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA
840
+ * @IWL_MVM_RXQ_NSSN_SYNC: notify all the RSS queues with the new NSSN
712841  */
713842 enum iwl_mvm_rxq_notif_type {
714843 	IWL_MVM_RXQ_EMPTY,
715844 	IWL_MVM_RXQ_NOTIF_DEL_BA,
845
+	IWL_MVM_RXQ_NSSN_SYNC,
716846 };
717847 
718848 /**