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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
....@@ -1,17 +1,6 @@
1
+// SPDX-License-Identifier: ISC
12 /*
23  * Copyright (c) 2014 Broadcom Corporation
3
- *
4
- * Permission to use, copy, modify, and/or distribute this software for any
5
- * purpose with or without fee is hereby granted, provided that the above
6
- * copyright notice and this permission notice appear in all copies.
7
- *
8
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
154  */
165 #include <linux/kernel.h>
176 #include <linux/delay.h>
....@@ -165,6 +154,7 @@
165154 #define SRCI_LSS_MASK		0x00f00000
166155 #define SRCI_LSS_SHIFT		20
167156 #define	SRCI_SRNB_MASK		0xf0
157
+#define	SRCI_SRNB_MASK_EXT	0x100
168158 #define	SRCI_SRNB_SHIFT		4
169159 #define	SRCI_SRBSZ_MASK		0xf
170160 #define	SRCI_SRBSZ_SHIFT	0
....@@ -443,11 +433,25 @@
443433 {
444434 	struct brcmf_chip_priv *ci;
445435 	int count;
436
+	struct brcmf_core *d11core2 = NULL;
437
+	struct brcmf_core_priv *d11priv2 = NULL;
446438 
447439 	ci = core->chip;
448440 
441
+	/* special handle two D11 cores reset */
442
+	if (core->pub.id == BCMA_CORE_80211) {
443
+		d11core2 = brcmf_chip_get_d11core(&ci->pub, 1);
444
+		if (d11core2) {
445
+			brcmf_dbg(INFO, "found two d11 cores, reset both\n");
446
+			d11priv2 = container_of(d11core2,
447
+						struct brcmf_core_priv, pub);
448
+		}
449
+	}
450
+
449451 	/* must disable first to work for arbitrary current core state */
450452 	brcmf_chip_ai_coredisable(core, prereset, reset);
453
+	if (d11priv2)
454
+		brcmf_chip_ai_coredisable(d11priv2, prereset, reset);
451455 
452456 	count = 0;
453457 	while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
....@@ -459,9 +463,30 @@
459463 		usleep_range(40, 60);
460464 	}
461465 
466
+	if (d11priv2) {
467
+		count = 0;
468
+		while (ci->ops->read32(ci->ctx,
469
+				       d11priv2->wrapbase + BCMA_RESET_CTL) &
470
+				       BCMA_RESET_CTL_RESET) {
471
+			ci->ops->write32(ci->ctx,
472
+					 d11priv2->wrapbase + BCMA_RESET_CTL,
473
+					 0);
474
+			count++;
475
+			if (count > 50)
476
+				break;
477
+			usleep_range(40, 60);
478
+		}
479
+	}
480
+
462481 	ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
463482 			 postreset | BCMA_IOCTL_CLK);
464483 	ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
484
+
485
+	if (d11priv2) {
486
+		ci->ops->write32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL,
487
+				 postreset | BCMA_IOCTL_CLK);
488
+		ci->ops->read32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL);
489
+	}
465490 }
466491 
467492 char *brcmf_chip_name(u32 id, u32 rev, char *buf, uint len)
....@@ -592,7 +617,13 @@
592617 		if (lss != 0)
593618 			*ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
594619 	} else {
595
-		nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
620
+		/* length of SRAM Banks increased for corerev greater than 23 */
621
+		if (sr->pub.rev >= 23) {
622
+			nb = (coreinfo & (SRCI_SRNB_MASK | SRCI_SRNB_MASK_EXT))
623
+				>> SRCI_SRNB_SHIFT;
624
+		} else {
625
+			nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
626
+		}
596627 		for (i = 0; i < nb; i++) {
597628 			retent = brcmf_chip_socram_banksize(sr, i, &banksize);
598629 			*ramsize += banksize;
....@@ -681,7 +712,6 @@
681712 	case BRCM_CC_43569_CHIP_ID:
682713 	case BRCM_CC_43570_CHIP_ID:
683714 	case BRCM_CC_4358_CHIP_ID:
684
-	case BRCM_CC_4359_CHIP_ID:
685715 	case BRCM_CC_43602_CHIP_ID:
686716 	case BRCM_CC_4371_CHIP_ID:
687717 		return 0x180000;
....@@ -691,6 +721,9 @@
691721 	case BRCM_CC_4366_CHIP_ID:
692722 	case BRCM_CC_43664_CHIP_ID:
693723 		return 0x200000;
724
+	case BRCM_CC_4359_CHIP_ID:
725
+		return (ci->pub.chiprev < 9) ? 0x180000 : 0x160000;
726
+	case BRCM_CC_4364_CHIP_ID:
694727 	case CY_CC_4373_CHIP_ID:
695728 		return 0x160000;
696729 	default:
....@@ -700,8 +733,10 @@
700733 	return 0;
701734 }
702735 
703
-static int brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
736
+int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
704737 {
738
+	struct brcmf_chip_priv *ci = container_of(pub, struct brcmf_chip_priv,
739
+						  pub);
705740 	struct brcmf_core_priv *mem_core;
706741 	struct brcmf_core *mem;
707742 
....@@ -779,8 +814,7 @@
779814 				      u32 *regbase, u32 *wrapbase)
780815 {
781816 	u8 desc;
782
-	u32 val;
783
-	u8 mpnum = 0;
817
+	u32 val, szdesc;
784818 	u8 stype, sztype, wraptype;
785819 
786820 	*regbase = 0;
....@@ -788,7 +822,6 @@
788822 
789823 	val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
790824 	if (desc == DMP_DESC_MASTER_PORT) {
791
-		mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S;
792825 		wraptype = DMP_SLAVE_TYPE_MWRAP;
793826 	} else if (desc == DMP_DESC_ADDRESS) {
794827 		/* revert erom address */
....@@ -825,14 +858,15 @@
825858 
826859 		/* next size descriptor can be skipped */
827860 		if (sztype == DMP_SLAVE_SIZE_DESC) {
828
-			val = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
861
+			szdesc = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
829862 			/* skip upper size descriptor if present */
830
-			if (val & DMP_DESC_ADDRSIZE_GT32)
863
+			if (szdesc & DMP_DESC_ADDRSIZE_GT32)
831864 				brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
832865 		}
833866 
834
-		/* only look for 4K register regions */
835
-		if (sztype != DMP_SLAVE_SIZE_4K)
867
+		/* look for 4K or 8K register regions */
868
+		if (sztype != DMP_SLAVE_SIZE_4K &&
869
+		    sztype != DMP_SLAVE_SIZE_8K)
836870 			continue;
837871 
838872 		stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
....@@ -855,7 +889,7 @@
855889 	u8 desc_type = 0;
856890 	u32 val;
857891 	u16 id;
858
-	u8 nmp, nsp, nmw, nsw, rev;
892
+	u8 nmw, nsw, rev;
859893 	u32 base, wrap;
860894 	int err;
861895 
....@@ -881,15 +915,14 @@
881915 			return -EFAULT;
882916 
883917 		/* only look at cores with master port(s) */
884
-		nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S;
885
-		nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S;
886918 		nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
887919 		nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
888920 		rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
889921 
890922 		/* need core with ports */
891923 		if (nmw + nsw == 0 &&
892
-		    id != BCMA_CORE_PMU)
924
+		    id != BCMA_CORE_PMU &&
925
+		    id != BCMA_CORE_GCI)
893926 			continue;
894927 
895928 		/* try to obtain register address info */
....@@ -981,7 +1014,7 @@
9811014 		brcmf_chip_set_passive(&ci->pub);
9821015 	}
9831016 
984
-	return brcmf_chip_get_raminfo(ci);
1017
+	return brcmf_chip_get_raminfo(&ci->pub);
9851018 }
9861019 
9871020 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
....@@ -1111,6 +1144,21 @@
11111144 		kfree(core);
11121145 	}
11131146 	kfree(chip);
1147
+}
1148
+
1149
+struct brcmf_core *brcmf_chip_get_d11core(struct brcmf_chip *pub, u8 unit)
1150
+{
1151
+	struct brcmf_chip_priv *chip;
1152
+	struct brcmf_core_priv *core;
1153
+
1154
+	chip = container_of(pub, struct brcmf_chip_priv, pub);
1155
+	list_for_each_entry(core, &chip->cores, list) {
1156
+		if (core->pub.id == BCMA_CORE_80211) {
1157
+			if (unit-- == 0)
1158
+				return &core->pub;
1159
+		}
1160
+	}
1161
+	return NULL;
11141162 }
11151163 
11161164 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
....@@ -1342,7 +1390,7 @@
13421390 	case BRCM_CC_4345_CHIP_ID:
13431391 		/* explicitly check SR engine enable bit */
13441392 		pmu_cc3_mask = BIT(2);
1345
-		/* fall-through */
1393
+		fallthrough;
13461394 	case BRCM_CC_43241_CHIP_ID:
13471395 	case BRCM_CC_4335_CHIP_ID:
13481396 	case BRCM_CC_4339_CHIP_ID:
....@@ -1356,6 +1404,17 @@
13561404 		addr = CORE_CC_REG(base, sr_control1);
13571405 		reg = chip->ops->read32(chip->ctx, addr);
13581406 		return reg != 0;
1407
+	case CY_CC_4373_CHIP_ID:
1408
+		/* explicitly check SR engine enable bit */
1409
+		addr = CORE_CC_REG(base, sr_control0);
1410
+		reg = chip->ops->read32(chip->ctx, addr);
1411
+		return (reg & CC_SR_CTL0_ENABLE_MASK) != 0;
1412
+	case BRCM_CC_4359_CHIP_ID:
1413
+	case CY_CC_43012_CHIP_ID:
1414
+		addr = CORE_CC_REG(pmu->base, retention_ctl);
1415
+		reg = chip->ops->read32(chip->ctx, addr);
1416
+		return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1417
+			       PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
13591418 	default:
13601419 		addr = CORE_CC_REG(pmu->base, pmucapabilities_ext);
13611420 		reg = chip->ops->read32(chip->ctx, addr);