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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
....@@ -1,25 +1,16 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*******************************************************************************
23   DWMAC Management Counters
34 
45   Copyright (C) 2011  STMicroelectronics Ltd
56 
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  The full GNU General Public License is included in this distribution in
16
-  the file called "COPYING".
177 
188   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
199 *******************************************************************************/
2010 
2111 #include <linux/kernel.h>
2212 #include <linux/io.h>
13
+#include "hwif.h"
2314 #include "mmc.h"
2415 
2516 /* MAC Management Counters register offset */
....@@ -128,7 +119,73 @@
128119 #define MMC_RX_ICMP_GD_OCTETS		0x180
129120 #define MMC_RX_ICMP_ERR_OCTETS		0x184
130121 
131
-void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
122
+#define MMC_TX_FPE_FRAG			0x1a8
123
+#define MMC_TX_HOLD_REQ			0x1ac
124
+#define MMC_RX_PKT_ASSEMBLY_ERR		0x1c8
125
+#define MMC_RX_PKT_SMD_ERR		0x1cc
126
+#define MMC_RX_PKT_ASSEMBLY_OK		0x1d0
127
+#define MMC_RX_FPE_FRAG			0x1d4
128
+
129
+/* XGMAC MMC Registers */
130
+#define MMC_XGMAC_TX_OCTET_GB		0x14
131
+#define MMC_XGMAC_TX_PKT_GB		0x1c
132
+#define MMC_XGMAC_TX_BROAD_PKT_G	0x24
133
+#define MMC_XGMAC_TX_MULTI_PKT_G	0x2c
134
+#define MMC_XGMAC_TX_64OCT_GB		0x34
135
+#define MMC_XGMAC_TX_65OCT_GB		0x3c
136
+#define MMC_XGMAC_TX_128OCT_GB		0x44
137
+#define MMC_XGMAC_TX_256OCT_GB		0x4c
138
+#define MMC_XGMAC_TX_512OCT_GB		0x54
139
+#define MMC_XGMAC_TX_1024OCT_GB		0x5c
140
+#define MMC_XGMAC_TX_UNI_PKT_GB		0x64
141
+#define MMC_XGMAC_TX_MULTI_PKT_GB	0x6c
142
+#define MMC_XGMAC_TX_BROAD_PKT_GB	0x74
143
+#define MMC_XGMAC_TX_UNDER		0x7c
144
+#define MMC_XGMAC_TX_OCTET_G		0x84
145
+#define MMC_XGMAC_TX_PKT_G		0x8c
146
+#define MMC_XGMAC_TX_PAUSE		0x94
147
+#define MMC_XGMAC_TX_VLAN_PKT_G		0x9c
148
+#define MMC_XGMAC_TX_LPI_USEC		0xa4
149
+#define MMC_XGMAC_TX_LPI_TRAN		0xa8
150
+
151
+#define MMC_XGMAC_RX_PKT_GB		0x100
152
+#define MMC_XGMAC_RX_OCTET_GB		0x108
153
+#define MMC_XGMAC_RX_OCTET_G		0x110
154
+#define MMC_XGMAC_RX_BROAD_PKT_G	0x118
155
+#define MMC_XGMAC_RX_MULTI_PKT_G	0x120
156
+#define MMC_XGMAC_RX_CRC_ERR		0x128
157
+#define MMC_XGMAC_RX_RUNT_ERR		0x130
158
+#define MMC_XGMAC_RX_JABBER_ERR		0x134
159
+#define MMC_XGMAC_RX_UNDER		0x138
160
+#define MMC_XGMAC_RX_OVER		0x13c
161
+#define MMC_XGMAC_RX_64OCT_GB		0x140
162
+#define MMC_XGMAC_RX_65OCT_GB		0x148
163
+#define MMC_XGMAC_RX_128OCT_GB		0x150
164
+#define MMC_XGMAC_RX_256OCT_GB		0x158
165
+#define MMC_XGMAC_RX_512OCT_GB		0x160
166
+#define MMC_XGMAC_RX_1024OCT_GB		0x168
167
+#define MMC_XGMAC_RX_UNI_PKT_G		0x170
168
+#define MMC_XGMAC_RX_LENGTH_ERR		0x178
169
+#define MMC_XGMAC_RX_RANGE		0x180
170
+#define MMC_XGMAC_RX_PAUSE		0x188
171
+#define MMC_XGMAC_RX_FIFOOVER_PKT	0x190
172
+#define MMC_XGMAC_RX_VLAN_PKT_GB	0x198
173
+#define MMC_XGMAC_RX_WATCHDOG_ERR	0x1a0
174
+#define MMC_XGMAC_RX_LPI_USEC		0x1a4
175
+#define MMC_XGMAC_RX_LPI_TRAN		0x1a8
176
+#define MMC_XGMAC_RX_DISCARD_PKT_GB	0x1ac
177
+#define MMC_XGMAC_RX_DISCARD_OCT_GB	0x1b4
178
+#define MMC_XGMAC_RX_ALIGN_ERR_PKT	0x1bc
179
+
180
+#define MMC_XGMAC_TX_FPE_FRAG		0x208
181
+#define MMC_XGMAC_TX_HOLD_REQ		0x20c
182
+#define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR	0x228
183
+#define MMC_XGMAC_RX_PKT_SMD_ERR	0x22c
184
+#define MMC_XGMAC_RX_PKT_ASSEMBLY_OK	0x230
185
+#define MMC_XGMAC_RX_FPE_FRAG		0x234
186
+#define MMC_XGMAC_RX_IPC_INTR_MASK	0x25c
187
+
188
+static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
132189 {
133190 	u32 value = readl(mmcaddr + MMC_CNTRL);
134191 
....@@ -141,7 +198,7 @@
141198 }
142199 
143200 /* To mask all all interrupts.*/
144
-void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr)
201
+static void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr)
145202 {
146203 	writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK);
147204 	writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK);
....@@ -153,7 +210,7 @@
153210  * counter after a read. So all the field of the mmc struct
154211  * have to be incremented.
155212  */
156
-void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
213
+static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
157214 {
158215 	mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB);
159216 	mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB);
....@@ -265,4 +322,154 @@
265322 	mmc->mmc_rx_tcp_err_octets += readl(mmcaddr + MMC_RX_TCP_ERR_OCTETS);
266323 	mmc->mmc_rx_icmp_gd_octets += readl(mmcaddr + MMC_RX_ICMP_GD_OCTETS);
267324 	mmc->mmc_rx_icmp_err_octets += readl(mmcaddr + MMC_RX_ICMP_ERR_OCTETS);
325
+
326
+	mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_TX_FPE_FRAG);
327
+	mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_TX_HOLD_REQ);
328
+	mmc->mmc_rx_packet_assembly_err_cntr +=
329
+		readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_ERR);
330
+	mmc->mmc_rx_packet_smd_err_cntr += readl(mmcaddr + MMC_RX_PKT_SMD_ERR);
331
+	mmc->mmc_rx_packet_assembly_ok_cntr +=
332
+		readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_OK);
333
+	mmc->mmc_rx_fpe_fragment_cntr += readl(mmcaddr + MMC_RX_FPE_FRAG);
268334 }
335
+
336
+const struct stmmac_mmc_ops dwmac_mmc_ops = {
337
+	.ctrl = dwmac_mmc_ctrl,
338
+	.intr_all_mask = dwmac_mmc_intr_all_mask,
339
+	.read = dwmac_mmc_read,
340
+};
341
+
342
+static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
343
+{
344
+	u32 value = readl(mmcaddr + MMC_CNTRL);
345
+
346
+	value |= (mode & 0x3F);
347
+
348
+	writel(value, mmcaddr + MMC_CNTRL);
349
+}
350
+
351
+static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr)
352
+{
353
+	writel(0x0, mmcaddr + MMC_RX_INTR_MASK);
354
+	writel(0x0, mmcaddr + MMC_TX_INTR_MASK);
355
+	writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK);
356
+}
357
+
358
+static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest)
359
+{
360
+	u64 tmp = 0;
361
+
362
+	tmp += readl(addr + reg);
363
+	tmp += ((u64 )readl(addr + reg + 0x4)) << 32;
364
+	if (tmp > GENMASK(31, 0))
365
+		*dest = ~0x0;
366
+	else
367
+		*dest = *dest + tmp;
368
+}
369
+
370
+/* This reads the MAC core counters (if actaully supported).
371
+ * by default the MMC core is programmed to reset each
372
+ * counter after a read. So all the field of the mmc struct
373
+ * have to be incremented.
374
+ */
375
+static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
376
+{
377
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_GB,
378
+			     &mmc->mmc_tx_octetcount_gb);
379
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_GB,
380
+			     &mmc->mmc_tx_framecount_gb);
381
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_G,
382
+			     &mmc->mmc_tx_broadcastframe_g);
383
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_G,
384
+			     &mmc->mmc_tx_multicastframe_g);
385
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_64OCT_GB,
386
+			     &mmc->mmc_tx_64_octets_gb);
387
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_65OCT_GB,
388
+			     &mmc->mmc_tx_65_to_127_octets_gb);
389
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_128OCT_GB,
390
+			     &mmc->mmc_tx_128_to_255_octets_gb);
391
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_256OCT_GB,
392
+			     &mmc->mmc_tx_256_to_511_octets_gb);
393
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_512OCT_GB,
394
+			     &mmc->mmc_tx_512_to_1023_octets_gb);
395
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_1024OCT_GB,
396
+			     &mmc->mmc_tx_1024_to_max_octets_gb);
397
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNI_PKT_GB,
398
+			     &mmc->mmc_tx_unicast_gb);
399
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_GB,
400
+			     &mmc->mmc_tx_multicast_gb);
401
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_GB,
402
+			     &mmc->mmc_tx_broadcast_gb);
403
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNDER,
404
+			     &mmc->mmc_tx_underflow_error);
405
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_G,
406
+			     &mmc->mmc_tx_octetcount_g);
407
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_G,
408
+			     &mmc->mmc_tx_framecount_g);
409
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PAUSE,
410
+			     &mmc->mmc_tx_pause_frame);
411
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_VLAN_PKT_G,
412
+			     &mmc->mmc_tx_vlan_frame_g);
413
+
414
+	/* MMC RX counter registers */
415
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PKT_GB,
416
+			     &mmc->mmc_rx_framecount_gb);
417
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_GB,
418
+			     &mmc->mmc_rx_octetcount_gb);
419
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_G,
420
+			     &mmc->mmc_rx_octetcount_g);
421
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_BROAD_PKT_G,
422
+			     &mmc->mmc_rx_broadcastframe_g);
423
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_MULTI_PKT_G,
424
+			     &mmc->mmc_rx_multicastframe_g);
425
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
426
+			     &mmc->mmc_rx_crc_error);
427
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
428
+			     &mmc->mmc_rx_crc_error);
429
+	mmc->mmc_rx_run_error += readl(mmcaddr + MMC_XGMAC_RX_RUNT_ERR);
430
+	mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_XGMAC_RX_JABBER_ERR);
431
+	mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_XGMAC_RX_UNDER);
432
+	mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_XGMAC_RX_OVER);
433
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_64OCT_GB,
434
+			     &mmc->mmc_rx_64_octets_gb);
435
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_65OCT_GB,
436
+			     &mmc->mmc_rx_65_to_127_octets_gb);
437
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_128OCT_GB,
438
+			     &mmc->mmc_rx_128_to_255_octets_gb);
439
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_256OCT_GB,
440
+			     &mmc->mmc_rx_256_to_511_octets_gb);
441
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_512OCT_GB,
442
+			     &mmc->mmc_rx_512_to_1023_octets_gb);
443
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_1024OCT_GB,
444
+			     &mmc->mmc_rx_1024_to_max_octets_gb);
445
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UNI_PKT_G,
446
+			     &mmc->mmc_rx_unicast_g);
447
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_LENGTH_ERR,
448
+			     &mmc->mmc_rx_length_error);
449
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_RANGE,
450
+			     &mmc->mmc_rx_autofrangetype);
451
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PAUSE,
452
+			     &mmc->mmc_rx_pause_frames);
453
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_FIFOOVER_PKT,
454
+			     &mmc->mmc_rx_fifo_overflow);
455
+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_VLAN_PKT_GB,
456
+			     &mmc->mmc_rx_vlan_frames_gb);
457
+	mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_XGMAC_RX_WATCHDOG_ERR);
458
+
459
+	mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_XGMAC_TX_FPE_FRAG);
460
+	mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_XGMAC_TX_HOLD_REQ);
461
+	mmc->mmc_rx_packet_assembly_err_cntr +=
462
+		readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_ERR);
463
+	mmc->mmc_rx_packet_smd_err_cntr +=
464
+		readl(mmcaddr + MMC_XGMAC_RX_PKT_SMD_ERR);
465
+	mmc->mmc_rx_packet_assembly_ok_cntr +=
466
+		readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_OK);
467
+	mmc->mmc_rx_fpe_fragment_cntr +=
468
+		readl(mmcaddr + MMC_XGMAC_RX_FPE_FRAG);
469
+}
470
+
471
+const struct stmmac_mmc_ops dwxgmac_mmc_ops = {
472
+	.ctrl = dwxgmac_mmc_ctrl,
473
+	.intr_all_mask = dwxgmac_mmc_intr_all_mask,
474
+	.read = dwxgmac_mmc_read,
475
+};