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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
....@@ -1,11 +1,8 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * DWMAC4 Header file.
34  *
45  * Copyright (C) 2015  STMicroelectronics Ltd
5
- *
6
- * This program is free software; you can redistribute it and/or modify it
7
- * under the terms and conditions of the GNU General Public License,
8
- * version 2, as published by the Free Software Foundation.
96  *
107  * Author: Alexandre Torgue <alexandre.torgue@st.com>
118  */
....@@ -17,10 +14,14 @@
1714 
1815 /*  MAC registers */
1916 #define GMAC_CONFIG			0x00000000
17
+#define GMAC_EXT_CONFIG			0x00000004
2018 #define GMAC_PACKET_FILTER		0x00000008
21
-#define GMAC_HASH_TAB_0_31		0x00000010
22
-#define GMAC_HASH_TAB_32_63		0x00000014
19
+#define GMAC_HASH_TAB(x)		(0x10 + (x) * 4)
20
+#define GMAC_VLAN_TAG			0x00000050
21
+#define GMAC_VLAN_TAG_DATA		0x00000054
22
+#define GMAC_VLAN_HASH_TABLE		0x00000058
2323 #define GMAC_RX_FLOW_CTRL		0x00000090
24
+#define GMAC_VLAN_INCL			0x00000060
2425 #define GMAC_QX_TX_FLOW_CTRL(x)		(0x70 + x * 4)
2526 #define GMAC_TXQ_PRTY_MAP0		0x98
2627 #define GMAC_TXQ_PRTY_MAP1		0x9C
....@@ -41,8 +42,13 @@
4142 #define GMAC_HW_FEATURE3		0x00000128
4243 #define GMAC_MDIO_ADDR			0x00000200
4344 #define GMAC_MDIO_DATA			0x00000204
45
+#define GMAC_ARP_ADDR			0x00000210
4446 #define GMAC_ADDR_HIGH(reg)		(0x300 + reg * 8)
4547 #define GMAC_ADDR_LOW(reg)		(0x304 + reg * 8)
48
+#define GMAC_L3L4_CTRL(reg)		(0x900 + (reg) * 0x30)
49
+#define GMAC_L4_ADDR(reg)		(0x904 + (reg) * 0x30)
50
+#define GMAC_L3_ADDR0(reg)		(0x910 + (reg) * 0x30)
51
+#define GMAC_L3_ADDR1(reg)		(0x914 + (reg) * 0x30)
4652 
4753 /* RX Queues Routing */
4854 #define GMAC_RXQCTRL_AVCPQ_MASK		GENMASK(2, 0)
....@@ -59,13 +65,56 @@
5965 #define GMAC_RXQCTRL_MCBCQEN_SHIFT	20
6066 #define GMAC_RXQCTRL_TACPQE		BIT(21)
6167 #define GMAC_RXQCTRL_TACPQE_SHIFT	21
68
+#define GMAC_RXQCTRL_FPRQ		GENMASK(26, 24)
69
+#define GMAC_RXQCTRL_FPRQ_SHIFT		24
6270 
6371 /* MAC Packet Filtering */
6472 #define GMAC_PACKET_FILTER_PR		BIT(0)
6573 #define GMAC_PACKET_FILTER_HMC		BIT(2)
6674 #define GMAC_PACKET_FILTER_PM		BIT(4)
75
+#define GMAC_PACKET_FILTER_PCF		BIT(7)
76
+#define GMAC_PACKET_FILTER_HPF		BIT(10)
77
+#define GMAC_PACKET_FILTER_VTFE		BIT(16)
78
+#define GMAC_PACKET_FILTER_IPFE		BIT(20)
79
+#define GMAC_PACKET_FILTER_RA		BIT(31)
6780 
6881 #define GMAC_MAX_PERFECT_ADDRESSES	128
82
+
83
+/* MAC VLAN */
84
+#define GMAC_VLAN_EDVLP			BIT(26)
85
+#define GMAC_VLAN_VTHM			BIT(25)
86
+#define GMAC_VLAN_DOVLTC		BIT(20)
87
+#define GMAC_VLAN_ESVL			BIT(18)
88
+#define GMAC_VLAN_ETV			BIT(16)
89
+#define GMAC_VLAN_VID			GENMASK(15, 0)
90
+#define GMAC_VLAN_VLTI			BIT(20)
91
+#define GMAC_VLAN_CSVL			BIT(19)
92
+#define GMAC_VLAN_VLC			GENMASK(17, 16)
93
+#define GMAC_VLAN_VLC_SHIFT		16
94
+#define GMAC_VLAN_VLHT			GENMASK(15, 0)
95
+
96
+/* MAC VLAN Tag */
97
+#define GMAC_VLAN_TAG_VID		GENMASK(15, 0)
98
+#define GMAC_VLAN_TAG_ETV		BIT(16)
99
+
100
+/* MAC VLAN Tag Control */
101
+#define GMAC_VLAN_TAG_CTRL_OB		BIT(0)
102
+#define GMAC_VLAN_TAG_CTRL_CT		BIT(1)
103
+#define GMAC_VLAN_TAG_CTRL_OFS_MASK	GENMASK(6, 2)
104
+#define GMAC_VLAN_TAG_CTRL_OFS_SHIFT	2
105
+#define GMAC_VLAN_TAG_CTRL_EVLS_MASK	GENMASK(22, 21)
106
+#define GMAC_VLAN_TAG_CTRL_EVLS_SHIFT	21
107
+#define GMAC_VLAN_TAG_CTRL_EVLRXS	BIT(24)
108
+
109
+#define GMAC_VLAN_TAG_STRIP_NONE	(0x0 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
110
+#define GMAC_VLAN_TAG_STRIP_PASS	(0x1 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
111
+#define GMAC_VLAN_TAG_STRIP_FAIL	(0x2 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
112
+#define GMAC_VLAN_TAG_STRIP_ALL		(0x3 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
113
+
114
+/* MAC VLAN Tag Data/Filter */
115
+#define GMAC_VLAN_TAG_DATA_VID		GENMASK(15, 0)
116
+#define GMAC_VLAN_TAG_DATA_VEN		BIT(16)
117
+#define GMAC_VLAN_TAG_DATA_ETV		BIT(17)
69118 
70119 /* MAC RX Queue Enable */
71120 #define GMAC_RX_QUEUE_CLEAR(queue)	~(GENMASK(1, 0) << ((queue) * 2))
....@@ -151,7 +200,12 @@
151200 #define GMAC_DEBUG_RPESTS		BIT(0)
152201 
153202 /* MAC config */
203
+#define GMAC_CONFIG_ARPEN		BIT(31)
204
+#define GMAC_CONFIG_SARC		GENMASK(30, 28)
205
+#define GMAC_CONFIG_SARC_SHIFT		28
154206 #define GMAC_CONFIG_IPC			BIT(27)
207
+#define GMAC_CONFIG_IPG			GENMASK(26, 24)
208
+#define GMAC_CONFIG_IPG_SHIFT		24
155209 #define GMAC_CONFIG_2K			BIT(22)
156210 #define GMAC_CONFIG_ACS			BIT(20)
157211 #define GMAC_CONFIG_BE			BIT(18)
....@@ -159,17 +213,29 @@
159213 #define GMAC_CONFIG_JE			BIT(16)
160214 #define GMAC_CONFIG_PS			BIT(15)
161215 #define GMAC_CONFIG_FES			BIT(14)
216
+#define GMAC_CONFIG_FES_SHIFT		14
162217 #define GMAC_CONFIG_DM			BIT(13)
218
+#define GMAC_CONFIG_LM			BIT(12)
163219 #define GMAC_CONFIG_DCRS		BIT(9)
164220 #define GMAC_CONFIG_TE			BIT(1)
165221 #define GMAC_CONFIG_RE			BIT(0)
166222 
223
+/* MAC extended config */
224
+#define GMAC_CONFIG_EIPG		GENMASK(29, 25)
225
+#define GMAC_CONFIG_EIPG_SHIFT		25
226
+#define GMAC_CONFIG_EIPG_EN		BIT(24)
227
+#define GMAC_CONFIG_HDSMS		GENMASK(22, 20)
228
+#define GMAC_CONFIG_HDSMS_SHIFT		20
229
+#define GMAC_CONFIG_HDSMS_256		(0x2 << GMAC_CONFIG_HDSMS_SHIFT)
230
+
167231 /* MAC HW features0 bitmap */
232
+#define GMAC_HW_FEAT_SAVLANINS		BIT(27)
168233 #define GMAC_HW_FEAT_ADDMAC		BIT(18)
169234 #define GMAC_HW_FEAT_RXCOESEL		BIT(16)
170235 #define GMAC_HW_FEAT_TXCOSEL		BIT(14)
171236 #define GMAC_HW_FEAT_EEESEL		BIT(13)
172237 #define GMAC_HW_FEAT_TSSEL		BIT(12)
238
+#define GMAC_HW_FEAT_ARPOFFSEL		BIT(9)
173239 #define GMAC_HW_FEAT_MMCSEL		BIT(8)
174240 #define GMAC_HW_FEAT_MGKSEL		BIT(7)
175241 #define GMAC_HW_FEAT_RWKSEL		BIT(6)
....@@ -181,8 +247,12 @@
181247 #define GMAC_HW_FEAT_MIISEL		BIT(0)
182248 
183249 /* MAC HW features1 bitmap */
250
+#define GMAC_HW_FEAT_L3L4FNUM		GENMASK(30, 27)
251
+#define GMAC_HW_HASH_TB_SZ		GENMASK(25, 24)
184252 #define GMAC_HW_FEAT_AVSEL		BIT(20)
185253 #define GMAC_HW_TSOEN			BIT(18)
254
+#define GMAC_HW_FEAT_SPHEN		BIT(17)
255
+#define GMAC_HW_ADDR64			GENMASK(15, 14)
186256 #define GMAC_HW_TXFIFOSIZE		GENMASK(10, 6)
187257 #define GMAC_HW_RXFIFOSIZE		GENMASK(4, 0)
188258 
....@@ -195,14 +265,36 @@
195265 
196266 /* MAC HW features3 bitmap */
197267 #define GMAC_HW_FEAT_ASP		GENMASK(29, 28)
268
+#define GMAC_HW_FEAT_TBSSEL		BIT(27)
269
+#define GMAC_HW_FEAT_FPESEL		BIT(26)
270
+#define GMAC_HW_FEAT_ESTWID		GENMASK(21, 20)
271
+#define GMAC_HW_FEAT_ESTDEP		GENMASK(19, 17)
272
+#define GMAC_HW_FEAT_ESTSEL		BIT(16)
198273 #define GMAC_HW_FEAT_FRPES		GENMASK(14, 13)
199274 #define GMAC_HW_FEAT_FRPBS		GENMASK(12, 11)
200275 #define GMAC_HW_FEAT_FRPSEL		BIT(10)
276
+#define GMAC_HW_FEAT_DVLAN		BIT(5)
277
+#define GMAC_HW_FEAT_NRVF		GENMASK(2, 0)
201278 
202279 /* MAC HW ADDR regs */
203280 #define GMAC_HI_DCS			GENMASK(18, 16)
204281 #define GMAC_HI_DCS_SHIFT		16
205282 #define GMAC_HI_REG_AE			BIT(31)
283
+
284
+/* L3/L4 Filters regs */
285
+#define GMAC_L4DPIM0			BIT(21)
286
+#define GMAC_L4DPM0			BIT(20)
287
+#define GMAC_L4SPIM0			BIT(19)
288
+#define GMAC_L4SPM0			BIT(18)
289
+#define GMAC_L4PEN0			BIT(16)
290
+#define GMAC_L3DAIM0			BIT(5)
291
+#define GMAC_L3DAM0			BIT(4)
292
+#define GMAC_L3SAIM0			BIT(3)
293
+#define GMAC_L3SAM0			BIT(2)
294
+#define GMAC_L3PEN0			BIT(0)
295
+#define GMAC_L4DP0			GENMASK(31, 16)
296
+#define GMAC_L4DP0_SHIFT		16
297
+#define GMAC_L4SP0			GENMASK(15, 0)
206298 
207299 /*  MTL registers */
208300 #define MTL_OPERATION_MODE		0x00000c00
....@@ -352,7 +444,8 @@
352444 
353445 /* Default operating mode of the MAC */
354446 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \
355
-			GMAC_CONFIG_BE | GMAC_CONFIG_DCRS)
447
+			GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \
448
+			GMAC_CONFIG_JE)
356449 
357450 /* To dump the core regs excluding  the Address Registers */
358451 #define	GMAC_REG_NUM	132