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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/net/ethernet/mediatek/mtk_eth_soc.h
....@@ -1,11 +1,5 @@
1
-/*   This program is free software; you can redistribute it and/or modify
2
- *   it under the terms of the GNU General Public License as published by
3
- *   the Free Software Foundation; version 2 of the License
4
- *
5
- *   This program is distributed in the hope that it will be useful,
6
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
7
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8
- *   GNU General Public License for more details.
1
+/* SPDX-License-Identifier: GPL-2.0-only */
2
+/*
93  *
104  *   Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
115  *   Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
....@@ -15,7 +9,12 @@
159 #ifndef MTK_ETH_H
1610 #define MTK_ETH_H
1711 
12
+#include <linux/dma-mapping.h>
13
+#include <linux/netdevice.h>
14
+#include <linux/of_net.h>
15
+#include <linux/u64_stats_sync.h>
1816 #include <linux/refcount.h>
17
+#include <linux/phylink.h>
1918 
2019 #define MTK_QDMA_PAGE_SIZE	2048
2120 #define	MTK_MAX_RX_LENGTH	1536
....@@ -41,7 +40,8 @@
4140 				 NETIF_F_SG | NETIF_F_TSO | \
4241 				 NETIF_F_TSO6 | \
4342 				 NETIF_F_IPV6_CSUM)
44
-#define NEXT_RX_DESP_IDX(X, Y)	(((X) + 1) & ((Y) - 1))
43
+#define MTK_HW_FEATURES_MT7628	(NETIF_F_SG | NETIF_F_RXCSUM)
44
+#define NEXT_DESP_IDX(X, Y)	(((X) + 1) & ((Y) - 1))
4545 
4646 #define MTK_MAX_RX_RING_NUM	4
4747 #define MTK_HW_LRO_DMA_SIZE	8
....@@ -84,6 +84,8 @@
8484 #define MTK_GDMA_ICS_EN		BIT(22)
8585 #define MTK_GDMA_TCS_EN		BIT(21)
8686 #define MTK_GDMA_UCS_EN		BIT(20)
87
+#define MTK_GDMA_TO_PDMA	0x0
88
+#define MTK_GDMA_DROP_ALL       0x7777
8789 
8890 /* Unicast Filter MAC Address Register - Low */
8991 #define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))
....@@ -120,6 +122,7 @@
120122 /* PDMA Global Configuration Register */
121123 #define MTK_PDMA_GLO_CFG	0xa04
122124 #define MTK_MULTI_EN		BIT(10)
125
+#define MTK_PDMA_SIZE_8DWORDS	(1 << 4)
123126 
124127 /* PDMA Reset Index Register */
125128 #define MTK_PDMA_RST_IDX	0xa08
....@@ -214,7 +217,7 @@
214217 #define FC_THRES_MIN		0x4444
215218 
216219 /* QDMA Interrupt Status Register */
217
-#define MTK_QMTK_INT_STATUS	0x1A18
220
+#define MTK_QDMA_INT_STATUS	0x1A18
218221 #define MTK_RX_DONE_DLY		BIT(30)
219222 #define MTK_RX_DONE_INT3	BIT(19)
220223 #define MTK_RX_DONE_INT2	BIT(18)
....@@ -263,8 +266,21 @@
263266 /* QDMA FQ Free Page Buffer Length Register */
264267 #define MTK_QDMA_FQ_BLEN	0x1B2C
265268 
266
-/* GMA1 Received Good Byte Count Register */
267
-#define MTK_GDM1_TX_GBCNT	0x2400
269
+/* GMA1 counter / statics register */
270
+#define MTK_GDM1_RX_GBCNT_L	0x2400
271
+#define MTK_GDM1_RX_GBCNT_H	0x2404
272
+#define MTK_GDM1_RX_GPCNT	0x2408
273
+#define MTK_GDM1_RX_OERCNT	0x2410
274
+#define MTK_GDM1_RX_FERCNT	0x2414
275
+#define MTK_GDM1_RX_SERCNT	0x2418
276
+#define MTK_GDM1_RX_LENCNT	0x241c
277
+#define MTK_GDM1_RX_CERCNT	0x2420
278
+#define MTK_GDM1_RX_FCCNT	0x2424
279
+#define MTK_GDM1_TX_SKIPCNT	0x2428
280
+#define MTK_GDM1_TX_COLCNT	0x242c
281
+#define MTK_GDM1_TX_GBCNT_L	0x2430
282
+#define MTK_GDM1_TX_GBCNT_H	0x2434
283
+#define MTK_GDM1_TX_GPCNT	0x2438
268284 #define MTK_STAT_OFFSET		0x40
269285 
270286 /* QDMA descriptor txd4 */
....@@ -278,11 +294,18 @@
278294 #define TX_DMA_OWNER_CPU	BIT(31)
279295 #define TX_DMA_LS0		BIT(30)
280296 #define TX_DMA_PLEN0(_x)	(((_x) & MTK_TX_DMA_BUF_LEN) << 16)
297
+#define TX_DMA_PLEN1(_x)	((_x) & MTK_TX_DMA_BUF_LEN)
281298 #define TX_DMA_SWC		BIT(14)
282299 #define TX_DMA_SDL(_x)		(((_x) & 0x3fff) << 16)
283300 
301
+/* PDMA on MT7628 */
302
+#define TX_DMA_DONE		BIT(31)
303
+#define TX_DMA_LS1		BIT(14)
304
+#define TX_DMA_DESP2_DEF	(TX_DMA_LS0 | TX_DMA_DONE)
305
+
284306 /* QDMA descriptor rxd2 */
285307 #define RX_DMA_DONE		BIT(31)
308
+#define RX_DMA_LSO		BIT(30)
286309 #define RX_DMA_PLEN0(_x)	(((_x) & 0x3fff) << 16)
287310 #define RX_DMA_GET_PLEN0(_x)	(((_x) >> 16) & 0x3fff)
288311 #define RX_DMA_VTAG		BIT(15)
....@@ -292,6 +315,7 @@
292315 
293316 /* QDMA descriptor rxd4 */
294317 #define RX_DMA_L4_VALID		BIT(24)
318
+#define RX_DMA_L4_VALID_PDMA	BIT(30)		/* when PDMA is used */
295319 #define RX_DMA_FPORT_SHIFT	19
296320 #define RX_DMA_FPORT_MASK	0x7
297321 
....@@ -323,21 +347,31 @@
323347 #define MAC_MCR_SPEED_100	BIT(2)
324348 #define MAC_MCR_FORCE_DPX	BIT(1)
325349 #define MAC_MCR_FORCE_LINK	BIT(0)
326
-#define MAC_MCR_FIXED_LINK	(MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \
327
-				 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \
328
-				 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \
329
-				 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \
330
-				 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \
331
-				 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK)
350
+#define MAC_MCR_FORCE_LINK_DOWN	(MAC_MCR_FORCE_MODE)
351
+
352
+/* Mac status registers */
353
+#define MTK_MAC_MSR(x)		(0x10108 + (x * 0x100))
354
+#define MAC_MSR_EEE1G		BIT(7)
355
+#define MAC_MSR_EEE100M		BIT(6)
356
+#define MAC_MSR_RX_FC		BIT(5)
357
+#define MAC_MSR_TX_FC		BIT(4)
358
+#define MAC_MSR_SPEED_1000	BIT(3)
359
+#define MAC_MSR_SPEED_100	BIT(2)
360
+#define MAC_MSR_SPEED_MASK	(MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)
361
+#define MAC_MSR_DPX		BIT(1)
362
+#define MAC_MSR_LINK		BIT(0)
332363 
333364 /* TRGMII RXC control register */
334365 #define TRGMII_RCK_CTRL		0x10300
335366 #define DQSI0(x)		((x << 0) & GENMASK(6, 0))
336367 #define DQSI1(x)		((x << 8) & GENMASK(14, 8))
337368 #define RXCTL_DMWTLAT(x)	((x << 16) & GENMASK(18, 16))
369
+#define RXC_RST			BIT(31)
338370 #define RXC_DQSISEL		BIT(30)
339371 #define RCK_CTRL_RGMII_1000	(RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
340372 #define RCK_CTRL_RGMII_10_100	RXCTL_DMWTLAT(2)
373
+
374
+#define NUM_TRGMII_CTRL		5
341375 
342376 /* TRGMII RXC control register */
343377 #define TRGMII_TCK_CTRL		0x10340
....@@ -345,6 +379,11 @@
345379 #define TXC_INV			BIT(30)
346380 #define TCK_CTRL_RGMII_1000	TXCTL_DMWTLAT(2)
347381 #define TCK_CTRL_RGMII_10_100	(TXC_INV | TXCTL_DMWTLAT(2))
382
+
383
+/* TRGMII TX Drive Strength */
384
+#define TRGMII_TD_ODT(i)	(0x10354 + 8 * (i))
385
+#define  TD_DM_DRVP(x)		((x) & 0xf)
386
+#define  TD_DM_DRVN(x)		(((x) & 0xf) << 4)
348387 
349388 /* TRGMII Interface mode register */
350389 #define INTF_MODE		0x10390
....@@ -364,18 +403,29 @@
364403 #define ETHSYS_CHIPID4_7	0x4
365404 #define MT7623_ETH		7623
366405 #define MT7622_ETH		7622
406
+#define MT7621_ETH		7621
407
+
408
+/* ethernet system control register */
409
+#define ETHSYS_SYSCFG		0x10
410
+#define SYSCFG_DRAM_TYPE_DDR2	BIT(4)
367411 
368412 /* ethernet subsystem config register */
369413 #define ETHSYS_SYSCFG0		0x14
370414 #define SYSCFG0_GE_MASK		0x3
371415 #define SYSCFG0_GE_MODE(x, y)	(x << (12 + (y * 2)))
372
-#define SYSCFG0_SGMII_MASK	(3 << 8)
373
-#define SYSCFG0_SGMII_GMAC1	((2 << 8) & GENMASK(9, 8))
374
-#define SYSCFG0_SGMII_GMAC2	((3 << 8) & GENMASK(9, 8))
416
+#define SYSCFG0_SGMII_MASK     GENMASK(9, 8)
417
+#define SYSCFG0_SGMII_GMAC1    ((2 << 8) & SYSCFG0_SGMII_MASK)
418
+#define SYSCFG0_SGMII_GMAC2    ((3 << 8) & SYSCFG0_SGMII_MASK)
419
+#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
420
+#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
421
+
375422 
376423 /* ethernet subsystem clock register */
377424 #define ETHSYS_CLKCFG0		0x2c
378425 #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
426
+#define ETHSYS_TRGMII_MT7621_MASK	(BIT(5) | BIT(6))
427
+#define ETHSYS_TRGMII_MT7621_APLL	BIT(6)
428
+#define ETHSYS_TRGMII_MT7621_DDR_PLL	BIT(5)
379429 
380430 /* ethernet reset control register */
381431 #define ETHSYS_RSTCTRL		0x34
....@@ -386,18 +436,67 @@
386436 /* Register to auto-negotiation restart */
387437 #define SGMSYS_PCS_CONTROL_1	0x0
388438 #define SGMII_AN_RESTART	BIT(9)
439
+#define SGMII_ISOLATE		BIT(10)
440
+#define SGMII_AN_ENABLE		BIT(12)
441
+#define SGMII_LINK_STATYS	BIT(18)
442
+#define SGMII_AN_ABILITY	BIT(19)
443
+#define SGMII_AN_COMPLETE	BIT(21)
444
+#define SGMII_PCS_FAULT		BIT(23)
445
+#define SGMII_AN_EXPANSION_CLR	BIT(30)
389446 
390447 /* Register to programmable link timer, the unit in 2 * 8ns */
391448 #define SGMSYS_PCS_LINK_TIMER	0x18
392449 #define SGMII_LINK_TIMER_DEFAULT	(0x186a0 & GENMASK(19, 0))
393450 
394451 /* Register to control remote fault */
395
-#define SGMSYS_SGMII_MODE	0x20
396
-#define SGMII_REMOTE_FAULT_DIS	BIT(8)
452
+#define SGMSYS_SGMII_MODE		0x20
453
+#define SGMII_IF_MODE_BIT0		BIT(0)
454
+#define SGMII_SPEED_DUPLEX_AN		BIT(1)
455
+#define SGMII_SPEED_10			0x0
456
+#define SGMII_SPEED_100			BIT(2)
457
+#define SGMII_SPEED_1000		BIT(3)
458
+#define SGMII_DUPLEX_FULL		BIT(4)
459
+#define SGMII_IF_MODE_BIT5		BIT(5)
460
+#define SGMII_REMOTE_FAULT_DIS		BIT(8)
461
+#define SGMII_CODE_SYNC_SET_VAL		BIT(9)
462
+#define SGMII_CODE_SYNC_SET_EN		BIT(10)
463
+#define SGMII_SEND_AN_ERROR_EN		BIT(11)
464
+#define SGMII_IF_MODE_MASK		GENMASK(5, 1)
465
+
466
+/* Register to set SGMII speed, ANA RG_ Control Signals III*/
467
+#define SGMSYS_ANA_RG_CS3	0x2028
468
+#define RG_PHY_SPEED_MASK	(BIT(2) | BIT(3))
469
+#define RG_PHY_SPEED_1_25G	0x0
470
+#define RG_PHY_SPEED_3_125G	BIT(2)
397471 
398472 /* Register to power up QPHY */
399473 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
400474 #define	SGMII_PHYA_PWD		BIT(4)
475
+
476
+/* Infrasys subsystem config registers */
477
+#define INFRA_MISC2            0x70c
478
+#define CO_QPHY_SEL            BIT(0)
479
+#define GEPHY_MAC_SEL          BIT(1)
480
+
481
+/* MT7628/88 specific stuff */
482
+#define MT7628_PDMA_OFFSET	0x0800
483
+#define MT7628_SDM_OFFSET	0x0c00
484
+
485
+#define MT7628_TX_BASE_PTR0	(MT7628_PDMA_OFFSET + 0x00)
486
+#define MT7628_TX_MAX_CNT0	(MT7628_PDMA_OFFSET + 0x04)
487
+#define MT7628_TX_CTX_IDX0	(MT7628_PDMA_OFFSET + 0x08)
488
+#define MT7628_TX_DTX_IDX0	(MT7628_PDMA_OFFSET + 0x0c)
489
+#define MT7628_PST_DTX_IDX0	BIT(0)
490
+
491
+#define MT7628_SDM_MAC_ADRL	(MT7628_SDM_OFFSET + 0x0c)
492
+#define MT7628_SDM_MAC_ADRH	(MT7628_SDM_OFFSET + 0x10)
493
+
494
+/* Counter / stat register */
495
+#define MT7628_SDM_TPCNT	(MT7628_SDM_OFFSET + 0x100)
496
+#define MT7628_SDM_TBCNT	(MT7628_SDM_OFFSET + 0x104)
497
+#define MT7628_SDM_RPCNT	(MT7628_SDM_OFFSET + 0x108)
498
+#define MT7628_SDM_RBCNT	(MT7628_SDM_OFFSET + 0x10c)
499
+#define MT7628_SDM_CS_ERR	(MT7628_SDM_OFFSET + 0x110)
401500 
402501 struct mtk_rx_dma {
403502 	unsigned int rxd1;
....@@ -463,15 +562,21 @@
463562  */
464563 enum mtk_clks_map {
465564 	MTK_CLK_ETHIF,
565
+	MTK_CLK_SGMIITOP,
466566 	MTK_CLK_ESW,
467567 	MTK_CLK_GP0,
468568 	MTK_CLK_GP1,
469569 	MTK_CLK_GP2,
570
+	MTK_CLK_FE,
470571 	MTK_CLK_TRGPLL,
471572 	MTK_CLK_SGMII_TX_250M,
472573 	MTK_CLK_SGMII_RX_250M,
473574 	MTK_CLK_SGMII_CDR_REF,
474575 	MTK_CLK_SGMII_CDR_FB,
576
+	MTK_CLK_SGMII2_TX_250M,
577
+	MTK_CLK_SGMII2_RX_250M,
578
+	MTK_CLK_SGMII2_CDR_REF,
579
+	MTK_CLK_SGMII2_CDR_FB,
475580 	MTK_CLK_SGMII_CK,
476581 	MTK_CLK_ETH2PLL,
477582 	MTK_CLK_MAX
....@@ -489,6 +594,22 @@
489594 				 BIT(MTK_CLK_SGMII_CDR_FB) | \
490595 				 BIT(MTK_CLK_SGMII_CK) | \
491596 				 BIT(MTK_CLK_ETH2PLL))
597
+#define MT7621_CLKS_BITMAP	(0)
598
+#define MT7628_CLKS_BITMAP	(0)
599
+#define MT7629_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
600
+				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
601
+				 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
602
+				 BIT(MTK_CLK_SGMII_TX_250M) | \
603
+				 BIT(MTK_CLK_SGMII_RX_250M) | \
604
+				 BIT(MTK_CLK_SGMII_CDR_REF) | \
605
+				 BIT(MTK_CLK_SGMII_CDR_FB) | \
606
+				 BIT(MTK_CLK_SGMII2_TX_250M) | \
607
+				 BIT(MTK_CLK_SGMII2_RX_250M) | \
608
+				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
609
+				 BIT(MTK_CLK_SGMII2_CDR_FB) | \
610
+				 BIT(MTK_CLK_SGMII_CK) | \
611
+				 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
612
+
492613 enum mtk_dev_state {
493614 	MTK_HW_INIT,
494615 	MTK_RESETTING
....@@ -529,6 +650,10 @@
529650 	struct mtk_tx_dma *last_free;
530651 	u16 thresh;
531652 	atomic_t free_count;
653
+	int dma_size;
654
+	struct mtk_tx_dma *dma_pdma;	/* For MT7628/88 PDMA handling */
655
+	dma_addr_t phys_pdma;
656
+	int cpu_idx;
532657 };
533658 
534659 /* PDMA rx ring mode */
....@@ -558,34 +683,165 @@
558683 	u32 crx_idx_reg;
559684 };
560685 
561
-#define MTK_TRGMII			BIT(0)
562
-#define MTK_GMAC1_TRGMII		(BIT(1) | MTK_TRGMII)
563
-#define MTK_ESW				BIT(4)
564
-#define MTK_GMAC1_ESW			(BIT(5) | MTK_ESW)
565
-#define MTK_SGMII			BIT(8)
566
-#define MTK_GMAC1_SGMII			(BIT(9) | MTK_SGMII)
567
-#define MTK_GMAC2_SGMII			(BIT(10) | MTK_SGMII)
568
-#define MTK_DUAL_GMAC_SHARED_SGMII	(BIT(11) | MTK_GMAC1_SGMII | \
569
-					 MTK_GMAC2_SGMII)
570
-#define MTK_HWLRO			BIT(12)
686
+enum mkt_eth_capabilities {
687
+	MTK_RGMII_BIT = 0,
688
+	MTK_TRGMII_BIT,
689
+	MTK_SGMII_BIT,
690
+	MTK_ESW_BIT,
691
+	MTK_GEPHY_BIT,
692
+	MTK_MUX_BIT,
693
+	MTK_INFRA_BIT,
694
+	MTK_SHARED_SGMII_BIT,
695
+	MTK_HWLRO_BIT,
696
+	MTK_SHARED_INT_BIT,
697
+	MTK_TRGMII_MT7621_CLK_BIT,
698
+	MTK_QDMA_BIT,
699
+	MTK_SOC_MT7628_BIT,
700
+
701
+	/* MUX BITS*/
702
+	MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
703
+	MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
704
+	MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
705
+	MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
706
+	MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
707
+
708
+	/* PATH BITS */
709
+	MTK_ETH_PATH_GMAC1_RGMII_BIT,
710
+	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
711
+	MTK_ETH_PATH_GMAC1_SGMII_BIT,
712
+	MTK_ETH_PATH_GMAC2_RGMII_BIT,
713
+	MTK_ETH_PATH_GMAC2_SGMII_BIT,
714
+	MTK_ETH_PATH_GMAC2_GEPHY_BIT,
715
+	MTK_ETH_PATH_GDM1_ESW_BIT,
716
+};
717
+
718
+/* Supported hardware group on SoCs */
719
+#define MTK_RGMII		BIT(MTK_RGMII_BIT)
720
+#define MTK_TRGMII		BIT(MTK_TRGMII_BIT)
721
+#define MTK_SGMII		BIT(MTK_SGMII_BIT)
722
+#define MTK_ESW			BIT(MTK_ESW_BIT)
723
+#define MTK_GEPHY		BIT(MTK_GEPHY_BIT)
724
+#define MTK_MUX			BIT(MTK_MUX_BIT)
725
+#define MTK_INFRA		BIT(MTK_INFRA_BIT)
726
+#define MTK_SHARED_SGMII	BIT(MTK_SHARED_SGMII_BIT)
727
+#define MTK_HWLRO		BIT(MTK_HWLRO_BIT)
728
+#define MTK_SHARED_INT		BIT(MTK_SHARED_INT_BIT)
729
+#define MTK_TRGMII_MT7621_CLK	BIT(MTK_TRGMII_MT7621_CLK_BIT)
730
+#define MTK_QDMA		BIT(MTK_QDMA_BIT)
731
+#define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)
732
+
733
+#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW		\
734
+	BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
735
+#define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY	\
736
+	BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
737
+#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY		\
738
+	BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
739
+#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII	\
740
+	BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
741
+#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII	\
742
+	BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
743
+
744
+/* Supported path present on SoCs */
745
+#define MTK_ETH_PATH_GMAC1_RGMII	BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
746
+#define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
747
+#define MTK_ETH_PATH_GMAC1_SGMII	BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
748
+#define MTK_ETH_PATH_GMAC2_RGMII	BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
749
+#define MTK_ETH_PATH_GMAC2_SGMII	BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
750
+#define MTK_ETH_PATH_GMAC2_GEPHY	BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
751
+#define MTK_ETH_PATH_GDM1_ESW		BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
752
+
753
+#define MTK_GMAC1_RGMII		(MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
754
+#define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
755
+#define MTK_GMAC1_SGMII		(MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII)
756
+#define MTK_GMAC2_RGMII		(MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
757
+#define MTK_GMAC2_SGMII		(MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
758
+#define MTK_GMAC2_GEPHY		(MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
759
+#define MTK_GDM1_ESW		(MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
760
+
761
+/* MUXes present on SoCs */
762
+/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
763
+#define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX)
764
+
765
+/* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
766
+#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY    \
767
+	(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
768
+
769
+/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
770
+#define MTK_MUX_U3_GMAC2_TO_QPHY        \
771
+	(MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
772
+
773
+/* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
774
+#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII      \
775
+	(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
776
+	MTK_SHARED_SGMII)
777
+
778
+/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
779
+#define MTK_MUX_GMAC12_TO_GEPHY_SGMII   \
780
+	(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
781
+
571782 #define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
783
+
784
+#define MT7621_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
785
+		      MTK_GMAC2_RGMII | MTK_SHARED_INT | \
786
+		      MTK_TRGMII_MT7621_CLK | MTK_QDMA)
787
+
788
+#define MT7622_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
789
+		      MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
790
+		      MTK_MUX_GDM1_TO_GMAC1_ESW | \
791
+		      MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
792
+
793
+#define MT7623_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
794
+		      MTK_QDMA)
795
+
796
+#define MT7628_CAPS  (MTK_SHARED_INT | MTK_SOC_MT7628)
797
+
798
+#define MT7629_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
799
+		      MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
800
+		      MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
801
+		      MTK_MUX_U3_GMAC2_TO_QPHY | \
802
+		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
572803 
573804 /* struct mtk_eth_data -	This is the structure holding all differences
574805  *				among various plaforms
806
+ * @ana_rgc3:                   The offset for register ANA_RGC3 related to
807
+ *				sgmiisys syscon
575808  * @caps			Flags shown the extra capability for the SoC
809
+ * @hw_features			Flags shown HW features
576810  * @required_clks		Flags shown the bitmap for required clocks on
577811  *				the target SoC
578812  * @required_pctl		A bool value to show whether the SoC requires
579813  *				the extra setup for those pins used by GMAC.
580814  */
581815 struct mtk_soc_data {
816
+	u32             ana_rgc3;
582817 	u32		caps;
583818 	u32		required_clks;
584819 	bool		required_pctl;
820
+	netdev_features_t hw_features;
585821 };
586822 
587823 /* currently no SoC has more than 2 macs */
588824 #define MTK_MAX_DEVS			2
825
+
826
+#define MTK_SGMII_PHYSPEED_AN          BIT(31)
827
+#define MTK_SGMII_PHYSPEED_MASK        GENMASK(2, 0)
828
+#define MTK_SGMII_PHYSPEED_1000        BIT(0)
829
+#define MTK_SGMII_PHYSPEED_2500        BIT(1)
830
+#define MTK_HAS_FLAGS(flags, _x)       (((flags) & (_x)) == (_x))
831
+
832
+/* struct mtk_sgmii -  This is the structure holding sgmii regmap and its
833
+ *                     characteristics
834
+ * @regmap:            The register map pointing at the range used to setup
835
+ *                     SGMII modes
836
+ * @flags:             The enum refers to which mode the sgmii wants to run on
837
+ * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap
838
+ */
839
+
840
+struct mtk_sgmii {
841
+	struct regmap   *regmap[MTK_MAX_DEVS];
842
+	u32             flags[MTK_MAX_DEVS];
843
+	u32             ana_rgc3;
844
+};
589845 
590846 /* struct mtk_eth -	This is the main datasructure for holding the state
591847  *			of the driver
....@@ -602,8 +858,8 @@
602858  * @msg_enable:		Ethtool msg level
603859  * @ethsys:		The register map pointing at the range used to setup
604860  *			MII modes
605
- * @sgmiisys:		The register map pointing at the range used to setup
606
- *			SGMII modes
861
+ * @infra:              The register map pointing at the range used to setup
862
+ *                      SGMII and GePHY path
607863  * @pctl:		The register map pointing at the range used to setup
608864  *			GMAC port drive/slew values
609865  * @dma_refcnt:		track how many netdevs are using the DMA engine
....@@ -635,7 +891,8 @@
635891 	u32				msg_enable;
636892 	unsigned long			sysclk;
637893 	struct regmap			*ethsys;
638
-	struct regmap			*sgmiisys;
894
+	struct regmap                   *infra;
895
+	struct mtk_sgmii                *sgmii;
639896 	struct regmap			*pctl;
640897 	bool				hwlro;
641898 	refcount_t			dma_refcnt;
....@@ -654,27 +911,33 @@
654911 	unsigned long			state;
655912 
656913 	const struct mtk_soc_data	*soc;
914
+
915
+	u32				tx_int_mask_reg;
916
+	u32				tx_int_status_reg;
917
+	u32				rx_dma_l4_valid;
918
+	int				ip_align;
657919 };
658920 
659921 /* struct mtk_mac -	the structure that holds the info about the MACs of the
660922  *			SoC
661923  * @id:			The number of the MAC
662
- * @ge_mode:            Interface mode kept for setup restoring
924
+ * @interface:		Interface mode kept for detecting change in hw settings
663925  * @of_node:		Our devicetree node
664926  * @hw:			Backpointer to our main datastruture
665927  * @hw_stats:		Packet statistics counter
666
- * @trgmii		Indicate if the MAC uses TRGMII connected to internal
667
-			switch
668928  */
669929 struct mtk_mac {
670930 	int				id;
671
-	int				ge_mode;
931
+	phy_interface_t			interface;
932
+	unsigned int			mode;
933
+	int				speed;
672934 	struct device_node		*of_node;
935
+	struct phylink			*phylink;
936
+	struct phylink_config		phylink_config;
673937 	struct mtk_eth			*hw;
674938 	struct mtk_hw_stats		*hw_stats;
675939 	__be32				hwlro_ip[MTK_MAX_LRO_IP_CNT];
676940 	int				hwlro_ip_cnt;
677
-	bool				trgmii;
678941 };
679942 
680943 /* the struct describing the SoC. these are declared in the soc_xyz.c files */
....@@ -686,4 +949,15 @@
686949 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
687950 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
688951 
952
+int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
953
+		   u32 ana_rgc3);
954
+int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id);
955
+int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
956
+			       const struct phylink_link_state *state);
957
+void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id);
958
+
959
+int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
960
+int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
961
+int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
962
+
689963 #endif /* MTK_ETH_H */