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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/drivers/net/ethernet/freescale/xgmac_mdio.c
..
..
@@ -49,6 +49,7 @@
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 struct mdio_fsl_priv {
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 	struct	tgec_mdio_controller __iomem *mdio_base;
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 	bool	is_little_endian;
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+	bool	has_a009885;
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 	bool	has_a011043;
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 };
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55
 
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@@ -184,10 +185,10 @@
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 {
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 	struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
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 	struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
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+	unsigned long flags;
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 	uint16_t dev_addr;
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 	uint32_t mdio_stat;
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 	uint32_t mdio_ctl;
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-	uint16_t value;
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 	int ret;
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 	bool endian = priv->is_little_endian;
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..
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@@ -219,40 +220,55 @@
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 			return ret;
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 	}
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222
 
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+	if (priv->has_a009885)
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+		/* Once the operation completes, i.e. MDIO_STAT_BSY clears, we
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+		 * must read back the data register within 16 MDC cycles.
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+		 */
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+		local_irq_save(flags);
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+
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 	/* Initiate the read */
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 	xgmac_write32(mdio_ctl | MDIO_CTL_READ, &regs->mdio_ctl, endian);
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231
 
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 	ret = xgmac_wait_until_done(&bus->dev, regs, endian);
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 	if (ret)
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-		return ret;
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+		goto irq_restore;
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 	/* Return all Fs if nothing was there */
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 	if ((xgmac_read32(&regs->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
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 	    !priv->has_a011043) {
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-		dev_err(&bus->dev,
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+		dev_dbg(&bus->dev,
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 			"Error while reading PHY%d reg at %d.%hhu\n",
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 			phy_id, dev_addr, regnum);
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-		return 0xffff;
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+		ret = 0xffff;
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+	} else {
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+		ret = xgmac_read32(&regs->mdio_data, endian) & 0xffff;
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+		dev_dbg(&bus->dev, "read %04x\n", ret);
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 	}
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-	value = xgmac_read32(&regs->mdio_data, endian) & 0xffff;
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-	dev_dbg(&bus->dev, "read %04x\n", value);
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+irq_restore:
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+	if (priv->has_a009885)
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+		local_irq_restore(flags);
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-	return value;
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+	return ret;
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 }
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254
 
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 static int xgmac_mdio_probe(struct platform_device *pdev)
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 {
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 	struct device_node *np = pdev->dev.of_node;
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 	struct mii_bus *bus;
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-	struct resource res;
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+	struct resource *res;
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 	struct mdio_fsl_priv *priv;
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 	int ret;
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262
 
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-	ret = of_address_to_resource(np, 0, &res);
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-	if (ret) {
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+	/* In DPAA-1, MDIO is one of the many FMan sub-devices. The FMan
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+	 * defines a register space that spans a large area, covering all the
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+	 * subdevice areas. Therefore, MDIO cannot claim exclusive access to
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+	 * this register area.
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+	 */
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+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+	if (!res) {
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 		dev_err(&pdev->dev, "could not obtain address\n");
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-		return ret;
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+		return -EINVAL;
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 	}
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273
 
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 	bus = mdiobus_alloc_size(sizeof(struct mdio_fsl_priv));
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@@ -263,21 +279,24 @@
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 	bus->read = xgmac_mdio_read;
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 	bus->write = xgmac_mdio_write;
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 	bus->parent = &pdev->dev;
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-	snprintf(bus->id, MII_BUS_ID_SIZE, "%llx", (unsigned long long)res.start);
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+	bus->probe_capabilities = MDIOBUS_C22_C45;
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+	snprintf(bus->id, MII_BUS_ID_SIZE, "%pa", &res->start);
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284
 
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 	/* Set the PHY base address */
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 	priv = bus->priv;
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-	priv->mdio_base = of_iomap(np, 0);
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+	priv->mdio_base = ioremap(res->start, resource_size(res));
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 	if (!priv->mdio_base) {
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 		ret = -ENOMEM;
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 		goto err_ioremap;
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 	}
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-	priv->is_little_endian = of_property_read_bool(pdev->dev.of_node,
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-						       "little-endian");
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+	priv->is_little_endian = device_property_read_bool(&pdev->dev,
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+							   "little-endian");
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-	priv->has_a011043 = of_property_read_bool(pdev->dev.of_node,
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-						  "fsl,erratum-a011043");
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+	priv->has_a009885 = device_property_read_bool(&pdev->dev,
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+						      "fsl,erratum-a009885");
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+	priv->has_a011043 = device_property_read_bool(&pdev->dev,
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+						      "fsl,erratum-a011043");
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 	ret = of_mdiobus_register(bus, np);
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 	if (ret) {
..
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@@ -321,10 +340,17 @@
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 };
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 MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
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342
 
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+static const struct acpi_device_id xgmac_acpi_match[] = {
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+	{ "NXP0006" },
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+	{ }
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+};
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+MODULE_DEVICE_TABLE(acpi, xgmac_acpi_match);
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+
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 static struct platform_driver xgmac_mdio_driver = {
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 	.driver = {
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 		.name = "fsl-fman_xmdio",
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 		.of_match_table = xgmac_mdio_match,
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+		.acpi_match_table = xgmac_acpi_match,
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 	},
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 	.probe = xgmac_mdio_probe,
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 	.remove = xgmac_mdio_remove,