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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/drivers/net/dsa/qca8k.h
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@@ -1,16 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
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  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #ifndef __QCA8K_H
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@@ -18,8 +10,10 @@
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 #include <linux/delay.h>
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 #include <linux/regmap.h>
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+#include <linux/gpio.h>
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 #define QCA8K_NUM_PORTS					7
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+#define QCA8K_MAX_MTU					9000
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 #define PHY_ID_QCA8337					0x004dd036
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 #define QCA8K_ID_QCA8337				0x13
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@@ -27,6 +21,8 @@
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 #define QCA8K_NUM_FDB_RECORDS				2048
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 #define QCA8K_CPU_PORT					0
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+
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+#define QCA8K_PORT_VID_DEF				1
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 /* Global control registers */
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 #define QCA8K_REG_MASK_CTRL				0x000
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@@ -43,14 +39,29 @@
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 #define   QCA8K_MAX_DELAY				3
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 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN		BIT(24)
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 #define   QCA8K_PORT_PAD_SGMII_EN			BIT(7)
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+#define QCA8K_REG_PWS					0x010
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+#define   QCA8K_PWS_SERDES_AEN_DIS			BIT(7)
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 #define QCA8K_REG_MODULE_EN				0x030
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 #define   QCA8K_MODULE_EN_MIB				BIT(0)
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 #define QCA8K_REG_MIB					0x034
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 #define   QCA8K_MIB_FLUSH				BIT(24)
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 #define   QCA8K_MIB_CPU_KEEP				BIT(20)
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 #define   QCA8K_MIB_BUSY				BIT(17)
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+#define QCA8K_MDIO_MASTER_CTRL				0x3c
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+#define   QCA8K_MDIO_MASTER_BUSY			BIT(31)
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+#define   QCA8K_MDIO_MASTER_EN				BIT(30)
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+#define   QCA8K_MDIO_MASTER_READ			BIT(27)
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+#define   QCA8K_MDIO_MASTER_WRITE			0
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+#define   QCA8K_MDIO_MASTER_SUP_PRE			BIT(26)
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+#define   QCA8K_MDIO_MASTER_PHY_ADDR(x)			((x) << 21)
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+#define   QCA8K_MDIO_MASTER_REG_ADDR(x)			((x) << 16)
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+#define   QCA8K_MDIO_MASTER_DATA(x)			(x)
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+#define   QCA8K_MDIO_MASTER_DATA_MASK			GENMASK(15, 0)
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+#define   QCA8K_MDIO_MASTER_MAX_PORTS			5
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+#define   QCA8K_MDIO_MASTER_MAX_REG			32
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 #define QCA8K_GOL_MAC_ADDR0				0x60
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 #define QCA8K_GOL_MAC_ADDR1				0x64
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+#define QCA8K_MAX_FRAME_SIZE				0x78
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 #define QCA8K_REG_PORT_STATUS(_i)			(0x07c + (_i) * 4)
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 #define   QCA8K_PORT_STATUS_SPEED			GENMASK(1, 0)
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 #define   QCA8K_PORT_STATUS_SPEED_10			0
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 #define   QCA8K_PORT_STATUS_LINK_UP			BIT(8)
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 #define   QCA8K_PORT_STATUS_LINK_AUTO			BIT(9)
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 #define   QCA8K_PORT_STATUS_LINK_PAUSE			BIT(10)
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+#define   QCA8K_PORT_STATUS_FLOW_AUTO			BIT(12)
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 #define QCA8K_REG_PORT_HDR_CTRL(_i)			(0x9c + (_i * 4))
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 #define   QCA8K_PORT_HDR_CTRL_RX_MASK			GENMASK(3, 2)
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 #define   QCA8K_PORT_HDR_CTRL_RX_S			2
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 #define   QCA8K_PORT_HDR_CTRL_ALL			2
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 #define   QCA8K_PORT_HDR_CTRL_MGMT			1
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 #define   QCA8K_PORT_HDR_CTRL_NONE			0
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+#define QCA8K_REG_SGMII_CTRL				0x0e0
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+#define   QCA8K_SGMII_EN_PLL				BIT(1)
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+#define   QCA8K_SGMII_EN_RX				BIT(2)
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+#define   QCA8K_SGMII_EN_TX				BIT(3)
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+#define   QCA8K_SGMII_EN_SD				BIT(4)
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+#define   QCA8K_SGMII_CLK125M_DELAY			BIT(7)
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+#define   QCA8K_SGMII_MODE_CTRL_MASK			(BIT(22) | BIT(23))
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+#define   QCA8K_SGMII_MODE_CTRL_BASEX			(0 << 22)
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+#define   QCA8K_SGMII_MODE_CTRL_PHY			(1 << 22)
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+#define   QCA8K_SGMII_MODE_CTRL_MAC			(2 << 22)
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 /* EEE control registers */
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 #define QCA8K_REG_EEE_CTRL				0x100
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 #define   QCA8K_ATU_FUNC_FULL				BIT(12)
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 #define   QCA8K_ATU_FUNC_PORT_M				0xf
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 #define   QCA8K_ATU_FUNC_PORT_S				8
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+#define QCA8K_REG_VTU_FUNC0				0x610
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+#define   QCA8K_VTU_FUNC0_VALID				BIT(20)
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+#define   QCA8K_VTU_FUNC0_IVL_EN			BIT(19)
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+#define   QCA8K_VTU_FUNC0_EG_MODE_S(_i)			(4 + (_i) * 2)
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+#define   QCA8K_VTU_FUNC0_EG_MODE_MASK			3
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+#define   QCA8K_VTU_FUNC0_EG_MODE_UNMOD			0
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+#define   QCA8K_VTU_FUNC0_EG_MODE_UNTAG			1
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+#define   QCA8K_VTU_FUNC0_EG_MODE_TAG			2
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+#define   QCA8K_VTU_FUNC0_EG_MODE_NOT			3
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+#define QCA8K_REG_VTU_FUNC1				0x614
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+#define   QCA8K_VTU_FUNC1_BUSY				BIT(31)
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+#define   QCA8K_VTU_FUNC1_VID_S				16
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+#define   QCA8K_VTU_FUNC1_FULL				BIT(4)
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 #define QCA8K_REG_GLOBAL_FW_CTRL0			0x620
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 #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN		BIT(10)
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 #define QCA8K_REG_GLOBAL_FW_CTRL1			0x624
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 #define   QCA8K_GLOBAL_FW_CTRL1_UC_DP_S			0
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 #define QCA8K_PORT_LOOKUP_CTRL(_i)			(0x660 + (_i) * 0xc)
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 #define   QCA8K_PORT_LOOKUP_MEMBER			GENMASK(6, 0)
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+#define   QCA8K_PORT_LOOKUP_VLAN_MODE			GENMASK(9, 8)
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+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_NONE		(0 << 8)
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+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK		(1 << 8)
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+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK		(2 << 8)
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+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE		(3 << 8)
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 #define   QCA8K_PORT_LOOKUP_STATE_MASK			GENMASK(18, 16)
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 #define   QCA8K_PORT_LOOKUP_STATE_DISABLED		(0 << 16)
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 #define   QCA8K_PORT_LOOKUP_STATE_BLOCKING		(1 << 16)
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 	QCA8K_FDB_SEARCH = 7,
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 };
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+enum qca8k_vlan_cmd {
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+	QCA8K_VLAN_FLUSH = 1,
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+	QCA8K_VLAN_LOAD = 2,
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+	QCA8K_VLAN_PURGE = 3,
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+	QCA8K_VLAN_REMOVE_PORT = 4,
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+	QCA8K_VLAN_NEXT = 5,
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+	QCA8K_VLAN_READ = 6,
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+};
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+
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 struct ar8xxx_port_status {
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 	int enabled;
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 };
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 	struct dsa_switch *ds;
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 	struct mutex reg_mutex;
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 	struct device *dev;
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+	struct dsa_switch_ops ops;
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+	struct gpio_desc *reset_gpio;
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+	unsigned int port_mtu[QCA8K_NUM_PORTS];
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 };
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 struct qca8k_mib_desc {