~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,15 +1,7 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Mediatek MT7530 DSA Switch driver
3	4	* Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4		- *
5		- * This program is free software; you can redistribute it and/or modify
6		- * it under the terms of the GNU General Public License version 2 as
7		- * published by the Free Software Foundation.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- * GNU General Public License for more details.
13	5	*/
14	6	#include <linux/etherdevice.h>
15	7	#include <linux/if_bridge.h>
..	..	@@ -18,11 +10,10 @@
18	10	#include <linux/mfd/syscon.h>
19	11	#include <linux/module.h>
20	12	#include <linux/netdevice.h>
21		-#include <linux/of_gpio.h>
22	13	#include <linux/of_mdio.h>
23	14	#include <linux/of_net.h>
24	15	#include <linux/of_platform.h>
25		-#include <linux/phy.h>
	16	+#include <linux/phylink.h>
26	17	#include <linux/regmap.h>
27	18	#include <linux/regulator/consumer.h>
28	19	#include <linux/reset.h>
..	..	@@ -75,58 +66,6 @@
75	66	MIB_DESC(1, 0xb4, "RxIngressDrop"),
76	67	MIB_DESC(1, 0xb8, "RxArlDrop"),
77	68	};
78		-
79		-static int
80		-mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val)
81		-{
82		- int ret;
83		-
84		- ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val);
85		- if (ret < 0)
86		- dev_err(priv->dev,
87		- "failed to priv write register\n");
88		- return ret;
89		-}
90		-
91		-static u32
92		-mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg)
93		-{
94		- int ret;
95		- u32 val;
96		-
97		- ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val);
98		- if (ret < 0) {
99		- dev_err(priv->dev,
100		- "failed to priv read register\n");
101		- return ret;
102		- }
103		-
104		- return val;
105		-}
106		-
107		-static void
108		-mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg,
109		- u32 mask, u32 set)
110		-{
111		- u32 val;
112		-
113		- val = mt7623_trgmii_read(priv, reg);
114		- val &= ~mask;
115		- val \|= set;
116		- mt7623_trgmii_write(priv, reg, val);
117		-}
118		-
119		-static void
120		-mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val)
121		-{
122		- mt7623_trgmii_rmw(priv, reg, 0, val);
123		-}
124		-
125		-static void
126		-mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val)
127		-{
128		- mt7623_trgmii_rmw(priv, reg, val, 0);
129		-}
130	69
131	70	static int
132	71	core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
..	..	@@ -296,6 +235,12 @@
296	235	}
297	236
298	237	static u32
	238	+_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
	239	+{
	240	+ return mt7530_mii_read(p->priv, p->reg);
	241	+}
	242	+
	243	+static u32
299	244	_mt7530_read(struct mt7530_dummy_poll *p)
300	245	{
301	246	struct mii_bus *bus = p->priv->bus;
..	..	@@ -434,27 +379,53 @@
434	379	mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
435	380	}
436	381
	382	+/* Setup TX circuit including relevant PAD and driving */
437	383	static int
438		-mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
	384	+mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
439	385	{
440	386	struct mt7530_priv *priv = ds->priv;
441		- u32 ncpo1, ssc_delta, trgint, i;
	387	+ u32 ncpo1, ssc_delta, trgint, i, xtal;
442	388
443		- switch (mode) {
	389	+ xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
	390	+
	391	+ if (xtal == HWTRAP_XTAL_20MHZ) {
	392	+ dev_err(priv->dev,
	393	+ "%s: MT7530 with a 20MHz XTAL is not supported!\n",
	394	+ __func__);
	395	+ return -EINVAL;
	396	+ }
	397	+
	398	+ switch (interface) {
444	399	case PHY_INTERFACE_MODE_RGMII:
445	400	trgint = 0;
	401	+ /* PLL frequency: 125MHz */
446	402	ncpo1 = 0x0c80;
447		- ssc_delta = 0x87;
448	403	break;
449	404	case PHY_INTERFACE_MODE_TRGMII:
450	405	trgint = 1;
451		- ncpo1 = 0x1400;
452		- ssc_delta = 0x57;
	406	+ if (priv->id == ID_MT7621) {
	407	+ /* PLL frequency: 150MHz: 1.2GBit */
	408	+ if (xtal == HWTRAP_XTAL_40MHZ)
	409	+ ncpo1 = 0x0780;
	410	+ if (xtal == HWTRAP_XTAL_25MHZ)
	411	+ ncpo1 = 0x0a00;
	412	+ } else { /* PLL frequency: 250MHz: 2.0Gbit */
	413	+ if (xtal == HWTRAP_XTAL_40MHZ)
	414	+ ncpo1 = 0x0c80;
	415	+ if (xtal == HWTRAP_XTAL_25MHZ)
	416	+ ncpo1 = 0x1400;
	417	+ }
453	418	break;
454	419	default:
455		- dev_err(priv->dev, "xMII mode %d not supported\n", mode);
	420	+ dev_err(priv->dev, "xMII interface %d not supported\n",
	421	+ interface);
456	422	return -EINVAL;
457	423	}
	424	+
	425	+ if (xtal == HWTRAP_XTAL_25MHZ)
	426	+ ssc_delta = 0x57;
	427	+ else
	428	+ ssc_delta = 0x87;
458	429
459	430	mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
460	431	P6_INTF_MODE(trgint));
..	..	@@ -516,26 +487,112 @@
516	487	for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
517	488	mt7530_rmw(priv, MT7530_TRGMII_RD(i),
518	489	RD_TAP_MASK, RD_TAP(16));
519		- else
520		- mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
521		-
522	490	return 0;
523	491	}
524	492
525		-static int
526		-mt7623_pad_clk_setup(struct dsa_switch *ds)
	493	+static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
527	494	{
528		- struct mt7530_priv *priv = ds->priv;
529		- int i;
	495	+ u32 val;
530	496
531		- for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
532		- mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i),
533		- TD_DM_DRVP(8) \| TD_DM_DRVN(8));
	497	+ val = mt7530_read(priv, MT7531_TOP_SIG_SR);
534	498
535		- mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST \| RXC_DQSISEL);
536		- mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST);
	499	+ return (val & PAD_DUAL_SGMII_EN) != 0;
	500	+}
537	501
	502	+static int
	503	+mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
	504	+{
538	505	return 0;
	506	+}
	507	+
	508	+static void
	509	+mt7531_pll_setup(struct mt7530_priv *priv)
	510	+{
	511	+ u32 top_sig;
	512	+ u32 hwstrap;
	513	+ u32 xtal;
	514	+ u32 val;
	515	+
	516	+ if (mt7531_dual_sgmii_supported(priv))
	517	+ return;
	518	+
	519	+ val = mt7530_read(priv, MT7531_CREV);
	520	+ top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
	521	+ hwstrap = mt7530_read(priv, MT7531_HWTRAP);
	522	+ if ((val & CHIP_REV_M) > 0)
	523	+ xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
	524	+ HWTRAP_XTAL_FSEL_25MHZ;
	525	+ else
	526	+ xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
	527	+
	528	+ /* Step 1 : Disable MT7531 COREPLL */
	529	+ val = mt7530_read(priv, MT7531_PLLGP_EN);
	530	+ val &= ~EN_COREPLL;
	531	+ mt7530_write(priv, MT7531_PLLGP_EN, val);
	532	+
	533	+ /* Step 2: switch to XTAL output */
	534	+ val = mt7530_read(priv, MT7531_PLLGP_EN);
	535	+ val \|= SW_CLKSW;
	536	+ mt7530_write(priv, MT7531_PLLGP_EN, val);
	537	+
	538	+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
	539	+ val &= ~RG_COREPLL_EN;
	540	+ mt7530_write(priv, MT7531_PLLGP_CR0, val);
	541	+
	542	+ /* Step 3: disable PLLGP and enable program PLLGP */
	543	+ val = mt7530_read(priv, MT7531_PLLGP_EN);
	544	+ val \|= SW_PLLGP;
	545	+ mt7530_write(priv, MT7531_PLLGP_EN, val);
	546	+
	547	+ /* Step 4: program COREPLL output frequency to 500MHz */
	548	+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
	549	+ val &= ~RG_COREPLL_POSDIV_M;
	550	+ val \|= 2 << RG_COREPLL_POSDIV_S;
	551	+ mt7530_write(priv, MT7531_PLLGP_CR0, val);
	552	+ usleep_range(25, 35);
	553	+
	554	+ switch (xtal) {
	555	+ case HWTRAP_XTAL_FSEL_25MHZ:
	556	+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
	557	+ val &= ~RG_COREPLL_SDM_PCW_M;
	558	+ val \|= 0x140000 << RG_COREPLL_SDM_PCW_S;
	559	+ mt7530_write(priv, MT7531_PLLGP_CR0, val);
	560	+ break;
	561	+ case HWTRAP_XTAL_FSEL_40MHZ:
	562	+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
	563	+ val &= ~RG_COREPLL_SDM_PCW_M;
	564	+ val \|= 0x190000 << RG_COREPLL_SDM_PCW_S;
	565	+ mt7530_write(priv, MT7531_PLLGP_CR0, val);
	566	+ break;
	567	+ };
	568	+
	569	+ /* Set feedback divide ratio update signal to high */
	570	+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
	571	+ val \|= RG_COREPLL_SDM_PCW_CHG;
	572	+ mt7530_write(priv, MT7531_PLLGP_CR0, val);
	573	+ /* Wait for at least 16 XTAL clocks */
	574	+ usleep_range(10, 20);
	575	+
	576	+ /* Step 5: set feedback divide ratio update signal to low */
	577	+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
	578	+ val &= ~RG_COREPLL_SDM_PCW_CHG;
	579	+ mt7530_write(priv, MT7531_PLLGP_CR0, val);
	580	+
	581	+ /* Enable 325M clock for SGMII */
	582	+ mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
	583	+
	584	+ /* Enable 250SSC clock for RGMII */
	585	+ mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
	586	+
	587	+ /* Step 6: Enable MT7531 PLL */
	588	+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
	589	+ val \|= RG_COREPLL_EN;
	590	+ mt7530_write(priv, MT7531_PLLGP_CR0, val);
	591	+
	592	+ val = mt7530_read(priv, MT7531_PLLGP_EN);
	593	+ val \|= EN_COREPLL;
	594	+ mt7530_write(priv, MT7531_PLLGP_EN, val);
	595	+ usleep_range(25, 35);
539	596	}
540	597
541	598	static void
..	..	@@ -545,17 +602,6 @@
545	602
546	603	mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
547	604	mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
548		-}
549		-
550		-static void
551		-mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable)
552		-{
553		- u32 mask = PMCR_TX_EN \| PMCR_RX_EN \| PMCR_FORCE_LNK;
554		-
555		- if (enable)
556		- mt7530_set(priv, MT7530_PMCR_P(port), mask);
557		- else
558		- mt7530_clear(priv, MT7530_PMCR_P(port), mask);
559	605	}
560	606
561	607	static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
..	..	@@ -571,6 +617,217 @@
571	617	struct mt7530_priv *priv = ds->priv;
572	618
573	619	return mdiobus_write_nested(priv->bus, port, regnum, val);
	620	+}
	621	+
	622	+static int
	623	+mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
	624	+ int regnum)
	625	+{
	626	+ struct mii_bus *bus = priv->bus;
	627	+ struct mt7530_dummy_poll p;
	628	+ u32 reg, val;
	629	+ int ret;
	630	+
	631	+ INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
	632	+
	633	+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
	634	+
	635	+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
	636	+ !(val & MT7531_PHY_ACS_ST), 20, 100000);
	637	+ if (ret < 0) {
	638	+ dev_err(priv->dev, "poll timeout\n");
	639	+ goto out;
	640	+ }
	641	+
	642	+ reg = MT7531_MDIO_CL45_ADDR \| MT7531_MDIO_PHY_ADDR(port) \|
	643	+ MT7531_MDIO_DEV_ADDR(devad) \| regnum;
	644	+ mt7530_mii_write(priv, MT7531_PHY_IAC, reg \| MT7531_PHY_ACS_ST);
	645	+
	646	+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
	647	+ !(val & MT7531_PHY_ACS_ST), 20, 100000);
	648	+ if (ret < 0) {
	649	+ dev_err(priv->dev, "poll timeout\n");
	650	+ goto out;
	651	+ }
	652	+
	653	+ reg = MT7531_MDIO_CL45_READ \| MT7531_MDIO_PHY_ADDR(port) \|
	654	+ MT7531_MDIO_DEV_ADDR(devad);
	655	+ mt7530_mii_write(priv, MT7531_PHY_IAC, reg \| MT7531_PHY_ACS_ST);
	656	+
	657	+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
	658	+ !(val & MT7531_PHY_ACS_ST), 20, 100000);
	659	+ if (ret < 0) {
	660	+ dev_err(priv->dev, "poll timeout\n");
	661	+ goto out;
	662	+ }
	663	+
	664	+ ret = val & MT7531_MDIO_RW_DATA_MASK;
	665	+out:
	666	+ mutex_unlock(&bus->mdio_lock);
	667	+
	668	+ return ret;
	669	+}
	670	+
	671	+static int
	672	+mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
	673	+ int regnum, u32 data)
	674	+{
	675	+ struct mii_bus *bus = priv->bus;
	676	+ struct mt7530_dummy_poll p;
	677	+ u32 val, reg;
	678	+ int ret;
	679	+
	680	+ INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
	681	+
	682	+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
	683	+
	684	+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
	685	+ !(val & MT7531_PHY_ACS_ST), 20, 100000);
	686	+ if (ret < 0) {
	687	+ dev_err(priv->dev, "poll timeout\n");
	688	+ goto out;
	689	+ }
	690	+
	691	+ reg = MT7531_MDIO_CL45_ADDR \| MT7531_MDIO_PHY_ADDR(port) \|
	692	+ MT7531_MDIO_DEV_ADDR(devad) \| regnum;
	693	+ mt7530_mii_write(priv, MT7531_PHY_IAC, reg \| MT7531_PHY_ACS_ST);
	694	+
	695	+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
	696	+ !(val & MT7531_PHY_ACS_ST), 20, 100000);
	697	+ if (ret < 0) {
	698	+ dev_err(priv->dev, "poll timeout\n");
	699	+ goto out;
	700	+ }
	701	+
	702	+ reg = MT7531_MDIO_CL45_WRITE \| MT7531_MDIO_PHY_ADDR(port) \|
	703	+ MT7531_MDIO_DEV_ADDR(devad) \| data;
	704	+ mt7530_mii_write(priv, MT7531_PHY_IAC, reg \| MT7531_PHY_ACS_ST);
	705	+
	706	+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
	707	+ !(val & MT7531_PHY_ACS_ST), 20, 100000);
	708	+ if (ret < 0) {
	709	+ dev_err(priv->dev, "poll timeout\n");
	710	+ goto out;
	711	+ }
	712	+
	713	+out:
	714	+ mutex_unlock(&bus->mdio_lock);
	715	+
	716	+ return ret;
	717	+}
	718	+
	719	+static int
	720	+mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
	721	+{
	722	+ struct mii_bus *bus = priv->bus;
	723	+ struct mt7530_dummy_poll p;
	724	+ int ret;
	725	+ u32 val;
	726	+
	727	+ INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
	728	+
	729	+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
	730	+
	731	+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
	732	+ !(val & MT7531_PHY_ACS_ST), 20, 100000);
	733	+ if (ret < 0) {
	734	+ dev_err(priv->dev, "poll timeout\n");
	735	+ goto out;
	736	+ }
	737	+
	738	+ val = MT7531_MDIO_CL22_READ \| MT7531_MDIO_PHY_ADDR(port) \|
	739	+ MT7531_MDIO_REG_ADDR(regnum);
	740	+
	741	+ mt7530_mii_write(priv, MT7531_PHY_IAC, val \| MT7531_PHY_ACS_ST);
	742	+
	743	+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
	744	+ !(val & MT7531_PHY_ACS_ST), 20, 100000);
	745	+ if (ret < 0) {
	746	+ dev_err(priv->dev, "poll timeout\n");
	747	+ goto out;
	748	+ }
	749	+
	750	+ ret = val & MT7531_MDIO_RW_DATA_MASK;
	751	+out:
	752	+ mutex_unlock(&bus->mdio_lock);
	753	+
	754	+ return ret;
	755	+}
	756	+
	757	+static int
	758	+mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
	759	+ u16 data)
	760	+{
	761	+ struct mii_bus *bus = priv->bus;
	762	+ struct mt7530_dummy_poll p;
	763	+ int ret;
	764	+ u32 reg;
	765	+
	766	+ INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
	767	+
	768	+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
	769	+
	770	+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
	771	+ !(reg & MT7531_PHY_ACS_ST), 20, 100000);
	772	+ if (ret < 0) {
	773	+ dev_err(priv->dev, "poll timeout\n");
	774	+ goto out;
	775	+ }
	776	+
	777	+ reg = MT7531_MDIO_CL22_WRITE \| MT7531_MDIO_PHY_ADDR(port) \|
	778	+ MT7531_MDIO_REG_ADDR(regnum) \| data;
	779	+
	780	+ mt7530_mii_write(priv, MT7531_PHY_IAC, reg \| MT7531_PHY_ACS_ST);
	781	+
	782	+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
	783	+ !(reg & MT7531_PHY_ACS_ST), 20, 100000);
	784	+ if (ret < 0) {
	785	+ dev_err(priv->dev, "poll timeout\n");
	786	+ goto out;
	787	+ }
	788	+
	789	+out:
	790	+ mutex_unlock(&bus->mdio_lock);
	791	+
	792	+ return ret;
	793	+}
	794	+
	795	+static int
	796	+mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)
	797	+{
	798	+ struct mt7530_priv *priv = ds->priv;
	799	+ int devad;
	800	+ int ret;
	801	+
	802	+ if (regnum & MII_ADDR_C45) {
	803	+ devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
	804	+ ret = mt7531_ind_c45_phy_read(priv, port, devad,
	805	+ regnum & MII_REGADDR_C45_MASK);
	806	+ } else {
	807	+ ret = mt7531_ind_c22_phy_read(priv, port, regnum);
	808	+ }
	809	+
	810	+ return ret;
	811	+}
	812	+
	813	+static int
	814	+mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,
	815	+ u16 data)
	816	+{
	817	+ struct mt7530_priv *priv = ds->priv;
	818	+ int devad;
	819	+ int ret;
	820	+
	821	+ if (regnum & MII_ADDR_C45) {
	822	+ devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
	823	+ ret = mt7531_ind_c45_phy_write(priv, port, devad,
	824	+ regnum & MII_REGADDR_C45_MASK,
	825	+ data);
	826	+ } else {
	827	+ ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
	828	+ }
	829	+
	830	+ return ret;
574	831	}
575	832
576	833	static void
..	..	@@ -617,80 +874,103 @@
617	874	return ARRAY_SIZE(mt7530_mib);
618	875	}
619	876
620		-static void mt7530_adjust_link(struct dsa_switch *ds, int port,
621		- struct phy_device *phydev)
	877	+static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
622	878	{
623	879	struct mt7530_priv *priv = ds->priv;
	880	+ u8 tx_delay = 0;
	881	+ int val;
624	882
625		- if (phy_is_pseudo_fixed_link(phydev)) {
626		- dev_dbg(priv->dev, "phy-mode for master device = %x\n",
627		- phydev->interface);
	883	+ mutex_lock(&priv->reg_mutex);
628	884
629		- /* Setup TX circuit incluing relevant PAD and driving */
630		- mt7530_pad_clk_setup(ds, phydev->interface);
	885	+ val = mt7530_read(priv, MT7530_MHWTRAP);
631	886
632		- /* Setup RX circuit, relevant PAD and driving on the host
633		- * which must be placed after the setup on the device side is
634		- * all finished.
635		- */
636		- mt7623_pad_clk_setup(ds);
637		- } else {
638		- u16 lcl_adv = 0, rmt_adv = 0;
639		- u8 flowctrl;
640		- u32 mcr = PMCR_USERP_LINK \| PMCR_FORCE_MODE;
	887	+ val \|= MHWTRAP_MANUAL \| MHWTRAP_P5_MAC_SEL \| MHWTRAP_P5_DIS;
	888	+ val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
641	889
642		- switch (phydev->speed) {
643		- case SPEED_1000:
644		- mcr \|= PMCR_FORCE_SPEED_1000;
645		- break;
646		- case SPEED_100:
647		- mcr \|= PMCR_FORCE_SPEED_100;
648		- break;
649		- };
	890	+ switch (priv->p5_intf_sel) {
	891	+ case P5_INTF_SEL_PHY_P0:
	892	+ /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
	893	+ val \|= MHWTRAP_PHY0_SEL;
	894	+ fallthrough;
	895	+ case P5_INTF_SEL_PHY_P4:
	896	+ /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
	897	+ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
650	898
651		- if (phydev->link)
652		- mcr \|= PMCR_FORCE_LNK;
653		-
654		- if (phydev->duplex) {
655		- mcr \|= PMCR_FORCE_FDX;
656		-
657		- if (phydev->pause)
658		- rmt_adv = LPA_PAUSE_CAP;
659		- if (phydev->asym_pause)
660		- rmt_adv \|= LPA_PAUSE_ASYM;
661		-
662		- if (phydev->advertising & ADVERTISED_Pause)
663		- lcl_adv \|= ADVERTISE_PAUSE_CAP;
664		- if (phydev->advertising & ADVERTISED_Asym_Pause)
665		- lcl_adv \|= ADVERTISE_PAUSE_ASYM;
666		-
667		- flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
668		-
669		- if (flowctrl & FLOW_CTRL_TX)
670		- mcr \|= PMCR_TX_FC_EN;
671		- if (flowctrl & FLOW_CTRL_RX)
672		- mcr \|= PMCR_RX_FC_EN;
673		- }
674		- mt7530_write(priv, MT7530_PMCR_P(port), mcr);
	899	+ /* Setup the MAC by default for the cpu port */
	900	+ mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
	901	+ break;
	902	+ case P5_INTF_SEL_GMAC5:
	903	+ /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
	904	+ val &= ~MHWTRAP_P5_DIS;
	905	+ break;
	906	+ case P5_DISABLED:
	907	+ interface = PHY_INTERFACE_MODE_NA;
	908	+ break;
	909	+ default:
	910	+ dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
	911	+ priv->p5_intf_sel);
	912	+ goto unlock_exit;
675	913	}
	914	+
	915	+ /* Setup RGMII settings */
	916	+ if (phy_interface_mode_is_rgmii(interface)) {
	917	+ val \|= MHWTRAP_P5_RGMII_MODE;
	918	+
	919	+ /* P5 RGMII RX Clock Control: delay setting for 1000M */
	920	+ mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
	921	+
	922	+ /* Don't set delay in DSA mode */
	923	+ if (!dsa_is_dsa_port(priv->ds, 5) &&
	924	+ (interface == PHY_INTERFACE_MODE_RGMII_TXID \|\|
	925	+ interface == PHY_INTERFACE_MODE_RGMII_ID))
	926	+ tx_delay = 4; /* n * 0.5 ns */
	927	+
	928	+ /* P5 RGMII TX Clock Control: delay x */
	929	+ mt7530_write(priv, MT7530_P5RGMIITXCR,
	930	+ CSR_RGMII_TXC_CFG(0x10 + tx_delay));
	931	+
	932	+ /* reduce P5 RGMII Tx driving, 8mA */
	933	+ mt7530_write(priv, MT7530_IO_DRV_CR,
	934	+ P5_IO_CLK_DRV(1) \| P5_IO_DATA_DRV(1));
	935	+ }
	936	+
	937	+ mt7530_write(priv, MT7530_MHWTRAP, val);
	938	+
	939	+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
	940	+ val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
	941	+
	942	+ priv->p5_interface = interface;
	943	+
	944	+unlock_exit:
	945	+ mutex_unlock(&priv->reg_mutex);
676	946	}
677	947
678	948	static int
679		-mt7530_cpu_port_enable(struct mt7530_priv *priv,
680		- int port)
	949	+mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
681	950	{
	951	+ struct mt7530_priv *priv = ds->priv;
	952	+ int ret;
	953	+
	954	+ /* Setup max capability of CPU port at first */
	955	+ if (priv->info->cpu_port_config) {
	956	+ ret = priv->info->cpu_port_config(ds, port);
	957	+ if (ret)
	958	+ return ret;
	959	+ }
	960	+
682	961	/* Enable Mediatek header mode on the cpu port */
683	962	mt7530_write(priv, MT7530_PVC_P(port),
684	963	PORT_SPEC_TAG);
685	964
686		- /* Setup the MAC by default for the cpu port */
687		- mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
688		-
689	965	/* Unknown multicast frame forwarding to the cpu port */
690	966	mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
691	967
	968	+ /* Set CPU port number */
	969	+ if (priv->id == ID_MT7621)
	970	+ mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN \| CPU_PORT(port));
	971	+
692	972	/* CPU port gets connected to all user ports of
693		- * the switch
	973	+ * the switch.
694	974	*/
695	975	mt7530_write(priv, MT7530_PCR_P(port),
696	976	PCR_MATRIX(dsa_user_ports(priv->ds)));
..	..	@@ -706,9 +986,6 @@
706	986
707	987	mutex_lock(&priv->reg_mutex);
708	988
709		- /* Setup the MAC for the user port */
710		- mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK);
711		-
712	989	/* Allow the user port gets connected to the cpu port and also
713	990	* restore the port matrix if the port is the member of a certain
714	991	* bridge.
..	..	@@ -717,7 +994,7 @@
717	994	priv->ports[port].enable = true;
718	995	mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
719	996	priv->ports[port].pm);
720		- mt7530_port_set_status(priv, port, 1);
	997	+ mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
721	998
722	999	mutex_unlock(&priv->reg_mutex);
723	1000
..	..	@@ -725,8 +1002,7 @@
725	1002	}
726	1003
727	1004	static void
728		-mt7530_port_disable(struct dsa_switch *ds, int port,
729		- struct phy_device *phy)
	1005	+mt7530_port_disable(struct dsa_switch *ds, int port)
730	1006	{
731	1007	struct mt7530_priv *priv = ds->priv;
732	1008
..	..	@@ -738,7 +1014,7 @@
738	1014	priv->ports[port].enable = false;
739	1015	mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
740	1016	PCR_MATRIX_CLR);
741		- mt7530_port_set_status(priv, port, 0);
	1017	+ mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
742	1018
743	1019	mutex_unlock(&priv->reg_mutex);
744	1020	}
..	..	@@ -826,11 +1102,9 @@
826	1102	VLAN_ATTR(MT7530_VLAN_TRANSPARENT) \|
827	1103	PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
828	1104
829		- priv->ports[port].vlan_filtering = false;
830		-
831	1105	for (i = 0; i < MT7530_NUM_PORTS; i++) {
832	1106	if (dsa_is_user_port(ds, i) &&
833		- priv->ports[i].vlan_filtering) {
	1107	+ dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
834	1108	all_user_ports_removed = false;
835	1109	break;
836	1110	}
..	..	@@ -884,11 +1158,8 @@
884	1158	/* Remove this port from the port matrix of the other ports
885	1159	* in the same bridge. If the port is disabled, port matrix
886	1160	* is kept and not being setup until the port becomes enabled.
887		- * And the other port's port matrix cannot be broken when the
888		- * other port is still a VLAN-aware port.
889	1161	*/
890		- if (!priv->ports[i].vlan_filtering &&
891		- dsa_is_user_port(ds, i) && i != port) {
	1162	+ if (dsa_is_user_port(ds, i) && i != port) {
892	1163	if (dsa_to_port(ds, i)->bridge_dev != bridge)
893	1164	continue;
894	1165	if (priv->ports[i].enable)
..	..	@@ -905,8 +1176,6 @@
905	1176	mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
906	1177	PCR_MATRIX(BIT(MT7530_CPU_PORT)));
907	1178	priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
908		-
909		- mt7530_port_set_vlan_unaware(ds, port);
910	1179
911	1180	mutex_unlock(&priv->reg_mutex);
912	1181	}
..	..	@@ -1007,11 +1276,11 @@
1007	1276
1008	1277	static int
1009	1278	mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
1010		- bool vlan_filtering)
	1279	+ bool vlan_filtering,
	1280	+ struct switchdev_trans *trans)
1011	1281	{
1012		- struct mt7530_priv *priv = ds->priv;
1013		-
1014		- priv->ports[port].vlan_filtering = vlan_filtering;
	1282	+ if (switchdev_trans_ph_prepare(trans))
	1283	+ return 0;
1015	1284
1016	1285	if (vlan_filtering) {
1017	1286	/* The port is being kept as VLAN-unaware port when bridge is
..	..	@@ -1021,6 +1290,8 @@
1021	1290	*/
1022	1291	mt7530_port_set_vlan_aware(ds, port);
1023	1292	mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
	1293	+ } else {
	1294	+ mt7530_port_set_vlan_unaware(ds, port);
1024	1295	}
1025	1296
1026	1297	return 0;
..	..	@@ -1132,12 +1403,6 @@
1132	1403	struct mt7530_priv *priv = ds->priv;
1133	1404	u16 vid;
1134	1405
1135		- /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1136		- * being set.
1137		- */
1138		- if (!priv->ports[port].vlan_filtering)
1139		- return;
1140		-
1141	1406	mutex_lock(&priv->reg_mutex);
1142	1407
1143	1408	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
..	..	@@ -1163,12 +1428,6 @@
1163	1428	struct mt7530_priv *priv = ds->priv;
1164	1429	u16 vid, pvid;
1165	1430
1166		- /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1167		- * being set.
1168		- */
1169		- if (!priv->ports[port].vlan_filtering)
1170		- return 0;
1171		-
1172	1431	mutex_lock(&priv->reg_mutex);
1173	1432
1174	1433	pvid = priv->ports[port].pvid;
..	..	@@ -1192,8 +1451,82 @@
1192	1451	return 0;
1193	1452	}
1194	1453
	1454	+static int mt753x_mirror_port_get(unsigned int id, u32 val)
	1455	+{
	1456	+ return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
	1457	+ MIRROR_PORT(val);
	1458	+}
	1459	+
	1460	+static int mt753x_mirror_port_set(unsigned int id, u32 val)
	1461	+{
	1462	+ return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
	1463	+ MIRROR_PORT(val);
	1464	+}
	1465	+
	1466	+static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
	1467	+ struct dsa_mall_mirror_tc_entry *mirror,
	1468	+ bool ingress)
	1469	+{
	1470	+ struct mt7530_priv *priv = ds->priv;
	1471	+ int monitor_port;
	1472	+ u32 val;
	1473	+
	1474	+ /* Check for existent entry */
	1475	+ if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
	1476	+ return -EEXIST;
	1477	+
	1478	+ val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
	1479	+
	1480	+ /* MT7530 only supports one monitor port */
	1481	+ monitor_port = mt753x_mirror_port_get(priv->id, val);
	1482	+ if (val & MT753X_MIRROR_EN(priv->id) &&
	1483	+ monitor_port != mirror->to_local_port)
	1484	+ return -EEXIST;
	1485	+
	1486	+ val \|= MT753X_MIRROR_EN(priv->id);
	1487	+ val &= ~MT753X_MIRROR_MASK(priv->id);
	1488	+ val \|= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
	1489	+ mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
	1490	+
	1491	+ val = mt7530_read(priv, MT7530_PCR_P(port));
	1492	+ if (ingress) {
	1493	+ val \|= PORT_RX_MIR;
	1494	+ priv->mirror_rx \|= BIT(port);
	1495	+ } else {
	1496	+ val \|= PORT_TX_MIR;
	1497	+ priv->mirror_tx \|= BIT(port);
	1498	+ }
	1499	+ mt7530_write(priv, MT7530_PCR_P(port), val);
	1500	+
	1501	+ return 0;
	1502	+}
	1503	+
	1504	+static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
	1505	+ struct dsa_mall_mirror_tc_entry *mirror)
	1506	+{
	1507	+ struct mt7530_priv *priv = ds->priv;
	1508	+ u32 val;
	1509	+
	1510	+ val = mt7530_read(priv, MT7530_PCR_P(port));
	1511	+ if (mirror->ingress) {
	1512	+ val &= ~PORT_RX_MIR;
	1513	+ priv->mirror_rx &= ~BIT(port);
	1514	+ } else {
	1515	+ val &= ~PORT_TX_MIR;
	1516	+ priv->mirror_tx &= ~BIT(port);
	1517	+ }
	1518	+ mt7530_write(priv, MT7530_PCR_P(port), val);
	1519	+
	1520	+ if (!priv->mirror_rx && !priv->mirror_tx) {
	1521	+ val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
	1522	+ val &= ~MT753X_MIRROR_EN(priv->id);
	1523	+ mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
	1524	+ }
	1525	+}
	1526	+
1195	1527	static enum dsa_tag_protocol
1196		-mtk_get_tag_protocol(struct dsa_switch *ds, int port)
	1528	+mtk_get_tag_protocol(struct dsa_switch *ds, int port,
	1529	+ enum dsa_tag_protocol mp)
1197	1530	{
1198	1531	struct mt7530_priv *priv = ds->priv;
1199	1532
..	..	@@ -1210,34 +1543,37 @@
1210	1543	mt7530_setup(struct dsa_switch *ds)
1211	1544	{
1212	1545	struct mt7530_priv *priv = ds->priv;
1213		- int ret, i;
1214		- u32 id, val;
1215		- struct device_node *dn;
	1546	+ struct device_node *phy_node;
	1547	+ struct device_node *mac_np;
1216	1548	struct mt7530_dummy_poll p;
	1549	+ phy_interface_t interface;
	1550	+ struct device_node *dn;
	1551	+ u32 id, val;
	1552	+ int ret, i;
1217	1553
1218	1554	/* The parent node of master netdev which holds the common system
1219	1555	* controller also is the container for two GMACs nodes representing
1220	1556	* as two netdev instances.
1221	1557	*/
1222		- dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent;
1223		- priv->ethernet = syscon_node_to_regmap(dn);
1224		- if (IS_ERR(priv->ethernet))
1225		- return PTR_ERR(priv->ethernet);
	1558	+ dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
	1559	+ ds->configure_vlan_while_not_filtering = true;
1226	1560
1227		- regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1228		- ret = regulator_enable(priv->core_pwr);
1229		- if (ret < 0) {
1230		- dev_err(priv->dev,
1231		- "Failed to enable core power: %d\n", ret);
1232		- return ret;
1233		- }
	1561	+ if (priv->id == ID_MT7530) {
	1562	+ regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
	1563	+ ret = regulator_enable(priv->core_pwr);
	1564	+ if (ret < 0) {
	1565	+ dev_err(priv->dev,
	1566	+ "Failed to enable core power: %d\n", ret);
	1567	+ return ret;
	1568	+ }
1234	1569
1235		- regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1236		- ret = regulator_enable(priv->io_pwr);
1237		- if (ret < 0) {
1238		- dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1239		- ret);
1240		- return ret;
	1570	+ regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
	1571	+ ret = regulator_enable(priv->io_pwr);
	1572	+ if (ret < 0) {
	1573	+ dev_err(priv->dev, "Failed to enable io pwr: %d\n",
	1574	+ ret);
	1575	+ return ret;
	1576	+ }
1241	1577	}
1242	1578
1243	1579	/* Reset whole chip through gpio pin or memory-mapped registers for
..	..	@@ -1280,6 +1616,8 @@
1280	1616	val \|= MHWTRAP_MANUAL;
1281	1617	mt7530_write(priv, MT7530_MHWTRAP, val);
1282	1618
	1619	+ priv->p6_interface = PHY_INTERFACE_MODE_NA;
	1620	+
1283	1621	/* Enable and reset MIB counters */
1284	1622	mt7530_mib_reset(ds);
1285	1623
..	..	@@ -1288,15 +1626,62 @@
1288	1626	mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1289	1627	PCR_MATRIX_CLR);
1290	1628
1291		- if (dsa_is_cpu_port(ds, i))
1292		- mt7530_cpu_port_enable(priv, i);
1293		- else
1294		- mt7530_port_disable(ds, i, NULL);
	1629	+ if (dsa_is_cpu_port(ds, i)) {
	1630	+ ret = mt753x_cpu_port_enable(ds, i);
	1631	+ if (ret)
	1632	+ return ret;
	1633	+ } else
	1634	+ mt7530_port_disable(ds, i);
1295	1635
1296	1636	/* Enable consistent egress tag */
1297	1637	mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1298	1638	PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1299	1639	}
	1640	+
	1641	+ /* Setup port 5 */
	1642	+ priv->p5_intf_sel = P5_DISABLED;
	1643	+ interface = PHY_INTERFACE_MODE_NA;
	1644	+
	1645	+ if (!dsa_is_unused_port(ds, 5)) {
	1646	+ priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
	1647	+ ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
	1648	+ if (ret && ret != -ENODEV)
	1649	+ return ret;
	1650	+ } else {
	1651	+ /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
	1652	+ for_each_child_of_node(dn, mac_np) {
	1653	+ if (!of_device_is_compatible(mac_np,
	1654	+ "mediatek,eth-mac"))
	1655	+ continue;
	1656	+
	1657	+ ret = of_property_read_u32(mac_np, "reg", &id);
	1658	+ if (ret < 0 \|\| id != 1)
	1659	+ continue;
	1660	+
	1661	+ phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
	1662	+ if (!phy_node)
	1663	+ continue;
	1664	+
	1665	+ if (phy_node->parent == priv->dev->of_node->parent) {
	1666	+ ret = of_get_phy_mode(mac_np, &interface);
	1667	+ if (ret && ret != -ENODEV) {
	1668	+ of_node_put(mac_np);
	1669	+ of_node_put(phy_node);
	1670	+ return ret;
	1671	+ }
	1672	+ id = of_mdio_parse_addr(ds->dev, phy_node);
	1673	+ if (id == 0)
	1674	+ priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
	1675	+ if (id == 4)
	1676	+ priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
	1677	+ }
	1678	+ of_node_put(mac_np);
	1679	+ of_node_put(phy_node);
	1680	+ break;
	1681	+ }
	1682	+ }
	1683	+
	1684	+ mt7530_setup_port5(ds, interface);
1300	1685
1301	1686	/* Flush the FDB table */
1302	1687	ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
..	..	@@ -1306,15 +1691,814 @@
1306	1691	return 0;
1307	1692	}
1308	1693
	1694	+static int
	1695	+mt7531_setup(struct dsa_switch *ds)
	1696	+{
	1697	+ struct mt7530_priv *priv = ds->priv;
	1698	+ struct mt7530_dummy_poll p;
	1699	+ u32 val, id;
	1700	+ int ret, i;
	1701	+
	1702	+ /* Reset whole chip through gpio pin or memory-mapped registers for
	1703	+ * different type of hardware
	1704	+ */
	1705	+ if (priv->mcm) {
	1706	+ reset_control_assert(priv->rstc);
	1707	+ usleep_range(1000, 1100);
	1708	+ reset_control_deassert(priv->rstc);
	1709	+ } else {
	1710	+ gpiod_set_value_cansleep(priv->reset, 0);
	1711	+ usleep_range(1000, 1100);
	1712	+ gpiod_set_value_cansleep(priv->reset, 1);
	1713	+ }
	1714	+
	1715	+ /* Waiting for MT7530 got to stable */
	1716	+ INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
	1717	+ ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
	1718	+ 20, 1000000);
	1719	+ if (ret < 0) {
	1720	+ dev_err(priv->dev, "reset timeout\n");
	1721	+ return ret;
	1722	+ }
	1723	+
	1724	+ id = mt7530_read(priv, MT7531_CREV);
	1725	+ id >>= CHIP_NAME_SHIFT;
	1726	+
	1727	+ if (id != MT7531_ID) {
	1728	+ dev_err(priv->dev, "chip %x can't be supported\n", id);
	1729	+ return -ENODEV;
	1730	+ }
	1731	+
	1732	+ /* Reset the switch through internal reset */
	1733	+ mt7530_write(priv, MT7530_SYS_CTRL,
	1734	+ SYS_CTRL_PHY_RST \| SYS_CTRL_SW_RST \|
	1735	+ SYS_CTRL_REG_RST);
	1736	+
	1737	+ mt7531_pll_setup(priv);
	1738	+
	1739	+ if (mt7531_dual_sgmii_supported(priv)) {
	1740	+ priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
	1741	+
	1742	+ /* Let ds->slave_mii_bus be able to access external phy. */
	1743	+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
	1744	+ MT7531_EXT_P_MDC_11);
	1745	+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
	1746	+ MT7531_EXT_P_MDIO_12);
	1747	+ } else {
	1748	+ priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
	1749	+ }
	1750	+ dev_dbg(ds->dev, "P5 support %s interface\n",
	1751	+ p5_intf_modes(priv->p5_intf_sel));
	1752	+
	1753	+ mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
	1754	+ MT7531_GPIO0_INTERRUPT);
	1755	+
	1756	+ /* Let phylink decide the interface later. */
	1757	+ priv->p5_interface = PHY_INTERFACE_MODE_NA;
	1758	+ priv->p6_interface = PHY_INTERFACE_MODE_NA;
	1759	+
	1760	+ /* Enable PHY core PLL, since phy_device has not yet been created
	1761	+ * provided for phy_[read,write]_mmd_indirect is called, we provide
	1762	+ * our own mt7531_ind_mmd_phy_[read,write] to complete this
	1763	+ * function.
	1764	+ */
	1765	+ val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
	1766	+ MDIO_MMD_VEND2, CORE_PLL_GROUP4);
	1767	+ val \|= MT7531_PHY_PLL_BYPASS_MODE;
	1768	+ val &= ~MT7531_PHY_PLL_OFF;
	1769	+ mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
	1770	+ CORE_PLL_GROUP4, val);
	1771	+
	1772	+ /* BPDU to CPU port */
	1773	+ mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
	1774	+ BIT(MT7530_CPU_PORT));
	1775	+ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
	1776	+ MT753X_BPDU_CPU_ONLY);
	1777	+
	1778	+ /* Enable and reset MIB counters */
	1779	+ mt7530_mib_reset(ds);
	1780	+
	1781	+ for (i = 0; i < MT7530_NUM_PORTS; i++) {
	1782	+ /* Disable forwarding by default on all ports */
	1783	+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
	1784	+ PCR_MATRIX_CLR);
	1785	+
	1786	+ mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
	1787	+
	1788	+ if (dsa_is_cpu_port(ds, i)) {
	1789	+ ret = mt753x_cpu_port_enable(ds, i);
	1790	+ if (ret)
	1791	+ return ret;
	1792	+ } else
	1793	+ mt7530_port_disable(ds, i);
	1794	+
	1795	+ /* Enable consistent egress tag */
	1796	+ mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
	1797	+ PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
	1798	+ }
	1799	+
	1800	+ ds->configure_vlan_while_not_filtering = true;
	1801	+
	1802	+ /* Flush the FDB table */
	1803	+ ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
	1804	+ if (ret < 0)
	1805	+ return ret;
	1806	+
	1807	+ return 0;
	1808	+}
	1809	+
	1810	+static bool
	1811	+mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
	1812	+ const struct phylink_link_state *state)
	1813	+{
	1814	+ struct mt7530_priv *priv = ds->priv;
	1815	+
	1816	+ switch (port) {
	1817	+ case 0 ... 4: /* Internal phy */
	1818	+ if (state->interface != PHY_INTERFACE_MODE_GMII)
	1819	+ return false;
	1820	+ break;
	1821	+ case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
	1822	+ if (!phy_interface_mode_is_rgmii(state->interface) &&
	1823	+ state->interface != PHY_INTERFACE_MODE_MII &&
	1824	+ state->interface != PHY_INTERFACE_MODE_GMII)
	1825	+ return false;
	1826	+ break;
	1827	+ case 6: /* 1st cpu port */
	1828	+ if (state->interface != PHY_INTERFACE_MODE_RGMII &&
	1829	+ state->interface != PHY_INTERFACE_MODE_TRGMII)
	1830	+ return false;
	1831	+ break;
	1832	+ default:
	1833	+ dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
	1834	+ port);
	1835	+ return false;
	1836	+ }
	1837	+
	1838	+ return true;
	1839	+}
	1840	+
	1841	+static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
	1842	+{
	1843	+ return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
	1844	+}
	1845	+
	1846	+static bool
	1847	+mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
	1848	+ const struct phylink_link_state *state)
	1849	+{
	1850	+ struct mt7530_priv *priv = ds->priv;
	1851	+
	1852	+ switch (port) {
	1853	+ case 0 ... 4: /* Internal phy */
	1854	+ if (state->interface != PHY_INTERFACE_MODE_GMII)
	1855	+ return false;
	1856	+ break;
	1857	+ case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
	1858	+ if (mt7531_is_rgmii_port(priv, port))
	1859	+ return phy_interface_mode_is_rgmii(state->interface);
	1860	+ fallthrough;
	1861	+ case 6: /* 1st cpu port supports sgmii/8023z only */
	1862	+ if (state->interface != PHY_INTERFACE_MODE_SGMII &&
	1863	+ !phy_interface_mode_is_8023z(state->interface))
	1864	+ return false;
	1865	+ break;
	1866	+ default:
	1867	+ dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
	1868	+ port);
	1869	+ return false;
	1870	+ }
	1871	+
	1872	+ return true;
	1873	+}
	1874	+
	1875	+static bool
	1876	+mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
	1877	+ const struct phylink_link_state *state)
	1878	+{
	1879	+ struct mt7530_priv *priv = ds->priv;
	1880	+
	1881	+ return priv->info->phy_mode_supported(ds, port, state);
	1882	+}
	1883	+
	1884	+static int
	1885	+mt753x_pad_setup(struct dsa_switch ds, const struct phylink_link_state state)
	1886	+{
	1887	+ struct mt7530_priv *priv = ds->priv;
	1888	+
	1889	+ return priv->info->pad_setup(ds, state->interface);
	1890	+}
	1891	+
	1892	+static int
	1893	+mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
	1894	+ phy_interface_t interface)
	1895	+{
	1896	+ struct mt7530_priv *priv = ds->priv;
	1897	+
	1898	+ /* Only need to setup port5. */
	1899	+ if (port != 5)
	1900	+ return 0;
	1901	+
	1902	+ mt7530_setup_port5(priv->ds, interface);
	1903	+
	1904	+ return 0;
	1905	+}
	1906	+
	1907	+static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
	1908	+ phy_interface_t interface,
	1909	+ struct phy_device *phydev)
	1910	+{
	1911	+ u32 val;
	1912	+
	1913	+ if (!mt7531_is_rgmii_port(priv, port)) {
	1914	+ dev_err(priv->dev, "RGMII mode is not available for port %d\n",
	1915	+ port);
	1916	+ return -EINVAL;
	1917	+ }
	1918	+
	1919	+ val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
	1920	+ val \|= GP_CLK_EN;
	1921	+ val &= ~GP_MODE_MASK;
	1922	+ val \|= GP_MODE(MT7531_GP_MODE_RGMII);
	1923	+ val &= ~CLK_SKEW_IN_MASK;
	1924	+ val \|= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
	1925	+ val &= ~CLK_SKEW_OUT_MASK;
	1926	+ val \|= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
	1927	+ val \|= TXCLK_NO_REVERSE \| RXCLK_NO_DELAY;
	1928	+
	1929	+ /* Do not adjust rgmii delay when vendor phy driver presents. */
	1930	+ if (!phydev \|\| phy_driver_is_genphy(phydev)) {
	1931	+ val &= ~(TXCLK_NO_REVERSE \| RXCLK_NO_DELAY);
	1932	+ switch (interface) {
	1933	+ case PHY_INTERFACE_MODE_RGMII:
	1934	+ val \|= TXCLK_NO_REVERSE;
	1935	+ val \|= RXCLK_NO_DELAY;
	1936	+ break;
	1937	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	1938	+ val \|= TXCLK_NO_REVERSE;
	1939	+ break;
	1940	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	1941	+ val \|= RXCLK_NO_DELAY;
	1942	+ break;
	1943	+ case PHY_INTERFACE_MODE_RGMII_ID:
	1944	+ break;
	1945	+ default:
	1946	+ return -EINVAL;
	1947	+ }
	1948	+ }
	1949	+ mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
	1950	+
	1951	+ return 0;
	1952	+}
	1953	+
	1954	+static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
	1955	+ unsigned long *supported)
	1956	+{
	1957	+ /* Port5 supports ethier RGMII or SGMII.
	1958	+ * Port6 supports SGMII only.
	1959	+ */
	1960	+ if (port == 6) {
	1961	+ phylink_set(supported, 2500baseX_Full);
	1962	+ phylink_set(supported, 2500baseT_Full);
	1963	+ }
	1964	+}
	1965	+
	1966	+static void
	1967	+mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
	1968	+ unsigned int mode, phy_interface_t interface,
	1969	+ int speed, int duplex)
	1970	+{
	1971	+ struct mt7530_priv *priv = ds->priv;
	1972	+ unsigned int val;
	1973	+
	1974	+ /* For adjusting speed and duplex of SGMII force mode. */
	1975	+ if (interface != PHY_INTERFACE_MODE_SGMII \|\|
	1976	+ phylink_autoneg_inband(mode))
	1977	+ return;
	1978	+
	1979	+ /* SGMII force mode setting */
	1980	+ val = mt7530_read(priv, MT7531_SGMII_MODE(port));
	1981	+ val &= ~MT7531_SGMII_IF_MODE_MASK;
	1982	+
	1983	+ switch (speed) {
	1984	+ case SPEED_10:
	1985	+ val \|= MT7531_SGMII_FORCE_SPEED_10;
	1986	+ break;
	1987	+ case SPEED_100:
	1988	+ val \|= MT7531_SGMII_FORCE_SPEED_100;
	1989	+ break;
	1990	+ case SPEED_1000:
	1991	+ val \|= MT7531_SGMII_FORCE_SPEED_1000;
	1992	+ break;
	1993	+ }
	1994	+
	1995	+ /* MT7531 SGMII 1G force mode can only work in full duplex mode,
	1996	+ * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
	1997	+ */
	1998	+ if ((speed == SPEED_10 \|\| speed == SPEED_100) &&
	1999	+ duplex != DUPLEX_FULL)
	2000	+ val \|= MT7531_SGMII_FORCE_HALF_DUPLEX;
	2001	+
	2002	+ mt7530_write(priv, MT7531_SGMII_MODE(port), val);
	2003	+}
	2004	+
	2005	+static bool mt753x_is_mac_port(u32 port)
	2006	+{
	2007	+ return (port == 5 \|\| port == 6);
	2008	+}
	2009	+
	2010	+static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
	2011	+ phy_interface_t interface)
	2012	+{
	2013	+ u32 val;
	2014	+
	2015	+ if (!mt753x_is_mac_port(port))
	2016	+ return -EINVAL;
	2017	+
	2018	+ mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
	2019	+ MT7531_SGMII_PHYA_PWD);
	2020	+
	2021	+ val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
	2022	+ val &= ~MT7531_RG_TPHY_SPEED_MASK;
	2023	+ /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
	2024	+ * encoding.
	2025	+ */
	2026	+ val \|= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
	2027	+ MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
	2028	+ mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
	2029	+
	2030	+ mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
	2031	+
	2032	+ /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
	2033	+ * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
	2034	+ */
	2035	+ mt7530_rmw(priv, MT7531_SGMII_MODE(port),
	2036	+ MT7531_SGMII_IF_MODE_MASK \| MT7531_SGMII_REMOTE_FAULT_DIS,
	2037	+ MT7531_SGMII_FORCE_SPEED_1000);
	2038	+
	2039	+ mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
	2040	+
	2041	+ return 0;
	2042	+}
	2043	+
	2044	+static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
	2045	+ phy_interface_t interface)
	2046	+{
	2047	+ if (!mt753x_is_mac_port(port))
	2048	+ return -EINVAL;
	2049	+
	2050	+ mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
	2051	+ MT7531_SGMII_PHYA_PWD);
	2052	+
	2053	+ mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
	2054	+ MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
	2055	+
	2056	+ mt7530_set(priv, MT7531_SGMII_MODE(port),
	2057	+ MT7531_SGMII_REMOTE_FAULT_DIS \|
	2058	+ MT7531_SGMII_SPEED_DUPLEX_AN);
	2059	+
	2060	+ mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
	2061	+ MT7531_SGMII_TX_CONFIG_MASK, 1);
	2062	+
	2063	+ mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
	2064	+
	2065	+ mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
	2066	+
	2067	+ mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
	2068	+
	2069	+ return 0;
	2070	+}
	2071	+
	2072	+static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
	2073	+{
	2074	+ struct mt7530_priv *priv = ds->priv;
	2075	+ u32 val;
	2076	+
	2077	+ /* Only restart AN when AN is enabled */
	2078	+ val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
	2079	+ if (val & MT7531_SGMII_AN_ENABLE) {
	2080	+ val \|= MT7531_SGMII_AN_RESTART;
	2081	+ mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
	2082	+ }
	2083	+}
	2084	+
	2085	+static int
	2086	+mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
	2087	+ phy_interface_t interface)
	2088	+{
	2089	+ struct mt7530_priv *priv = ds->priv;
	2090	+ struct phy_device *phydev;
	2091	+ struct dsa_port *dp;
	2092	+
	2093	+ if (!mt753x_is_mac_port(port)) {
	2094	+ dev_err(priv->dev, "port %d is not a MAC port\n", port);
	2095	+ return -EINVAL;
	2096	+ }
	2097	+
	2098	+ switch (interface) {
	2099	+ case PHY_INTERFACE_MODE_RGMII:
	2100	+ case PHY_INTERFACE_MODE_RGMII_ID:
	2101	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	2102	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	2103	+ dp = dsa_to_port(ds, port);
	2104	+ phydev = dp->slave->phydev;
	2105	+ return mt7531_rgmii_setup(priv, port, interface, phydev);
	2106	+ case PHY_INTERFACE_MODE_SGMII:
	2107	+ return mt7531_sgmii_setup_mode_an(priv, port, interface);
	2108	+ case PHY_INTERFACE_MODE_NA:
	2109	+ case PHY_INTERFACE_MODE_1000BASEX:
	2110	+ case PHY_INTERFACE_MODE_2500BASEX:
	2111	+ if (phylink_autoneg_inband(mode))
	2112	+ return -EINVAL;
	2113	+
	2114	+ return mt7531_sgmii_setup_mode_force(priv, port, interface);
	2115	+ default:
	2116	+ return -EINVAL;
	2117	+ }
	2118	+
	2119	+ return -EINVAL;
	2120	+}
	2121	+
	2122	+static int
	2123	+mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
	2124	+ const struct phylink_link_state *state)
	2125	+{
	2126	+ struct mt7530_priv *priv = ds->priv;
	2127	+
	2128	+ return priv->info->mac_port_config(ds, port, mode, state->interface);
	2129	+}
	2130	+
	2131	+static void
	2132	+mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
	2133	+ const struct phylink_link_state *state)
	2134	+{
	2135	+ struct mt7530_priv *priv = ds->priv;
	2136	+ u32 mcr_cur, mcr_new;
	2137	+
	2138	+ if (!mt753x_phy_mode_supported(ds, port, state))
	2139	+ goto unsupported;
	2140	+
	2141	+ switch (port) {
	2142	+ case 0 ... 4: /* Internal phy */
	2143	+ if (state->interface != PHY_INTERFACE_MODE_GMII)
	2144	+ goto unsupported;
	2145	+ break;
	2146	+ case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
	2147	+ if (priv->p5_interface == state->interface)
	2148	+ break;
	2149	+
	2150	+ if (mt753x_mac_config(ds, port, mode, state) < 0)
	2151	+ goto unsupported;
	2152	+
	2153	+ if (priv->p5_intf_sel != P5_DISABLED)
	2154	+ priv->p5_interface = state->interface;
	2155	+ break;
	2156	+ case 6: /* 1st cpu port */
	2157	+ if (priv->p6_interface == state->interface)
	2158	+ break;
	2159	+
	2160	+ mt753x_pad_setup(ds, state);
	2161	+
	2162	+ if (mt753x_mac_config(ds, port, mode, state) < 0)
	2163	+ goto unsupported;
	2164	+
	2165	+ priv->p6_interface = state->interface;
	2166	+ break;
	2167	+ default:
	2168	+unsupported:
	2169	+ dev_err(ds->dev, "%s: unsupported %s port: %i\n",
	2170	+ __func__, phy_modes(state->interface), port);
	2171	+ return;
	2172	+ }
	2173	+
	2174	+ if (phylink_autoneg_inband(mode) &&
	2175	+ state->interface != PHY_INTERFACE_MODE_SGMII) {
	2176	+ dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
	2177	+ __func__);
	2178	+ return;
	2179	+ }
	2180	+
	2181	+ mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
	2182	+ mcr_new = mcr_cur;
	2183	+ mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
	2184	+ mcr_new \|= PMCR_IFG_XMIT(1) \| PMCR_MAC_MODE \| PMCR_BACKOFF_EN \|
	2185	+ PMCR_BACKPR_EN \| PMCR_FORCE_MODE_ID(priv->id);
	2186	+
	2187	+ /* Are we connected to external phy */
	2188	+ if (port == 5 && dsa_is_user_port(ds, 5))
	2189	+ mcr_new \|= PMCR_EXT_PHY;
	2190	+
	2191	+ if (mcr_new != mcr_cur)
	2192	+ mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
	2193	+}
	2194	+
	2195	+static void
	2196	+mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
	2197	+{
	2198	+ struct mt7530_priv *priv = ds->priv;
	2199	+
	2200	+ if (!priv->info->mac_pcs_an_restart)
	2201	+ return;
	2202	+
	2203	+ priv->info->mac_pcs_an_restart(ds, port);
	2204	+}
	2205	+
	2206	+static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
	2207	+ unsigned int mode,
	2208	+ phy_interface_t interface)
	2209	+{
	2210	+ struct mt7530_priv *priv = ds->priv;
	2211	+
	2212	+ mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
	2213	+}
	2214	+
	2215	+static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
	2216	+ unsigned int mode, phy_interface_t interface,
	2217	+ int speed, int duplex)
	2218	+{
	2219	+ struct mt7530_priv *priv = ds->priv;
	2220	+
	2221	+ if (!priv->info->mac_pcs_link_up)
	2222	+ return;
	2223	+
	2224	+ priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
	2225	+}
	2226	+
	2227	+static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
	2228	+ unsigned int mode,
	2229	+ phy_interface_t interface,
	2230	+ struct phy_device *phydev,
	2231	+ int speed, int duplex,
	2232	+ bool tx_pause, bool rx_pause)
	2233	+{
	2234	+ struct mt7530_priv *priv = ds->priv;
	2235	+ u32 mcr;
	2236	+
	2237	+ mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
	2238	+
	2239	+ mcr = PMCR_RX_EN \| PMCR_TX_EN \| PMCR_FORCE_LNK;
	2240	+
	2241	+ /* MT753x MAC works in 1G full duplex mode for all up-clocked
	2242	+ * variants.
	2243	+ */
	2244	+ if (interface == PHY_INTERFACE_MODE_TRGMII \|\|
	2245	+ (phy_interface_mode_is_8023z(interface))) {
	2246	+ speed = SPEED_1000;
	2247	+ duplex = DUPLEX_FULL;
	2248	+ }
	2249	+
	2250	+ switch (speed) {
	2251	+ case SPEED_1000:
	2252	+ mcr \|= PMCR_FORCE_SPEED_1000;
	2253	+ break;
	2254	+ case SPEED_100:
	2255	+ mcr \|= PMCR_FORCE_SPEED_100;
	2256	+ break;
	2257	+ }
	2258	+ if (duplex == DUPLEX_FULL) {
	2259	+ mcr \|= PMCR_FORCE_FDX;
	2260	+ if (tx_pause)
	2261	+ mcr \|= PMCR_TX_FC_EN;
	2262	+ if (rx_pause)
	2263	+ mcr \|= PMCR_RX_FC_EN;
	2264	+ }
	2265	+
	2266	+ mt7530_set(priv, MT7530_PMCR_P(port), mcr);
	2267	+}
	2268	+
	2269	+static int
	2270	+mt7531_cpu_port_config(struct dsa_switch *ds, int port)
	2271	+{
	2272	+ struct mt7530_priv *priv = ds->priv;
	2273	+ phy_interface_t interface;
	2274	+ int speed;
	2275	+ int ret;
	2276	+
	2277	+ switch (port) {
	2278	+ case 5:
	2279	+ if (mt7531_is_rgmii_port(priv, port))
	2280	+ interface = PHY_INTERFACE_MODE_RGMII;
	2281	+ else
	2282	+ interface = PHY_INTERFACE_MODE_2500BASEX;
	2283	+
	2284	+ priv->p5_interface = interface;
	2285	+ break;
	2286	+ case 6:
	2287	+ interface = PHY_INTERFACE_MODE_2500BASEX;
	2288	+
	2289	+ priv->p6_interface = interface;
	2290	+ break;
	2291	+ default:
	2292	+ return -EINVAL;
	2293	+ }
	2294	+
	2295	+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
	2296	+ speed = SPEED_2500;
	2297	+ else
	2298	+ speed = SPEED_1000;
	2299	+
	2300	+ ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
	2301	+ if (ret)
	2302	+ return ret;
	2303	+ mt7530_write(priv, MT7530_PMCR_P(port),
	2304	+ PMCR_CPU_PORT_SETTING(priv->id));
	2305	+ mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
	2306	+ speed, DUPLEX_FULL, true, true);
	2307	+
	2308	+ return 0;
	2309	+}
	2310	+
	2311	+static void
	2312	+mt7530_mac_port_validate(struct dsa_switch *ds, int port,
	2313	+ unsigned long *supported)
	2314	+{
	2315	+}
	2316	+
	2317	+static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
	2318	+ unsigned long *supported)
	2319	+{
	2320	+ struct mt7530_priv *priv = ds->priv;
	2321	+
	2322	+ mt7531_sgmii_validate(priv, port, supported);
	2323	+}
	2324	+
	2325	+static void
	2326	+mt753x_phylink_validate(struct dsa_switch *ds, int port,
	2327	+ unsigned long *supported,
	2328	+ struct phylink_link_state *state)
	2329	+{
	2330	+ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
	2331	+ struct mt7530_priv *priv = ds->priv;
	2332	+
	2333	+ if (state->interface != PHY_INTERFACE_MODE_NA &&
	2334	+ !mt753x_phy_mode_supported(ds, port, state)) {
	2335	+ linkmode_zero(supported);
	2336	+ return;
	2337	+ }
	2338	+
	2339	+ phylink_set_port_modes(mask);
	2340	+
	2341	+ if (state->interface != PHY_INTERFACE_MODE_TRGMII &&
	2342	+ !phy_interface_mode_is_8023z(state->interface)) {
	2343	+ phylink_set(mask, 10baseT_Half);
	2344	+ phylink_set(mask, 10baseT_Full);
	2345	+ phylink_set(mask, 100baseT_Half);
	2346	+ phylink_set(mask, 100baseT_Full);
	2347	+ phylink_set(mask, Autoneg);
	2348	+ }
	2349	+
	2350	+ /* This switch only supports 1G full-duplex. */
	2351	+ if (state->interface != PHY_INTERFACE_MODE_MII) {
	2352	+ phylink_set(mask, 1000baseT_Full);
	2353	+ phylink_set(mask, 1000baseX_Full);
	2354	+ }
	2355	+
	2356	+ priv->info->mac_port_validate(ds, port, mask);
	2357	+
	2358	+ phylink_set(mask, Pause);
	2359	+ phylink_set(mask, Asym_Pause);
	2360	+
	2361	+ linkmode_and(supported, supported, mask);
	2362	+ linkmode_and(state->advertising, state->advertising, mask);
	2363	+
	2364	+ /* We can only operate at 2500BaseX or 1000BaseX. If requested
	2365	+ * to advertise both, only report advertising at 2500BaseX.
	2366	+ */
	2367	+ phylink_helper_basex_speed(state);
	2368	+}
	2369	+
	2370	+static int
	2371	+mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
	2372	+ struct phylink_link_state *state)
	2373	+{
	2374	+ struct mt7530_priv *priv = ds->priv;
	2375	+ u32 pmsr;
	2376	+
	2377	+ if (port < 0 \|\| port >= MT7530_NUM_PORTS)
	2378	+ return -EINVAL;
	2379	+
	2380	+ pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
	2381	+
	2382	+ state->link = (pmsr & PMSR_LINK);
	2383	+ state->an_complete = state->link;
	2384	+ state->duplex = !!(pmsr & PMSR_DPX);
	2385	+
	2386	+ switch (pmsr & PMSR_SPEED_MASK) {
	2387	+ case PMSR_SPEED_10:
	2388	+ state->speed = SPEED_10;
	2389	+ break;
	2390	+ case PMSR_SPEED_100:
	2391	+ state->speed = SPEED_100;
	2392	+ break;
	2393	+ case PMSR_SPEED_1000:
	2394	+ state->speed = SPEED_1000;
	2395	+ break;
	2396	+ default:
	2397	+ state->speed = SPEED_UNKNOWN;
	2398	+ break;
	2399	+ }
	2400	+
	2401	+ state->pause &= ~(MLO_PAUSE_RX \| MLO_PAUSE_TX);
	2402	+ if (pmsr & PMSR_RX_FC)
	2403	+ state->pause \|= MLO_PAUSE_RX;
	2404	+ if (pmsr & PMSR_TX_FC)
	2405	+ state->pause \|= MLO_PAUSE_TX;
	2406	+
	2407	+ return 1;
	2408	+}
	2409	+
	2410	+static int
	2411	+mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
	2412	+ struct phylink_link_state *state)
	2413	+{
	2414	+ u32 status, val;
	2415	+ u16 config_reg;
	2416	+
	2417	+ status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
	2418	+ state->link = !!(status & MT7531_SGMII_LINK_STATUS);
	2419	+ if (state->interface == PHY_INTERFACE_MODE_SGMII &&
	2420	+ (status & MT7531_SGMII_AN_ENABLE)) {
	2421	+ val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
	2422	+ config_reg = val >> 16;
	2423	+
	2424	+ switch (config_reg & LPA_SGMII_SPD_MASK) {
	2425	+ case LPA_SGMII_1000:
	2426	+ state->speed = SPEED_1000;
	2427	+ break;
	2428	+ case LPA_SGMII_100:
	2429	+ state->speed = SPEED_100;
	2430	+ break;
	2431	+ case LPA_SGMII_10:
	2432	+ state->speed = SPEED_10;
	2433	+ break;
	2434	+ default:
	2435	+ dev_err(priv->dev, "invalid sgmii PHY speed\n");
	2436	+ state->link = false;
	2437	+ return -EINVAL;
	2438	+ }
	2439	+
	2440	+ if (config_reg & LPA_SGMII_FULL_DUPLEX)
	2441	+ state->duplex = DUPLEX_FULL;
	2442	+ else
	2443	+ state->duplex = DUPLEX_HALF;
	2444	+ }
	2445	+
	2446	+ return 0;
	2447	+}
	2448	+
	2449	+static int
	2450	+mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
	2451	+ struct phylink_link_state *state)
	2452	+{
	2453	+ struct mt7530_priv *priv = ds->priv;
	2454	+
	2455	+ if (state->interface == PHY_INTERFACE_MODE_SGMII)
	2456	+ return mt7531_sgmii_pcs_get_state_an(priv, port, state);
	2457	+
	2458	+ return -EOPNOTSUPP;
	2459	+}
	2460	+
	2461	+static int
	2462	+mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
	2463	+ struct phylink_link_state *state)
	2464	+{
	2465	+ struct mt7530_priv *priv = ds->priv;
	2466	+
	2467	+ return priv->info->mac_port_get_state(ds, port, state);
	2468	+}
	2469	+
	2470	+static int
	2471	+mt753x_setup(struct dsa_switch *ds)
	2472	+{
	2473	+ struct mt7530_priv *priv = ds->priv;
	2474	+
	2475	+ return priv->info->sw_setup(ds);
	2476	+}
	2477	+
	2478	+static int
	2479	+mt753x_phy_read(struct dsa_switch *ds, int port, int regnum)
	2480	+{
	2481	+ struct mt7530_priv *priv = ds->priv;
	2482	+
	2483	+ return priv->info->phy_read(ds, port, regnum);
	2484	+}
	2485	+
	2486	+static int
	2487	+mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
	2488	+{
	2489	+ struct mt7530_priv *priv = ds->priv;
	2490	+
	2491	+ return priv->info->phy_write(ds, port, regnum, val);
	2492	+}
	2493	+
1309	2494	static const struct dsa_switch_ops mt7530_switch_ops = {
1310	2495	.get_tag_protocol = mtk_get_tag_protocol,
1311		- .setup = mt7530_setup,
	2496	+ .setup = mt753x_setup,
1312	2497	.get_strings = mt7530_get_strings,
1313		- .phy_read = mt7530_phy_read,
1314		- .phy_write = mt7530_phy_write,
	2498	+ .phy_read = mt753x_phy_read,
	2499	+ .phy_write = mt753x_phy_write,
1315	2500	.get_ethtool_stats = mt7530_get_ethtool_stats,
1316	2501	.get_sset_count = mt7530_get_sset_count,
1317		- .adjust_link = mt7530_adjust_link,
1318	2502	.port_enable = mt7530_port_enable,
1319	2503	.port_disable = mt7530_port_disable,
1320	2504	.port_stp_state_set = mt7530_stp_state_set,
..	..	@@ -1327,7 +2511,62 @@
1327	2511	.port_vlan_prepare = mt7530_port_vlan_prepare,
1328	2512	.port_vlan_add = mt7530_port_vlan_add,
1329	2513	.port_vlan_del = mt7530_port_vlan_del,
	2514	+ .port_mirror_add = mt753x_port_mirror_add,
	2515	+ .port_mirror_del = mt753x_port_mirror_del,
	2516	+ .phylink_validate = mt753x_phylink_validate,
	2517	+ .phylink_mac_link_state = mt753x_phylink_mac_link_state,
	2518	+ .phylink_mac_config = mt753x_phylink_mac_config,
	2519	+ .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
	2520	+ .phylink_mac_link_down = mt753x_phylink_mac_link_down,
	2521	+ .phylink_mac_link_up = mt753x_phylink_mac_link_up,
1330	2522	};
	2523	+
	2524	+static const struct mt753x_info mt753x_table[] = {
	2525	+ [ID_MT7621] = {
	2526	+ .id = ID_MT7621,
	2527	+ .sw_setup = mt7530_setup,
	2528	+ .phy_read = mt7530_phy_read,
	2529	+ .phy_write = mt7530_phy_write,
	2530	+ .pad_setup = mt7530_pad_clk_setup,
	2531	+ .phy_mode_supported = mt7530_phy_mode_supported,
	2532	+ .mac_port_validate = mt7530_mac_port_validate,
	2533	+ .mac_port_get_state = mt7530_phylink_mac_link_state,
	2534	+ .mac_port_config = mt7530_mac_config,
	2535	+ },
	2536	+ [ID_MT7530] = {
	2537	+ .id = ID_MT7530,
	2538	+ .sw_setup = mt7530_setup,
	2539	+ .phy_read = mt7530_phy_read,
	2540	+ .phy_write = mt7530_phy_write,
	2541	+ .pad_setup = mt7530_pad_clk_setup,
	2542	+ .phy_mode_supported = mt7530_phy_mode_supported,
	2543	+ .mac_port_validate = mt7530_mac_port_validate,
	2544	+ .mac_port_get_state = mt7530_phylink_mac_link_state,
	2545	+ .mac_port_config = mt7530_mac_config,
	2546	+ },
	2547	+ [ID_MT7531] = {
	2548	+ .id = ID_MT7531,
	2549	+ .sw_setup = mt7531_setup,
	2550	+ .phy_read = mt7531_ind_phy_read,
	2551	+ .phy_write = mt7531_ind_phy_write,
	2552	+ .pad_setup = mt7531_pad_setup,
	2553	+ .cpu_port_config = mt7531_cpu_port_config,
	2554	+ .phy_mode_supported = mt7531_phy_mode_supported,
	2555	+ .mac_port_validate = mt7531_mac_port_validate,
	2556	+ .mac_port_get_state = mt7531_phylink_mac_link_state,
	2557	+ .mac_port_config = mt7531_mac_config,
	2558	+ .mac_pcs_an_restart = mt7531_sgmii_restart_an,
	2559	+ .mac_pcs_link_up = mt7531_sgmii_link_up_force,
	2560	+ },
	2561	+};
	2562	+
	2563	+static const struct of_device_id mt7530_of_match[] = {
	2564	+ { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
	2565	+ { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
	2566	+ { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
	2567	+ { /* sentinel */ },
	2568	+};
	2569	+MODULE_DEVICE_TABLE(of, mt7530_of_match);
1331	2570
1332	2571	static int
1333	2572	mt7530_probe(struct mdio_device *mdiodev)
..	..	@@ -1341,9 +2580,12 @@
1341	2580	if (!priv)
1342	2581	return -ENOMEM;
1343	2582
1344		- priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
	2583	+ priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
1345	2584	if (!priv->ds)
1346	2585	return -ENOMEM;
	2586	+
	2587	+ priv->ds->dev = &mdiodev->dev;
	2588	+ priv->ds->num_ports = MT7530_NUM_PORTS;
1347	2589
1348	2590	/* Use medatek,mcm property to distinguish hardware type that would
1349	2591	* casues a little bit differences on power-on sequence.
..	..	@@ -1359,13 +2601,34 @@
1359	2601	}
1360	2602	}
1361	2603
1362		- priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1363		- if (IS_ERR(priv->core_pwr))
1364		- return PTR_ERR(priv->core_pwr);
	2604	+ /* Get the hardware identifier from the devicetree node.
	2605	+ * We will need it for some of the clock and regulator setup.
	2606	+ */
	2607	+ priv->info = of_device_get_match_data(&mdiodev->dev);
	2608	+ if (!priv->info)
	2609	+ return -EINVAL;
1365	2610
1366		- priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1367		- if (IS_ERR(priv->io_pwr))
1368		- return PTR_ERR(priv->io_pwr);
	2611	+ /* Sanity check if these required device operations are filled
	2612	+ * properly.
	2613	+ */
	2614	+ if (!priv->info->sw_setup \|\| !priv->info->pad_setup \|\|
	2615	+ !priv->info->phy_read \|\| !priv->info->phy_write \|\|
	2616	+ !priv->info->phy_mode_supported \|\|
	2617	+ !priv->info->mac_port_validate \|\|
	2618	+ !priv->info->mac_port_get_state \|\| !priv->info->mac_port_config)
	2619	+ return -EINVAL;
	2620	+
	2621	+ priv->id = priv->info->id;
	2622	+
	2623	+ if (priv->id == ID_MT7530) {
	2624	+ priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
	2625	+ if (IS_ERR(priv->core_pwr))
	2626	+ return PTR_ERR(priv->core_pwr);
	2627	+
	2628	+ priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
	2629	+ if (IS_ERR(priv->io_pwr))
	2630	+ return PTR_ERR(priv->io_pwr);
	2631	+ }
1369	2632
1370	2633	/* Not MCM that indicates switch works as the remote standalone
1371	2634	* integrated circuit so the GPIO pin would be used to complete
..	..	@@ -1410,12 +2673,6 @@
1410	2673	dsa_unregister_switch(priv->ds);
1411	2674	mutex_destroy(&priv->reg_mutex);
1412	2675	}
1413		-
1414		-static const struct of_device_id mt7530_of_match[] = {
1415		- { .compatible = "mediatek,mt7530" },
1416		- { /* sentinel */ },
1417		-};
1418		-MODULE_DEVICE_TABLE(of, mt7530_of_match);
1419	2676
1420	2677	static struct mdio_driver mt7530_mdio_driver = {
1421	2678	.probe = mt7530_probe,