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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/mmc/host/sdhci-of-at91.c
....@@ -1,23 +1,17 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Atmel SDMMC controller driver.
34  *
45  * Copyright (C) 2015 Atmel,
56  *		 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6
- *
7
- * This software is licensed under the terms of the GNU General Public
8
- * License version 2, as published by the Free Software Foundation, and
9
- * may be copied, distributed, and modified under those terms.
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
- * GNU General Public License for more details.
157  */
168 
9
+#include <linux/bitfield.h>
1710 #include <linux/clk.h>
1811 #include <linux/delay.h>
1912 #include <linux/err.h>
2013 #include <linux/io.h>
14
+#include <linux/iopoll.h>
2115 #include <linux/kernel.h>
2216 #include <linux/mmc/host.h>
2317 #include <linux/mmc/slot-gpio.h>
....@@ -35,14 +29,25 @@
3529 #define SDMMC_CACR	0x230
3630 #define		SDMMC_CACR_CAPWREN	BIT(0)
3731 #define		SDMMC_CACR_KEY		(0x46 << 8)
32
+#define SDMMC_CALCR	0x240
33
+#define		SDMMC_CALCR_EN		BIT(0)
34
+#define		SDMMC_CALCR_ALWYSON	BIT(4)
3835 
3936 #define SDHCI_AT91_PRESET_COMMON_CONF	0x400 /* drv type B, programmable clock mode */
4037 
38
+struct sdhci_at91_soc_data {
39
+	const struct sdhci_pltfm_data *pdata;
40
+	bool baseclk_is_generated_internally;
41
+	unsigned int divider_for_baseclk;
42
+};
43
+
4144 struct sdhci_at91_priv {
45
+	const struct sdhci_at91_soc_data *soc_data;
4246 	struct clk *hclock;
4347 	struct clk *gck;
4448 	struct clk *mainck;
4549 	bool restore_needed;
50
+	bool cal_always_on;
4651 };
4752 
4853 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
....@@ -57,7 +62,6 @@
5762 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
5863 {
5964 	u16 clk;
60
-	unsigned long timeout;
6165 
6266 	host->mmc->actual_clock = 0;
6367 
....@@ -82,53 +86,52 @@
8286 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
8387 
8488 	/* Wait max 20 ms */
85
-	timeout = 20;
86
-	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
87
-		& SDHCI_CLOCK_INT_STABLE)) {
88
-		if (timeout == 0) {
89
-			pr_err("%s: Internal clock never stabilised.\n",
90
-			       mmc_hostname(host->mmc));
91
-			return;
92
-		}
93
-		timeout--;
94
-		mdelay(1);
89
+	if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE),
90
+			      1000, 20000, false, host, SDHCI_CLOCK_CONTROL)) {
91
+		pr_err("%s: Internal clock never stabilised.\n",
92
+		       mmc_hostname(host->mmc));
93
+		return;
9594 	}
9695 
9796 	clk |= SDHCI_CLOCK_CARD_EN;
9897 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
9998 }
10099 
101
-/*
102
- * In this specific implementation of the SDHCI controller, the power register
103
- * needs to have a valid voltage set even when the power supply is managed by
104
- * an external regulator.
105
- */
106
-static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
107
-		     unsigned short vdd)
108
-{
109
-	if (!IS_ERR(host->mmc->supply.vmmc)) {
110
-		struct mmc_host *mmc = host->mmc;
111
-
112
-		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
113
-	}
114
-	sdhci_set_power_noreg(host, mode, vdd);
115
-}
116
-
117100 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
118101 					 unsigned int timing)
119102 {
120
-	if (timing == MMC_TIMING_MMC_DDR52)
121
-		sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
103
+	u8 mc1r;
104
+
105
+	if (timing == MMC_TIMING_MMC_DDR52) {
106
+		mc1r = sdhci_readb(host, SDMMC_MC1R);
107
+		mc1r |= SDMMC_MC1R_DDR;
108
+		sdhci_writeb(host, mc1r, SDMMC_MC1R);
109
+	}
122110 	sdhci_set_uhs_signaling(host, timing);
123111 }
124112 
125113 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
126114 {
115
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
116
+	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
117
+	unsigned int tmp;
118
+
127119 	sdhci_reset(host, mask);
128120 
129121 	if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
130122 	    || mmc_gpio_get_cd(host->mmc) >= 0)
131123 		sdhci_at91_set_force_card_detect(host);
124
+
125
+	if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) {
126
+		u32 calcr = sdhci_readl(host, SDMMC_CALCR);
127
+
128
+		sdhci_writel(host, calcr | SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN,
129
+			     SDMMC_CALCR);
130
+
131
+		if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN),
132
+				      10, 20000, false, host, SDMMC_CALCR))
133
+			dev_err(mmc_dev(host->mmc), "Failed to calibrate\n");
134
+	}
132135 }
133136 
134137 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
....@@ -136,15 +139,27 @@
136139 	.set_bus_width		= sdhci_set_bus_width,
137140 	.reset			= sdhci_at91_reset,
138141 	.set_uhs_signaling	= sdhci_at91_set_uhs_signaling,
139
-	.set_power		= sdhci_at91_set_power,
142
+	.set_power		= sdhci_set_power_and_bus_voltage,
140143 };
141144 
142
-static const struct sdhci_pltfm_data soc_data_sama5d2 = {
145
+static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = {
143146 	.ops = &sdhci_at91_sama5d2_ops,
147
+};
148
+
149
+static const struct sdhci_at91_soc_data soc_data_sama5d2 = {
150
+	.pdata = &sdhci_sama5d2_pdata,
151
+	.baseclk_is_generated_internally = false,
152
+};
153
+
154
+static const struct sdhci_at91_soc_data soc_data_sam9x60 = {
155
+	.pdata = &sdhci_sama5d2_pdata,
156
+	.baseclk_is_generated_internally = true,
157
+	.divider_for_baseclk = 2,
144158 };
145159 
146160 static const struct of_device_id sdhci_at91_dt_match[] = {
147161 	{ .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
162
+	{ .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 },
148163 	{}
149164 };
150165 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
....@@ -154,50 +169,37 @@
154169 	struct sdhci_host *host = dev_get_drvdata(dev);
155170 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
156171 	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
157
-	int ret;
158172 	unsigned int			caps0, caps1;
159173 	unsigned int			clk_base, clk_mul;
160
-	unsigned int			gck_rate, real_gck_rate;
174
+	unsigned int			gck_rate, clk_base_rate;
161175 	unsigned int			preset_div;
162176 
163
-	/*
164
-	 * The mult clock is provided by as a generated clock by the PMC
165
-	 * controller. In order to set the rate of gck, we have to get the
166
-	 * base clock rate and the clock mult from capabilities.
167
-	 */
168177 	clk_prepare_enable(priv->hclock);
169178 	caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
170179 	caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
171
-	clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
172
-	clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
173
-	gck_rate = clk_base * 1000000 * (clk_mul + 1);
174
-	ret = clk_set_rate(priv->gck, gck_rate);
175
-	if (ret < 0) {
176
-		dev_err(dev, "failed to set gck");
177
-		clk_disable_unprepare(priv->hclock);
178
-		return ret;
179
-	}
180
-	/*
181
-	 * We need to check if we have the requested rate for gck because in
182
-	 * some cases this rate could be not supported. If it happens, the rate
183
-	 * is the closest one gck can provide. We have to update the value
184
-	 * of clk mul.
185
-	 */
186
-	real_gck_rate = clk_get_rate(priv->gck);
187
-	if (real_gck_rate != gck_rate) {
188
-		clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
189
-		caps1 &= (~SDHCI_CLOCK_MUL_MASK);
190
-		caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) &
191
-			  SDHCI_CLOCK_MUL_MASK);
192
-		/* Set capabilities in r/w mode. */
193
-		writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN,
194
-		       host->ioaddr + SDMMC_CACR);
195
-		writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
196
-		/* Set capabilities in ro mode. */
197
-		writel(0, host->ioaddr + SDMMC_CACR);
198
-		dev_info(dev, "update clk mul to %u as gck rate is %u Hz\n",
199
-			 clk_mul, real_gck_rate);
200
-	}
180
+
181
+	gck_rate = clk_get_rate(priv->gck);
182
+	if (priv->soc_data->baseclk_is_generated_internally)
183
+		clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk;
184
+	else
185
+		clk_base_rate = clk_get_rate(priv->mainck);
186
+
187
+	clk_base = clk_base_rate / 1000000;
188
+	clk_mul = gck_rate / clk_base_rate - 1;
189
+
190
+	caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK;
191
+	caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base);
192
+	caps1 &= ~SDHCI_CLOCK_MUL_MASK;
193
+	caps1 |= FIELD_PREP(SDHCI_CLOCK_MUL_MASK, clk_mul);
194
+	/* Set capabilities in r/w mode. */
195
+	writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
196
+	writel(caps0, host->ioaddr + SDHCI_CAPABILITIES);
197
+	writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
198
+	/* Set capabilities in ro mode. */
199
+	writel(0, host->ioaddr + SDMMC_CACR);
200
+
201
+	dev_dbg(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n",
202
+		clk_mul, gck_rate, clk_base_rate);
201203 
202204 	/*
203205 	 * We have to set preset values because it depends on the clk_mul
....@@ -205,19 +207,19 @@
205207 	 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
206208 	 * reason, we need to use presets to support SDR104.
207209 	 */
208
-	preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
210
+	preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1;
209211 	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
210212 	       host->ioaddr + SDHCI_PRESET_FOR_SDR12);
211
-	preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
213
+	preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
212214 	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
213215 	       host->ioaddr + SDHCI_PRESET_FOR_SDR25);
214
-	preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
216
+	preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1;
215217 	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
216218 	       host->ioaddr + SDHCI_PRESET_FOR_SDR50);
217
-	preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
219
+	preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1;
218220 	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
219221 	       host->ioaddr + SDHCI_PRESET_FOR_SDR104);
220
-	preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
222
+	preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
221223 	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
222224 	       host->ioaddr + SDHCI_PRESET_FOR_DDR50);
223225 
....@@ -298,7 +300,7 @@
298300 	}
299301 
300302 out:
301
-	return sdhci_runtime_resume_host(host);
303
+	return sdhci_runtime_resume_host(host, 0);
302304 }
303305 #endif /* CONFIG_PM */
304306 
....@@ -312,7 +314,7 @@
312314 static int sdhci_at91_probe(struct platform_device *pdev)
313315 {
314316 	const struct of_device_id	*match;
315
-	const struct sdhci_pltfm_data	*soc_data;
317
+	const struct sdhci_at91_soc_data	*soc_data;
316318 	struct sdhci_host		*host;
317319 	struct sdhci_pltfm_host		*pltfm_host;
318320 	struct sdhci_at91_priv		*priv;
....@@ -323,18 +325,23 @@
323325 		return -EINVAL;
324326 	soc_data = match->data;
325327 
326
-	host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
328
+	host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv));
327329 	if (IS_ERR(host))
328330 		return PTR_ERR(host);
329331 
330332 	pltfm_host = sdhci_priv(host);
331333 	priv = sdhci_pltfm_priv(pltfm_host);
334
+	priv->soc_data = soc_data;
332335 
333336 	priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
334337 	if (IS_ERR(priv->mainck)) {
335
-		dev_err(&pdev->dev, "failed to get baseclk\n");
336
-		ret = PTR_ERR(priv->mainck);
337
-		goto sdhci_pltfm_free;
338
+		if (soc_data->baseclk_is_generated_internally) {
339
+			priv->mainck = NULL;
340
+		} else {
341
+			dev_err(&pdev->dev, "failed to get baseclk\n");
342
+			ret = PTR_ERR(priv->mainck);
343
+			goto sdhci_pltfm_free;
344
+		}
338345 	}
339346 
340347 	priv->hclock = devm_clk_get(&pdev->dev, "hclock");
....@@ -357,6 +364,14 @@
357364 
358365 	priv->restore_needed = false;
359366 
367
+	/*
368
+	 * if SDCAL pin is wrongly connected, we must enable
369
+	 * the analog calibration cell permanently.
370
+	 */
371
+	priv->cal_always_on =
372
+		device_property_read_bool(&pdev->dev,
373
+					  "microchip,sdcal-inverted");
374
+
360375 	ret = mmc_of_parse(host->mmc);
361376 	if (ret)
362377 		goto clocks_disable_unprepare;