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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/drivers/gpu/drm/radeon/r600_cs.c
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@@ -26,7 +26,7 @@
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  *          Jerome Glisse
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  */
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 #include <linux/kernel.h>
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-#include <drm/drmP.h>
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+
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 #include "radeon.h"
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 #include "radeon_asic.h"
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 #include "r600d.h"
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@@ -350,7 +350,7 @@
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 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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 {
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 	struct r600_cs_track *track = p->track;
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-	u32 slice_tile_max, size, tmp;
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+	u32 slice_tile_max, tmp;
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 	u32 height, height_align, pitch, pitch_align, depth_align;
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 	u64 base_offset, base_align;
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 	struct array_mode_checker array_check;
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@@ -360,7 +360,6 @@
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 	/* When resolve is used, the second colorbuffer has always 1 sample. */
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 	unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
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-	size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
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 	format = G_0280A0_FORMAT(track->cb_color_info[i]);
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 	if (!r600_fmt_is_valid_color(format)) {
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 		dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
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@@ -488,7 +487,7 @@
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 				return -EINVAL;
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 			}
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 		}
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-		/* fall through */
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+		fallthrough;
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 	case V_0280A0_CLEAR_ENABLE:
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 	{
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 		uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
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@@ -517,7 +516,7 @@
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 static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
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 {
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 	struct r600_cs_track *track = p->track;
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-	u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
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+	u32 nviews, bpe, ntiles, slice_tile_max, tmp;
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 	u32 height_align, pitch_align, depth_align;
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 	u32 pitch = 8192;
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 	u32 height = 8192;
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@@ -564,7 +563,6 @@
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 		}
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 		ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
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 	} else {
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-		size = radeon_bo_size(track->db_bo);
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 		/* pitch in pixels */
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 		pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
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 		slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
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@@ -1537,7 +1535,7 @@
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 		break;
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 	case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
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 		is_array = true;
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-		/* fall through */
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+		fallthrough;
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 	case V_038000_SQ_TEX_DIM_2D_MSAA:
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 		array_check.nsamples = 1 << llevel;
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 		llevel = 0;
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@@ -2342,7 +2340,6 @@
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 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
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 			   struct radeon_bo_list **cs_reloc)
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 {
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-	struct radeon_cs_chunk *relocs_chunk;
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 	unsigned idx;
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 	*cs_reloc = NULL;
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@@ -2350,7 +2347,6 @@
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 		DRM_ERROR("No relocation chunk !\n");
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 		return -EINVAL;
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 	}
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-	relocs_chunk = p->chunk_relocs;
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 	idx = p->dma_reloc_idx;
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 	if (idx >= p->nrelocs) {
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 		DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",