~hc/RK356X_SDK_RELEASE.git

..	..	@@ -21,25 +21,26 @@
21	21	* DEALINGS IN THE SOFTWARE.
22	22	*/
23	23
24		-#include <linux/backlight.h>
	24	+#include <linux/delay.h>
25	25	#include <linux/gpio/consumer.h>
	26	+#include <linux/iopoll.h>
26	27	#include <linux/module.h>
27	28	#include <linux/of_platform.h>
28	29	#include <linux/platform_device.h>
29	30	#include <linux/regulator/consumer.h>
30	31
31		-#include <drm/drmP.h>
32		-#include <drm/drm_crtc.h>
33		-#include <drm/drm_mipi_dsi.h>
34		-#include <drm/drm_panel.h>
35		-
36	32	#include <video/display_timing.h>
37	33	#include <video/mipi_display.h>
38	34	#include <video/of_display_timing.h>
39		-#include <linux/of_graph.h>
40	35	#include <video/videomode.h>
41	36
42		-#include "../rockchip/rockchip_drm_drv.h"
	37	+#include <drm/drm_crtc.h>
	38	+#include <drm/drm_device.h>
	39	+#include <drm/drm_mipi_dsi.h>
	40	+#include <drm/drm_panel.h>
	41	+#include <drm/drm_dsc.h>
	42	+
	43	+#include "panel-simple.h"
43	44
44	45	struct panel_cmd_header {
45	46	u8 data_type;
..	..	@@ -57,6 +58,22 @@
57	58	unsigned int cmd_cnt;
58	59	};
59	60
	61	+/**
	62	+ * @modes: Pointer to array of fixed modes appropriate for this panel. If
	63	+ * only one mode then this can just be the address of this the mode.
	64	+ * NOTE: cannot be used with "timings" and also if this is specified
	65	+ * then you cannot override the mode in the device tree.
	66	+ * @num_modes: Number of elements in modes array.
	67	+ * @timings: Pointer to array of display timings. NOTE: cannot be used with
	68	+ * "modes" and also these will be used to validate a device tree
	69	+ * override if one is present.
	70	+ * @num_timings: Number of elements in timings array.
	71	+ * @bpc: Bits per color.
	72	+ * @size: Structure containing the physical size of this panel.
	73	+ * @delay: Structure containing various delay values for this panel.
	74	+ * @bus_format: See MEDIA_BUS_FMT_... defines.
	75	+ * @bus_flags: See DRM_BUS_FLAG_... defines.
	76	+ */
60	77	struct panel_desc {
61	78	const struct drm_display_mode *modes;
62	79	unsigned int num_modes;
..	..	@@ -77,6 +94,8 @@
77	94	/**
78	95	* @prepare: the time (in milliseconds) that it takes for the panel to
79	96	* become ready and start receiving video data
	97	+ * @hpd_absent_delay: Add this to the prepare delay if we know Hot
	98	+ * Plug Detect isn't used.
80	99	* @enable: the time (in milliseconds) that it takes for the panel to
81	100	* display the first valid frame after starting to receive
82	101	* video data
..	..	@@ -91,6 +110,7 @@
91	110	*/
92	111	struct {
93	112	unsigned int prepare;
	113	+ unsigned int hpd_absent_delay;
94	114	unsigned int enable;
95	115	unsigned int disable;
96	116	unsigned int unprepare;
..	..	@@ -100,6 +120,7 @@
100	120
101	121	u32 bus_format;
102	122	u32 bus_flags;
	123	+ int connector_type;
103	124
104	125	struct panel_cmd_seq *init_seq;
105	126	struct panel_cmd_seq *exit_seq;
..	..	@@ -111,62 +132,22 @@
111	132	bool prepared;
112	133	bool enabled;
113	134	bool power_invert;
	135	+ bool no_hpd;
114	136
115	137	const struct panel_desc *desc;
116	138
117		- struct backlight_device *backlight;
118	139	struct regulator *supply;
119		- struct regulator_bulk_data supplies[2];
120	140	struct i2c_adapter *ddc;
121	141
122	142	struct gpio_desc *enable_gpio;
123	143	struct gpio_desc *reset_gpio;
124		- int cmd_type;
	144	+ struct gpio_desc *hpd_gpio;
125	145
126		- struct gpio_desc *spi_sdi_gpio;
127		- struct gpio_desc *spi_scl_gpio;
128		- struct gpio_desc *spi_cs_gpio;
129		- struct device_node *np_crtc;
	146	+ struct drm_display_mode override_mode;
	147	+
	148	+ struct drm_dsc_picture_parameter_set *pps;
	149	+ enum drm_panel_orientation orientation;
130	150	};
131		-
132		-enum rockchip_cmd_type {
133		- CMD_TYPE_DEFAULT,
134		- CMD_TYPE_SPI,
135		- CMD_TYPE_MCU
136		-};
137		-
138		-enum MCU_IOCTL {
139		- MCU_WRCMD = 0,
140		- MCU_WRDATA,
141		- MCU_SETBYPASS,
142		-};
143		-
144		-enum rockchip_spi_cmd_type {
145		- SPI_3LINE_9BIT_MODE_CMD = 0,
146		- SPI_3LINE_9BIT_MODE_DATA,
147		- SPI_4LINE_8BIT_MODE,
148		-};
149		-
150		-static void panel_simple_sleep(unsigned int msec)
151		-{
152		- if (msec > 20)
153		- msleep(msec);
154		- else
155		- usleep_range(msec * 1000, (msec + 1) * 1000);
156		-}
157		-
158		-static inline int get_panel_cmd_type(const char *s)
159		-{
160		- if (!s)
161		- return -EINVAL;
162		-
163		- if (strncmp(s, "spi", 3) == 0)
164		- return CMD_TYPE_SPI;
165		- else if (strncmp(s, "mcu", 3) == 0)
166		- return CMD_TYPE_MCU;
167		-
168		- return CMD_TYPE_DEFAULT;
169		-}
170	151
171	152	static inline struct panel_simple to_panel_simple(struct drm_panel panel)
172	153	{
..	..	@@ -232,109 +213,16 @@
232	213	return 0;
233	214	}
234	215
235		-static void panel_simple_spi_write_cmd(struct panel_simple *panel,
236		- u8 type, int value)
237		-{
238		- int i;
239		-
240		- gpiod_direction_output(panel->spi_cs_gpio, 0);
241		-
242		- /**
243		- * send cmd or data flag for 3line 9bit serial data
244		- */
245		- if (type == SPI_3LINE_9BIT_MODE_CMD) {
246		- gpiod_direction_output(panel->spi_sdi_gpio, 0);
247		- gpiod_direction_output(panel->spi_scl_gpio, 0);
248		- udelay(10);
249		- gpiod_direction_output(panel->spi_scl_gpio, 1);
250		- udelay(10);
251		- } else if (type == SPI_3LINE_9BIT_MODE_DATA) {
252		- gpiod_direction_output(panel->spi_sdi_gpio, 1);
253		- gpiod_direction_output(panel->spi_scl_gpio, 0);
254		- udelay(10);
255		- gpiod_direction_output(panel->spi_scl_gpio, 1);
256		- udelay(10);
257		- }
258		-
259		- /**
260		- * send the 8bit value from the MSB
261		- */
262		- for (i = 0; i < 8; i++) {
263		- if (value & 0x80)
264		- gpiod_direction_output(panel->spi_sdi_gpio, 1);
265		- else
266		- gpiod_direction_output(panel->spi_sdi_gpio, 0);
267		-
268		- gpiod_direction_output(panel->spi_scl_gpio, 0);
269		- udelay(10);
270		- gpiod_direction_output(panel->spi_scl_gpio, 1);
271		- value <<= 1;
272		- udelay(10);
273		- }
274		-
275		- gpiod_direction_output(panel->spi_cs_gpio, 1);
276		-}
277		-
278		-static int panel_simple_xfer_mcu_cmd_seq(struct panel_simple *panel,
279		- struct panel_cmd_seq *cmds)
280		-{
281		- int i;
282		-
283		- if (!cmds)
284		- return -EINVAL;
285		-
286		- rockchip_drm_crtc_send_mcu_cmd(panel->base.drm,
287		- panel->np_crtc, MCU_SETBYPASS, 1);
288		- for (i = 0; i < cmds->cmd_cnt; i++) {
289		- struct panel_cmd_desc *cmd = &cmds->cmds[i];
290		- u32 value = 0;
291		-
292		- value = cmd->payload[0];
293		- rockchip_drm_crtc_send_mcu_cmd(panel->base.drm, panel->np_crtc,
294		- cmd->header.data_type, value);
295		- if (cmd->header.delay)
296		- panel_simple_sleep(cmd->header.delay);
297		- }
298		- rockchip_drm_crtc_send_mcu_cmd(panel->base.drm,
299		- panel->np_crtc, MCU_SETBYPASS, 0);
300		-
301		- return 0;
302		-}
303		-
304		-static int panel_simple_xfer_spi_cmd_seq(struct panel_simple *panel,
305		- struct panel_cmd_seq *cmds)
306		-{
307		- int i;
308		-
309		- if (!cmds)
310		- return -EINVAL;
311		-
312		- for (i = 0; i < cmds->cmd_cnt; i++) {
313		- struct panel_cmd_desc *cmd = &cmds->cmds[i];
314		- int value = 0;
315		-
316		- if (cmd->header.payload_length == 2)
317		- value = (cmd->payload[0] << 8) \| cmd->payload[1];
318		- else
319		- value = cmd->payload[0];
320		- panel_simple_spi_write_cmd(panel, cmd->header.data_type, value);
321		-
322		- if (cmd->header.delay)
323		- panel_simple_sleep(cmd->header.delay);
324		- }
325		-
326		- return 0;
327		-}
328		-
329		-#if IS_ENABLED(CONFIG_DRM_MIPI_DSI)
330	216	static int panel_simple_xfer_dsi_cmd_seq(struct panel_simple *panel,
331		- struct panel_cmd_seq *seq)
	217	+ struct panel_cmd_seq *seq)
332	218	{
333	219	struct device *dev = panel->base.dev;
334	220	struct mipi_dsi_device *dsi = panel->dsi;
335	221	unsigned int i;
336	222	int err;
337	223
	224	+ if (!IS_ENABLED(CONFIG_DRM_MIPI_DSI))
	225	+ return -EINVAL;
338	226	if (!seq)
339	227	return -EINVAL;
340	228
..	..	@@ -342,6 +230,9 @@
342	230	struct panel_cmd_desc *cmd = &seq->cmds[i];
343	231
344	232	switch (cmd->header.data_type) {
	233	+ case MIPI_DSI_COMPRESSION_MODE:
	234	+ err = mipi_dsi_compression_mode(dsi, cmd->payload[0]);
	235	+ break;
345	236	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
346	237	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
347	238	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
..	..	@@ -355,6 +246,18 @@
355	246	err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
356	247	cmd->header.payload_length);
357	248	break;
	249	+ case MIPI_DSI_PICTURE_PARAMETER_SET:
	250	+ if (!panel->pps) {
	251	+ panel->pps = devm_kzalloc(dev, sizeof(*panel->pps),
	252	+ GFP_KERNEL);
	253	+ if (!panel->pps)
	254	+ return -ENOMEM;
	255	+
	256	+ memcpy(panel->pps, cmd->payload, cmd->header.payload_length);
	257	+ }
	258	+
	259	+ err = mipi_dsi_picture_parameter_set(dsi, panel->pps);
	260	+ break;
358	261	default:
359	262	return -EINVAL;
360	263	}
..	..	@@ -363,37 +266,26 @@
363	266	dev_err(dev, "failed to write dcs cmd: %d\n", err);
364	267
365	268	if (cmd->header.delay)
366		- panel_simple_sleep(cmd->header.delay);
	269	+ msleep(cmd->header.delay);
367	270	}
368	271
369	272	return 0;
370	273	}
371		-#else
372		-static inline int panel_simple_xfer_dsi_cmd_seq(struct panel_simple *panel,
373		- struct panel_cmd_seq *seq)
374		-{
375		- return -EINVAL;
376		-}
377		-#endif
378	274
379		-static int panel_simple_get_fixed_modes(struct panel_simple *panel)
	275	+static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
	276	+ struct drm_connector *connector)
380	277	{
381		- struct drm_connector *connector = panel->base.connector;
382		- struct drm_device *drm = panel->base.drm;
383	278	struct drm_display_mode *mode;
384	279	unsigned int i, num = 0;
385		-
386		- if (!panel->desc)
387		- return 0;
388	280
389	281	for (i = 0; i < panel->desc->num_timings; i++) {
390	282	const struct display_timing *dt = &panel->desc->timings[i];
391	283	struct videomode vm;
392	284
393	285	videomode_from_timing(dt, &vm);
394		- mode = drm_mode_create(drm);
	286	+ mode = drm_mode_create(connector->dev);
395	287	if (!mode) {
396		- dev_err(drm->dev, "failed to add mode %ux%u\n",
	288	+ dev_err(panel->base.dev, "failed to add mode %ux%u\n",
397	289	dt->hactive.typ, dt->vactive.typ);
398	290	continue;
399	291	}
..	..	@@ -409,13 +301,23 @@
409	301	num++;
410	302	}
411	303
	304	+ return num;
	305	+}
	306	+
	307	+static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
	308	+ struct drm_connector *connector)
	309	+{
	310	+ struct drm_display_mode *mode;
	311	+ unsigned int i, num = 0;
	312	+
412	313	for (i = 0; i < panel->desc->num_modes; i++) {
413	314	const struct drm_display_mode *m = &panel->desc->modes[i];
414	315
415		- mode = drm_mode_duplicate(drm, m);
	316	+ mode = drm_mode_duplicate(connector->dev, m);
416	317	if (!mode) {
417		- dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
418		- m->hdisplay, m->vdisplay, m->vrefresh);
	318	+ dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
	319	+ m->hdisplay, m->vdisplay,
	320	+ drm_mode_vrefresh(m));
419	321	continue;
420	322	}
421	323
..	..	@@ -429,6 +331,44 @@
429	331	drm_mode_probed_add(connector, mode);
430	332	num++;
431	333	}
	334	+
	335	+ return num;
	336	+}
	337	+
	338	+static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
	339	+ struct drm_connector *connector)
	340	+{
	341	+ struct drm_display_mode *mode;
	342	+ bool has_override = panel->override_mode.type;
	343	+ unsigned int num = 0;
	344	+
	345	+ if (!panel->desc)
	346	+ return 0;
	347	+
	348	+ if (has_override) {
	349	+ mode = drm_mode_duplicate(connector->dev,
	350	+ &panel->override_mode);
	351	+ if (mode) {
	352	+ drm_mode_probed_add(connector, mode);
	353	+ num = 1;
	354	+ } else {
	355	+ dev_err(panel->base.dev, "failed to add override mode\n");
	356	+ }
	357	+ }
	358	+
	359	+ /* Only add timings if override was not there or failed to validate */
	360	+ if (num == 0 && panel->desc->num_timings)
	361	+ num = panel_simple_get_timings_modes(panel, connector);
	362	+
	363	+ /*
	364	+ * Only add fixed modes if timings/override added no mode.
	365	+ *
	366	+ * We should only ever have either the display timings specified
	367	+ * or a fixed mode. Anything else is rather bogus.
	368	+ */
	369	+ WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
	370	+ if (num == 0)
	371	+ num = panel_simple_get_display_modes(panel, connector);
432	372
433	373	if (panel->desc->bpc)
434	374	connector->display_info.bpc = panel->desc->bpc;
..	..	@@ -448,10 +388,6 @@
448	388	static int panel_simple_regulator_enable(struct panel_simple *p)
449	389	{
450	390	int err;
451		-
452		- err = regulator_bulk_enable(ARRAY_SIZE(p->supplies), p->supplies);
453		- if (err < 0)
454		- return err;
455	391
456	392	if (p->power_invert) {
457	393	if (regulator_is_enabled(p->supply) > 0)
..	..	@@ -479,55 +415,37 @@
479	415	regulator_disable(p->supply);
480	416	}
481	417
482		- regulator_bulk_disable(ARRAY_SIZE(p->supplies), p->supplies);
483		-
484	418	return 0;
485	419	}
486	420
487		-static int panel_simple_loader_protect(struct drm_panel *panel, bool on)
	421	+int panel_simple_loader_protect(struct drm_panel *panel)
488	422	{
489	423	struct panel_simple *p = to_panel_simple(panel);
490	424	int err;
491	425
492		- if (on) {
493		- err = panel_simple_regulator_enable(p);
494		- if (err < 0) {
495		- dev_err(panel->dev, "failed to enable supply: %d\n",
496		- err);
497		- return err;
498		- }
499		-
500		- p->prepared = true;
501		- p->enabled = true;
502		- } else {
503		- /* do nothing */
	426	+ err = panel_simple_regulator_enable(p);
	427	+ if (err < 0) {
	428	+ dev_err(panel->dev, "failed to enable supply: %d\n", err);
	429	+ return err;
504	430	}
	431	+
	432	+ p->prepared = true;
	433	+ p->enabled = true;
505	434
506	435	return 0;
507	436	}
	437	+EXPORT_SYMBOL(panel_simple_loader_protect);
508	438
509	439	static int panel_simple_disable(struct drm_panel *panel)
510	440	{
511	441	struct panel_simple *p = to_panel_simple(panel);
512		- int err = 0;
513	442
514	443	if (!p->enabled)
515	444	return 0;
516	445
517		- if (p->backlight) {
518		- p->backlight->props.power = FB_BLANK_POWERDOWN;
519		- p->backlight->props.state \|= BL_CORE_FBBLANK;
520		- backlight_update_status(p->backlight);
521		- }
522		-
523	446	if (p->desc->delay.disable)
524		- panel_simple_sleep(p->desc->delay.disable);
	447	+ msleep(p->desc->delay.disable);
525	448
526		- if (p->cmd_type == CMD_TYPE_MCU) {
527		- err = panel_simple_xfer_mcu_cmd_seq(p, p->desc->exit_seq);
528		- if (err)
529		- dev_err(panel->dev, "failed to send exit cmds seq\n");
530		- }
531	449	p->enabled = false;
532	450
533	451	return 0;
..	..	@@ -536,30 +454,48 @@
536	454	static int panel_simple_unprepare(struct drm_panel *panel)
537	455	{
538	456	struct panel_simple *p = to_panel_simple(panel);
539		- int err = 0;
540	457
541	458	if (!p->prepared)
542	459	return 0;
543	460
544		- if (p->desc->exit_seq) {
	461	+ if (p->desc->exit_seq)
545	462	if (p->dsi)
546	463	panel_simple_xfer_dsi_cmd_seq(p, p->desc->exit_seq);
547		- else if (p->cmd_type == CMD_TYPE_SPI)
548		- err = panel_simple_xfer_spi_cmd_seq(p, p->desc->exit_seq);
549		- if (err)
550		- dev_err(panel->dev, "failed to send exit cmds seq\n");
551		- }
552	464
553	465	gpiod_direction_output(p->reset_gpio, 1);
554		-
555	466	gpiod_direction_output(p->enable_gpio, 0);
556	467
557	468	panel_simple_regulator_disable(p);
558	469
559	470	if (p->desc->delay.unprepare)
560		- panel_simple_sleep(p->desc->delay.unprepare);
	471	+ msleep(p->desc->delay.unprepare);
561	472
562	473	p->prepared = false;
	474	+
	475	+ return 0;
	476	+}
	477	+
	478	+static int panel_simple_get_hpd_gpio(struct device *dev,
	479	+ struct panel_simple *p, bool from_probe)
	480	+{
	481	+ int err;
	482	+
	483	+ p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
	484	+ if (IS_ERR(p->hpd_gpio)) {
	485	+ err = PTR_ERR(p->hpd_gpio);
	486	+
	487	+ /*
	488	+ * If we're called from probe we won't consider '-EPROBE_DEFER'
	489	+ * to be an error--we'll leave the error code in "hpd_gpio".
	490	+ * When we try to use it we'll try again. This allows for
	491	+ * circular dependencies where the component providing the
	492	+ * hpd gpio needs the panel to init before probing.
	493	+ */
	494	+ if (err != -EPROBE_DEFER \|\| !from_probe) {
	495	+ dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
	496	+ return err;
	497	+ }
	498	+ }
563	499
564	500	return 0;
565	501	}
..	..	@@ -567,7 +503,9 @@
567	503	static int panel_simple_prepare(struct drm_panel *panel)
568	504	{
569	505	struct panel_simple *p = to_panel_simple(panel);
	506	+ unsigned int delay;
570	507	int err;
	508	+ int hpd_asserted;
571	509
572	510	if (p->prepared)
573	511	return 0;
..	..	@@ -580,27 +518,45 @@
580	518
581	519	gpiod_direction_output(p->enable_gpio, 1);
582	520
583		- if (p->desc->delay.prepare)
584		- panel_simple_sleep(p->desc->delay.prepare);
	521	+ delay = p->desc->delay.prepare;
	522	+ if (p->no_hpd)
	523	+ delay += p->desc->delay.hpd_absent_delay;
	524	+ if (delay)
	525	+ msleep(delay);
	526	+
	527	+ if (p->hpd_gpio) {
	528	+ if (IS_ERR(p->hpd_gpio)) {
	529	+ err = panel_simple_get_hpd_gpio(panel->dev, p, false);
	530	+ if (err)
	531	+ return err;
	532	+ }
	533	+
	534	+ err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
	535	+ hpd_asserted, hpd_asserted,
	536	+ 1000, 2000000);
	537	+ if (hpd_asserted < 0)
	538	+ err = hpd_asserted;
	539	+
	540	+ if (err) {
	541	+ dev_err(panel->dev,
	542	+ "error waiting for hpd GPIO: %d\n", err);
	543	+ return err;
	544	+ }
	545	+ }
585	546
586	547	gpiod_direction_output(p->reset_gpio, 1);
587	548
588	549	if (p->desc->delay.reset)
589		- panel_simple_sleep(p->desc->delay.reset);
	550	+ msleep(p->desc->delay.reset);
590	551
591	552	gpiod_direction_output(p->reset_gpio, 0);
592	553
593	554	if (p->desc->delay.init)
594		- panel_simple_sleep(p->desc->delay.init);
	555	+ msleep(p->desc->delay.init);
595	556
596		- if (p->desc->init_seq) {
	557	+ if (p->desc->init_seq)
597	558	if (p->dsi)
598	559	panel_simple_xfer_dsi_cmd_seq(p, p->desc->init_seq);
599		- else if (p->cmd_type == CMD_TYPE_SPI)
600		- err = panel_simple_xfer_spi_cmd_seq(p, p->desc->init_seq);
601		- if (err)
602		- dev_err(panel->dev, "failed to send init cmds seq\n");
603		- }
604	560
605	561	p->prepared = true;
606	562
..	..	@@ -610,47 +566,40 @@
610	566	static int panel_simple_enable(struct drm_panel *panel)
611	567	{
612	568	struct panel_simple *p = to_panel_simple(panel);
613		- int err = 0;
614	569
615	570	if (p->enabled)
616	571	return 0;
617	572
618		- if (p->cmd_type == CMD_TYPE_MCU) {
619		- err = panel_simple_xfer_mcu_cmd_seq(p, p->desc->init_seq);
620		- if (err)
621		- dev_err(panel->dev, "failed to send init cmds seq\n");
622		- }
623	573	if (p->desc->delay.enable)
624		- panel_simple_sleep(p->desc->delay.enable);
625		-
626		- if (p->backlight) {
627		- p->backlight->props.state &= ~BL_CORE_FBBLANK;
628		- p->backlight->props.power = FB_BLANK_UNBLANK;
629		- backlight_update_status(p->backlight);
630		- }
	574	+ msleep(p->desc->delay.enable);
631	575
632	576	p->enabled = true;
633	577
634	578	return 0;
635	579	}
636	580
637		-static int panel_simple_get_modes(struct drm_panel *panel)
	581	+static int panel_simple_get_modes(struct drm_panel *panel,
	582	+ struct drm_connector *connector)
638	583	{
639	584	struct panel_simple *p = to_panel_simple(panel);
640	585	int num = 0;
641	586
642	587	/* probe EDID if a DDC bus is available */
643	588	if (p->ddc) {
644		- struct edid *edid = drm_get_edid(panel->connector, p->ddc);
645		- drm_connector_update_edid_property(panel->connector, edid);
	589	+ struct edid *edid = drm_get_edid(connector, p->ddc);
	590	+
	591	+ drm_connector_update_edid_property(connector, edid);
646	592	if (edid) {
647		- num += drm_add_edid_modes(panel->connector, edid);
	593	+ num += drm_add_edid_modes(connector, edid);
648	594	kfree(edid);
649	595	}
650	596	}
651	597
652	598	/* add hard-coded panel modes */
653		- num += panel_simple_get_fixed_modes(p);
	599	+ num += panel_simple_get_non_edid_modes(p, connector);
	600	+
	601	+ /* set up connector's "panel orientation" property */
	602	+ drm_connector_set_panel_orientation(connector, p->orientation);
654	603
655	604	return num;
656	605	}
..	..	@@ -673,7 +622,6 @@
673	622	}
674	623
675	624	static const struct drm_panel_funcs panel_simple_funcs = {
676		- .loader_protect = panel_simple_loader_protect,
677	625	.disable = panel_simple_disable,
678	626	.unprepare = panel_simple_unprepare,
679	627	.prepare = panel_simple_prepare,
..	..	@@ -682,11 +630,154 @@
682	630	.get_timings = panel_simple_get_timings,
683	631	};
684	632
	633	+static struct panel_desc panel_dpi;
	634	+
	635	+static int panel_dpi_probe(struct device *dev,
	636	+ struct panel_simple *panel)
	637	+{
	638	+ struct display_timing *timing;
	639	+ const struct device_node *np;
	640	+ struct panel_desc *desc;
	641	+ unsigned int bus_flags;
	642	+ struct videomode vm;
	643	+ int ret;
	644	+
	645	+ np = dev->of_node;
	646	+ desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
	647	+ if (!desc)
	648	+ return -ENOMEM;
	649	+
	650	+ timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
	651	+ if (!timing)
	652	+ return -ENOMEM;
	653	+
	654	+ ret = of_get_display_timing(np, "panel-timing", timing);
	655	+ if (ret < 0) {
	656	+ dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
	657	+ np);
	658	+ return ret;
	659	+ }
	660	+
	661	+ desc->timings = timing;
	662	+ desc->num_timings = 1;
	663	+
	664	+ of_property_read_u32(np, "width-mm", &desc->size.width);
	665	+ of_property_read_u32(np, "height-mm", &desc->size.height);
	666	+
	667	+ /* Extract bus_flags from display_timing */
	668	+ bus_flags = 0;
	669	+ vm.flags = timing->flags;
	670	+ drm_bus_flags_from_videomode(&vm, &bus_flags);
	671	+ desc->bus_flags = bus_flags;
	672	+
	673	+ /* We do not know the connector for the DT node, so guess it */
	674	+ desc->connector_type = DRM_MODE_CONNECTOR_DPI;
	675	+
	676	+ panel->desc = desc;
	677	+
	678	+ return 0;
	679	+}
	680	+
	681	+#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
	682	+ (to_check->field.typ >= bounds->field.min && \
	683	+ to_check->field.typ <= bounds->field.max)
	684	+static void panel_simple_parse_panel_timing_node(struct device *dev,
	685	+ struct panel_simple *panel,
	686	+ const struct display_timing *ot)
	687	+{
	688	+ const struct panel_desc *desc = panel->desc;
	689	+ struct videomode vm;
	690	+ unsigned int i;
	691	+
	692	+ if (WARN_ON(desc->num_modes)) {
	693	+ dev_err(dev, "Reject override mode: panel has a fixed mode\n");
	694	+ return;
	695	+ }
	696	+ if (WARN_ON(!desc->num_timings)) {
	697	+ dev_err(dev, "Reject override mode: no timings specified\n");
	698	+ return;
	699	+ }
	700	+
	701	+ for (i = 0; i < panel->desc->num_timings; i++) {
	702	+ const struct display_timing *dt = &panel->desc->timings[i];
	703	+
	704	+ if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) \|\|
	705	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) \|\|
	706	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) \|\|
	707	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) \|\|
	708	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) \|\|
	709	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) \|\|
	710	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) \|\|
	711	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
	712	+ continue;
	713	+
	714	+ if (ot->flags != dt->flags)
	715	+ continue;
	716	+
	717	+ videomode_from_timing(ot, &vm);
	718	+ drm_display_mode_from_videomode(&vm, &panel->override_mode);
	719	+ panel->override_mode.type \|= DRM_MODE_TYPE_DRIVER \|
	720	+ DRM_MODE_TYPE_PREFERRED;
	721	+ break;
	722	+ }
	723	+
	724	+ if (WARN_ON(!panel->override_mode.type))
	725	+ dev_err(dev, "Reject override mode: No display_timing found\n");
	726	+}
	727	+
	728	+static int dcs_bl_update_status(struct backlight_device *bl)
	729	+{
	730	+ struct panel_simple *p = bl_get_data(bl);
	731	+ struct mipi_dsi_device *dsi = p->dsi;
	732	+ int ret;
	733	+
	734	+ if (!p->prepared)
	735	+ return 0;
	736	+
	737	+ dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
	738	+
	739	+ ret = mipi_dsi_dcs_set_display_brightness(dsi, bl->props.brightness);
	740	+ if (ret < 0)
	741	+ return ret;
	742	+
	743	+ dsi->mode_flags \|= MIPI_DSI_MODE_LPM;
	744	+
	745	+ return 0;
	746	+}
	747	+
	748	+static int dcs_bl_get_brightness(struct backlight_device *bl)
	749	+{
	750	+ struct panel_simple *p = bl_get_data(bl);
	751	+ struct mipi_dsi_device *dsi = p->dsi;
	752	+ u16 brightness = bl->props.brightness;
	753	+ int ret;
	754	+
	755	+ if (!p->prepared)
	756	+ return 0;
	757	+
	758	+ dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
	759	+
	760	+ ret = mipi_dsi_dcs_get_display_brightness(dsi, &brightness);
	761	+ if (ret < 0)
	762	+ return ret;
	763	+
	764	+ dsi->mode_flags \|= MIPI_DSI_MODE_LPM;
	765	+
	766	+ return brightness & 0xff;
	767	+}
	768	+
	769	+static const struct backlight_ops dcs_bl_ops = {
	770	+ .update_status = dcs_bl_update_status,
	771	+ .get_brightness = dcs_bl_get_brightness,
	772	+};
	773	+
685	774	static int panel_simple_probe(struct device dev, const struct panel_desc desc)
686	775	{
687		- struct device_node backlight, ddc;
688	776	struct panel_simple *panel;
689		- const char *cmd_type;
	777	+ struct display_timing dt;
	778	+ struct device_node *ddc;
	779	+ int connector_type;
	780	+ u32 bus_flags;
690	781	int err;
691	782
692	783	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
..	..	@@ -697,20 +788,21 @@
697	788	panel->prepared = false;
698	789	panel->desc = desc;
699	790
	791	+ panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
	792	+ if (!panel->no_hpd) {
	793	+ err = panel_simple_get_hpd_gpio(dev, panel, true);
	794	+ if (err)
	795	+ return err;
	796	+ }
	797	+
700	798	panel->supply = devm_regulator_get(dev, "power");
701		- if (IS_ERR(panel->supply))
702		- return PTR_ERR(panel->supply);
703		-
704		- panel->supplies[0].supply = "vsp";
705		- panel->supplies[1].supply = "vsn";
706		-
707		- err = devm_regulator_bulk_get(dev, ARRAY_SIZE(panel->supplies),
708		- panel->supplies);
709		- if (err)
	799	+ if (IS_ERR(panel->supply)) {
	800	+ err = PTR_ERR(panel->supply);
	801	+ dev_err(dev, "failed to get power regulator: %d\n", err);
710	802	return err;
	803	+ }
711	804
712		- panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
713		- GPIOD_ASIS);
	805	+ panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_ASIS);
714	806	if (IS_ERR(panel->enable_gpio)) {
715	807	err = PTR_ERR(panel->enable_gpio);
716	808	if (err != -EPROBE_DEFER)
..	..	@@ -726,68 +818,13 @@
726	818	return err;
727	819	}
728	820
729		- if (of_property_read_string(dev->of_node, "rockchip,cmd-type",
730		- &cmd_type))
731		- panel->cmd_type = CMD_TYPE_DEFAULT;
732		- else
733		- panel->cmd_type = get_panel_cmd_type(cmd_type);
734		-
735		- if (panel->cmd_type == CMD_TYPE_SPI) {
736		- panel->spi_sdi_gpio =
737		- devm_gpiod_get_optional(dev, "spi-sdi", 0);
738		- if (IS_ERR(panel->spi_sdi_gpio)) {
739		- err = PTR_ERR(panel->spi_sdi_gpio);
740		- dev_err(dev, "failed to request spi_sdi: %d\n", err);
741		- return err;
742		- }
743		-
744		- panel->spi_scl_gpio =
745		- devm_gpiod_get_optional(dev, "spi-scl", 0);
746		- if (IS_ERR(panel->spi_scl_gpio)) {
747		- err = PTR_ERR(panel->spi_scl_gpio);
748		- dev_err(dev, "failed to request spi_scl: %d\n", err);
749		- return err;
750		- }
751		-
752		- panel->spi_cs_gpio = devm_gpiod_get_optional(dev, "spi-cs", 0);
753		- if (IS_ERR(panel->spi_cs_gpio)) {
754		- err = PTR_ERR(panel->spi_cs_gpio);
755		- dev_err(dev, "failed to request spi_cs: %d\n", err);
756		- return err;
757		- }
758		- gpiod_direction_output(panel->spi_cs_gpio, 1);
759		- gpiod_direction_output(panel->spi_sdi_gpio, 1);
760		- gpiod_direction_output(panel->spi_scl_gpio, 1);
761		- } else if (panel->cmd_type == CMD_TYPE_MCU) {
762		- struct device_node port, endpoint;
763		- struct device_node *np;
764		-
765		- port = of_graph_get_port_by_id(dev->of_node, 0);
766		- if (port) {
767		- endpoint = of_get_next_child(port, NULL);
768		- /* get connect device node */
769		- np = of_graph_get_remote_port_parent(endpoint);
770		-
771		- port = of_graph_get_port_by_id(np, 0);
772		- if (port) {
773		- endpoint = of_get_next_child(port, NULL);
774		- /* get crtc device node */
775		- np = of_graph_get_remote_port_parent(endpoint);
776		- panel->np_crtc = np;
777		- }
778		- }
	821	+ err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
	822	+ if (err) {
	823	+ dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
	824	+ return err;
779	825	}
780		- panel->power_invert =
781		- of_property_read_bool(dev->of_node, "power-invert");
782	826
783		- backlight = of_parse_phandle(dev->of_node, "backlight", 0);
784		- if (backlight) {
785		- panel->backlight = of_find_backlight_by_node(backlight);
786		- of_node_put(backlight);
787		-
788		- if (!panel->backlight)
789		- return -EPROBE_DEFER;
790		- }
	827	+ panel->power_invert = of_property_read_bool(dev->of_node, "power-invert");
791	828
792	829	ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
793	830	if (ddc) {
..	..	@@ -796,17 +833,87 @@
796	833
797	834	if (!panel->ddc) {
798	835	err = -EPROBE_DEFER;
799		- goto free_backlight;
	836	+ dev_err(dev, "failed to find ddc-i2c-bus: %d\n", err);
	837	+ return err;
800	838	}
801	839	}
802	840
803		- drm_panel_init(&panel->base);
804		- panel->base.dev = dev;
805		- panel->base.funcs = &panel_simple_funcs;
	841	+ if (desc == &panel_dpi) {
	842	+ /* Handle the generic panel-dpi binding */
	843	+ err = panel_dpi_probe(dev, panel);
	844	+ if (err)
	845	+ goto free_ddc;
	846	+ desc = panel->desc;
	847	+ } else {
	848	+ if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
	849	+ panel_simple_parse_panel_timing_node(dev, panel, &dt);
	850	+ }
806	851
807		- err = drm_panel_add(&panel->base);
808		- if (err < 0)
	852	+ connector_type = desc->connector_type;
	853	+ /* Catch common mistakes for panels. */
	854	+ switch (connector_type) {
	855	+ case 0:
	856	+ dev_dbg(dev, "Specify missing connector_type\n");
	857	+ connector_type = DRM_MODE_CONNECTOR_DPI;
	858	+ break;
	859	+ case DRM_MODE_CONNECTOR_LVDS:
	860	+ WARN_ON(desc->bus_flags &
	861	+ ~(DRM_BUS_FLAG_DE_LOW \|
	862	+ DRM_BUS_FLAG_DE_HIGH \|
	863	+ DRM_BUS_FLAG_DATA_MSB_TO_LSB \|
	864	+ DRM_BUS_FLAG_DATA_LSB_TO_MSB));
	865	+ WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
	866	+ desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
	867	+ desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
	868	+ WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
	869	+ desc->bpc != 6);
	870	+ WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG \|\|
	871	+ desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
	872	+ desc->bpc != 8);
	873	+ break;
	874	+ case DRM_MODE_CONNECTOR_eDP:
	875	+ if (desc->bus_format == 0)
	876	+ dev_warn(dev, "Specify missing bus_format\n");
	877	+ if (desc->bpc != 6 && desc->bpc != 8)
	878	+ dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
	879	+ break;
	880	+ case DRM_MODE_CONNECTOR_DSI:
	881	+ if (desc->bpc != 6 && desc->bpc != 8)
	882	+ dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
	883	+ break;
	884	+ case DRM_MODE_CONNECTOR_DPI:
	885	+ bus_flags = DRM_BUS_FLAG_DE_LOW \|
	886	+ DRM_BUS_FLAG_DE_HIGH \|
	887	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE \|
	888	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	889	+ DRM_BUS_FLAG_DATA_MSB_TO_LSB \|
	890	+ DRM_BUS_FLAG_DATA_LSB_TO_MSB \|
	891	+ DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE \|
	892	+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
	893	+ if (desc->bus_flags & ~bus_flags)
	894	+ dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
	895	+ if (!(desc->bus_flags & bus_flags))
	896	+ dev_warn(dev, "Specify missing bus_flags\n");
	897	+ if (desc->bus_format == 0)
	898	+ dev_warn(dev, "Specify missing bus_format\n");
	899	+ if (desc->bpc != 6 && desc->bpc != 8)
	900	+ dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
	901	+ break;
	902	+ default:
	903	+ dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
	904	+ connector_type = DRM_MODE_CONNECTOR_DPI;
	905	+ break;
	906	+ }
	907	+
	908	+ drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
	909	+
	910	+ err = drm_panel_of_backlight(&panel->base);
	911	+ if (err) {
	912	+ dev_err(dev, "failed to find backlight: %d\n", err);
809	913	goto free_ddc;
	914	+ }
	915	+
	916	+ drm_panel_add(&panel->base);
810	917
811	918	dev_set_drvdata(dev, panel);
812	919
..	..	@@ -815,9 +922,6 @@
815	922	free_ddc:
816	923	if (panel->ddc)
817	924	put_device(&panel->ddc->dev);
818		-free_backlight:
819		- if (panel->backlight)
820		- put_device(&panel->backlight->dev);
821	925
822	926	return err;
823	927	}
..	..	@@ -827,15 +931,11 @@
827	931	struct panel_simple *panel = dev_get_drvdata(dev);
828	932
829	933	drm_panel_remove(&panel->base);
830		-
831		- panel_simple_disable(&panel->base);
832		- panel_simple_unprepare(&panel->base);
	934	+ drm_panel_disable(&panel->base);
	935	+ drm_panel_unprepare(&panel->base);
833	936
834	937	if (panel->ddc)
835	938	put_device(&panel->ddc->dev);
836		-
837		- if (panel->backlight)
838		- put_device(&panel->backlight->dev);
839	939
840	940	return 0;
841	941	}
..	..	@@ -844,14 +944,35 @@
844	944	{
845	945	struct panel_simple *panel = dev_get_drvdata(dev);
846	946
847		- panel_simple_disable(&panel->base);
848		-
849		- if (panel->prepared) {
850		- gpiod_direction_output(panel->reset_gpio, 1);
851		- gpiod_direction_output(panel->enable_gpio, 0);
852		- panel_simple_regulator_disable(panel);
853		- }
	947	+ drm_panel_disable(&panel->base);
	948	+ drm_panel_unprepare(&panel->base);
854	949	}
	950	+
	951	+static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
	952	+ .clock = 71100,
	953	+ .hdisplay = 1280,
	954	+ .hsync_start = 1280 + 40,
	955	+ .hsync_end = 1280 + 40 + 80,
	956	+ .htotal = 1280 + 40 + 80 + 40,
	957	+ .vdisplay = 800,
	958	+ .vsync_start = 800 + 3,
	959	+ .vsync_end = 800 + 3 + 10,
	960	+ .vtotal = 800 + 3 + 10 + 10,
	961	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	962	+};
	963	+
	964	+static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
	965	+ .modes = &ampire_am_1280800n3tzqw_t00h_mode,
	966	+ .num_modes = 1,
	967	+ .bpc = 8,
	968	+ .size = {
	969	+ .width = 217,
	970	+ .height = 136,
	971	+ },
	972	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	973	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	974	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	975	+};
855	976
856	977	static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
857	978	.clock = 9000,
..	..	@@ -863,7 +984,6 @@
863	984	.vsync_start = 272 + 2,
864	985	.vsync_end = 272 + 2 + 10,
865	986	.vtotal = 272 + 2 + 10 + 2,
866		- .vrefresh = 60,
867	987	.flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
868	988	};
869	989
..	..	@@ -888,7 +1008,6 @@
888	1008	.vsync_start = 480 + 2,
889	1009	.vsync_end = 480 + 2 + 45,
890	1010	.vtotal = 480 + 2 + 45 + 0,
891		- .vrefresh = 60,
892	1011	.flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
893	1012	};
894	1013
..	..	@@ -926,7 +1045,7 @@
926	1045	.height = 86,
927	1046	},
928	1047	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
929		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	1048	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
930	1049	};
931	1050
932	1051	static const struct drm_display_mode auo_b101aw03_mode = {
..	..	@@ -939,7 +1058,6 @@
939	1058	.vsync_start = 600 + 16,
940	1059	.vsync_end = 600 + 16 + 6,
941	1060	.vtotal = 600 + 16 + 6 + 16,
942		- .vrefresh = 60,
943	1061	};
944	1062
945	1063	static const struct panel_desc auo_b101aw03 = {
..	..	@@ -950,24 +1068,26 @@
950	1068	.width = 223,
951	1069	.height = 125,
952	1070	},
	1071	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1072	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1073	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
953	1074	};
954	1075
955		-static const struct drm_display_mode auo_b101ean01_mode = {
956		- .clock = 72500,
957		- .hdisplay = 1280,
958		- .hsync_start = 1280 + 119,
959		- .hsync_end = 1280 + 119 + 32,
960		- .htotal = 1280 + 119 + 32 + 21,
961		- .vdisplay = 800,
962		- .vsync_start = 800 + 4,
963		- .vsync_end = 800 + 4 + 20,
964		- .vtotal = 800 + 4 + 20 + 8,
965		- .vrefresh = 60,
	1076	+static const struct display_timing auo_b101ean01_timing = {
	1077	+ .pixelclock = { 65300000, 72500000, 75000000 },
	1078	+ .hactive = { 1280, 1280, 1280 },
	1079	+ .hfront_porch = { 18, 119, 119 },
	1080	+ .hback_porch = { 21, 21, 21 },
	1081	+ .hsync_len = { 32, 32, 32 },
	1082	+ .vactive = { 800, 800, 800 },
	1083	+ .vfront_porch = { 4, 4, 4 },
	1084	+ .vback_porch = { 8, 8, 8 },
	1085	+ .vsync_len = { 18, 20, 20 },
966	1086	};
967	1087
968	1088	static const struct panel_desc auo_b101ean01 = {
969		- .modes = &auo_b101ean01_mode,
970		- .num_modes = 1,
	1089	+ .timings = &auo_b101ean01_timing,
	1090	+ .num_timings = 1,
971	1091	.bpc = 6,
972	1092	.size = {
973	1093	.width = 217,
..	..	@@ -985,7 +1105,6 @@
985	1105	.vsync_start = 768 + 14,
986	1106	.vsync_end = 768 + 14 + 42,
987	1107	.vtotal = 768 + 14 + 42,
988		- .vrefresh = 60,
989	1108	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
990	1109	};
991	1110
..	..	@@ -999,6 +1118,34 @@
999	1118	},
1000	1119	};
1001	1120
	1121	+static const struct drm_display_mode auo_b116xak01_mode = {
	1122	+ .clock = 69300,
	1123	+ .hdisplay = 1366,
	1124	+ .hsync_start = 1366 + 48,
	1125	+ .hsync_end = 1366 + 48 + 32,
	1126	+ .htotal = 1366 + 48 + 32 + 10,
	1127	+ .vdisplay = 768,
	1128	+ .vsync_start = 768 + 4,
	1129	+ .vsync_end = 768 + 4 + 6,
	1130	+ .vtotal = 768 + 4 + 6 + 15,
	1131	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	1132	+};
	1133	+
	1134	+static const struct panel_desc auo_b116xak01 = {
	1135	+ .modes = &auo_b116xak01_mode,
	1136	+ .num_modes = 1,
	1137	+ .bpc = 6,
	1138	+ .size = {
	1139	+ .width = 256,
	1140	+ .height = 144,
	1141	+ },
	1142	+ .delay = {
	1143	+ .hpd_absent_delay = 200,
	1144	+ },
	1145	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1146	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	1147	+};
	1148	+
1002	1149	static const struct drm_display_mode auo_b116xw03_mode = {
1003	1150	.clock = 70589,
1004	1151	.hdisplay = 1366,
..	..	@@ -1009,7 +1156,7 @@
1009	1156	.vsync_start = 768 + 10,
1010	1157	.vsync_end = 768 + 10 + 12,
1011	1158	.vtotal = 768 + 10 + 12 + 6,
1012		- .vrefresh = 60,
	1159	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1013	1160	};
1014	1161
1015	1162	static const struct panel_desc auo_b116xw03 = {
..	..	@@ -1020,6 +1167,12 @@
1020	1167	.width = 256,
1021	1168	.height = 144,
1022	1169	},
	1170	+ .delay = {
	1171	+ .enable = 400,
	1172	+ },
	1173	+ .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
	1174	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1175	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
1023	1176	};
1024	1177
1025	1178	static const struct drm_display_mode auo_b133xtn01_mode = {
..	..	@@ -1032,7 +1185,6 @@
1032	1185	.vsync_start = 768 + 3,
1033	1186	.vsync_end = 768 + 3 + 6,
1034	1187	.vtotal = 768 + 3 + 6 + 13,
1035		- .vrefresh = 60,
1036	1188	};
1037	1189
1038	1190	static const struct panel_desc auo_b133xtn01 = {
..	..	@@ -1055,7 +1207,6 @@
1055	1207	.vsync_start = 1080 + 25,
1056	1208	.vsync_end = 1080 + 25 + 10,
1057	1209	.vtotal = 1080 + 25 + 10 + 10,
1058		- .vrefresh = 60,
1059	1210	};
1060	1211
1061	1212	static const struct panel_desc auo_b133htn01 = {
..	..	@@ -1101,6 +1252,30 @@
1101	1252	},
1102	1253	};
1103	1254
	1255	+static const struct drm_display_mode auo_g101evn010_mode = {
	1256	+ .clock = 68930,
	1257	+ .hdisplay = 1280,
	1258	+ .hsync_start = 1280 + 82,
	1259	+ .hsync_end = 1280 + 82 + 2,
	1260	+ .htotal = 1280 + 82 + 2 + 84,
	1261	+ .vdisplay = 800,
	1262	+ .vsync_start = 800 + 8,
	1263	+ .vsync_end = 800 + 8 + 2,
	1264	+ .vtotal = 800 + 8 + 2 + 6,
	1265	+};
	1266	+
	1267	+static const struct panel_desc auo_g101evn010 = {
	1268	+ .modes = &auo_g101evn010_mode,
	1269	+ .num_modes = 1,
	1270	+ .bpc = 6,
	1271	+ .size = {
	1272	+ .width = 216,
	1273	+ .height = 135,
	1274	+ },
	1275	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1276	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1277	+};
	1278	+
1104	1279	static const struct drm_display_mode auo_g104sn02_mode = {
1105	1280	.clock = 40000,
1106	1281	.hdisplay = 800,
..	..	@@ -1111,7 +1286,6 @@
1111	1286	.vsync_start = 600 + 10,
1112	1287	.vsync_end = 600 + 10 + 35,
1113	1288	.vtotal = 600 + 10 + 35 + 2,
1114		- .vrefresh = 60,
1115	1289	};
1116	1290
1117	1291	static const struct panel_desc auo_g104sn02 = {
..	..	@@ -1122,6 +1296,30 @@
1122	1296	.width = 211,
1123	1297	.height = 158,
1124	1298	},
	1299	+};
	1300	+
	1301	+static const struct drm_display_mode auo_g121ean01_mode = {
	1302	+ .clock = 66700,
	1303	+ .hdisplay = 1280,
	1304	+ .hsync_start = 1280 + 58,
	1305	+ .hsync_end = 1280 + 58 + 8,
	1306	+ .htotal = 1280 + 58 + 8 + 70,
	1307	+ .vdisplay = 800,
	1308	+ .vsync_start = 800 + 6,
	1309	+ .vsync_end = 800 + 6 + 4,
	1310	+ .vtotal = 800 + 6 + 4 + 10,
	1311	+};
	1312	+
	1313	+static const struct panel_desc auo_g121ean01 = {
	1314	+ .modes = &auo_g121ean01_mode,
	1315	+ .num_modes = 1,
	1316	+ .bpc = 8,
	1317	+ .size = {
	1318	+ .width = 261,
	1319	+ .height = 163,
	1320	+ },
	1321	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1322	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1125	1323	};
1126	1324
1127	1325	static const struct display_timing auo_g133han01_timings = {
..	..	@@ -1151,6 +1349,31 @@
1151	1349	.unprepare = 1000,
1152	1350	},
1153	1351	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
	1352	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1353	+};
	1354	+
	1355	+static const struct drm_display_mode auo_g156xtn01_mode = {
	1356	+ .clock = 76000,
	1357	+ .hdisplay = 1366,
	1358	+ .hsync_start = 1366 + 33,
	1359	+ .hsync_end = 1366 + 33 + 67,
	1360	+ .htotal = 1560,
	1361	+ .vdisplay = 768,
	1362	+ .vsync_start = 768 + 4,
	1363	+ .vsync_end = 768 + 4 + 4,
	1364	+ .vtotal = 806,
	1365	+};
	1366	+
	1367	+static const struct panel_desc auo_g156xtn01 = {
	1368	+ .modes = &auo_g156xtn01_mode,
	1369	+ .num_modes = 1,
	1370	+ .bpc = 8,
	1371	+ .size = {
	1372	+ .width = 344,
	1373	+ .height = 194,
	1374	+ },
	1375	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1376	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1154	1377	};
1155	1378
1156	1379	static const struct display_timing auo_g185han01_timings = {
..	..	@@ -1180,6 +1403,37 @@
1180	1403	.unprepare = 1000,
1181	1404	},
1182	1405	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1406	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1407	+};
	1408	+
	1409	+static const struct display_timing auo_g190ean01_timings = {
	1410	+ .pixelclock = { 90000000, 108000000, 135000000 },
	1411	+ .hactive = { 1280, 1280, 1280 },
	1412	+ .hfront_porch = { 126, 184, 1266 },
	1413	+ .hback_porch = { 84, 122, 844 },
	1414	+ .hsync_len = { 70, 102, 704 },
	1415	+ .vactive = { 1024, 1024, 1024 },
	1416	+ .vfront_porch = { 4, 26, 76 },
	1417	+ .vback_porch = { 2, 8, 25 },
	1418	+ .vsync_len = { 2, 8, 25 },
	1419	+};
	1420	+
	1421	+static const struct panel_desc auo_g190ean01 = {
	1422	+ .timings = &auo_g190ean01_timings,
	1423	+ .num_timings = 1,
	1424	+ .bpc = 8,
	1425	+ .size = {
	1426	+ .width = 376,
	1427	+ .height = 301,
	1428	+ },
	1429	+ .delay = {
	1430	+ .prepare = 50,
	1431	+ .enable = 200,
	1432	+ .disable = 110,
	1433	+ .unprepare = 1000,
	1434	+ },
	1435	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1436	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1183	1437	};
1184	1438
1185	1439	static const struct display_timing auo_p320hvn03_timings = {
..	..	@@ -1208,6 +1462,7 @@
1208	1462	.unprepare = 500,
1209	1463	},
1210	1464	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1465	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1211	1466	};
1212	1467
1213	1468	static const struct drm_display_mode auo_t215hvn01_mode = {
..	..	@@ -1220,7 +1475,6 @@
1220	1475	.vsync_start = 1080 + 4,
1221	1476	.vsync_end = 1080 + 4 + 5,
1222	1477	.vtotal = 1080 + 4 + 5 + 36,
1223		- .vrefresh = 60,
1224	1478	};
1225	1479
1226	1480	static const struct panel_desc auo_t215hvn01 = {
..	..	@@ -1247,7 +1501,6 @@
1247	1501	.vsync_start = 600 + 17,
1248	1502	.vsync_end = 600 + 17 + 1,
1249	1503	.vtotal = 600 + 17 + 1 + 17,
1250		- .vrefresh = 60,
1251	1504	};
1252	1505
1253	1506	static const struct panel_desc avic_tm070ddh03 = {
..	..	@@ -1265,26 +1518,51 @@
1265	1518	},
1266	1519	};
1267	1520
	1521	+static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
	1522	+ .clock = 30000,
	1523	+ .hdisplay = 800,
	1524	+ .hsync_start = 800 + 40,
	1525	+ .hsync_end = 800 + 40 + 48,
	1526	+ .htotal = 800 + 40 + 48 + 40,
	1527	+ .vdisplay = 480,
	1528	+ .vsync_start = 480 + 13,
	1529	+ .vsync_end = 480 + 13 + 3,
	1530	+ .vtotal = 480 + 13 + 3 + 29,
	1531	+};
	1532	+
	1533	+static const struct panel_desc bananapi_s070wv20_ct16 = {
	1534	+ .modes = &bananapi_s070wv20_ct16_mode,
	1535	+ .num_modes = 1,
	1536	+ .bpc = 6,
	1537	+ .size = {
	1538	+ .width = 154,
	1539	+ .height = 86,
	1540	+ },
	1541	+};
	1542	+
1268	1543	static const struct drm_display_mode boe_hv070wsa_mode = {
1269		- .clock = 40800,
	1544	+ .clock = 42105,
1270	1545	.hdisplay = 1024,
1271		- .hsync_start = 1024 + 90,
1272		- .hsync_end = 1024 + 90 + 90,
1273		- .htotal = 1024 + 90 + 90 + 90,
	1546	+ .hsync_start = 1024 + 30,
	1547	+ .hsync_end = 1024 + 30 + 30,
	1548	+ .htotal = 1024 + 30 + 30 + 30,
1274	1549	.vdisplay = 600,
1275		- .vsync_start = 600 + 3,
1276		- .vsync_end = 600 + 3 + 4,
1277		- .vtotal = 600 + 3 + 4 + 3,
1278		- .vrefresh = 60,
	1550	+ .vsync_start = 600 + 10,
	1551	+ .vsync_end = 600 + 10 + 10,
	1552	+ .vtotal = 600 + 10 + 10 + 10,
1279	1553	};
1280	1554
1281	1555	static const struct panel_desc boe_hv070wsa = {
1282	1556	.modes = &boe_hv070wsa_mode,
1283	1557	.num_modes = 1,
	1558	+ .bpc = 8,
1284	1559	.size = {
1285	1560	.width = 154,
1286	1561	.height = 90,
1287	1562	},
	1563	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1564	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1565	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1288	1566	};
1289	1567
1290	1568	static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
..	..	@@ -1298,7 +1576,6 @@
1298	1576	.vsync_start = 800 + 3,
1299	1577	.vsync_end = 800 + 3 + 5,
1300	1578	.vtotal = 800 + 3 + 5 + 24,
1301		- .vrefresh = 60,
1302	1579	},
1303	1580	{
1304	1581	.clock = 57500,
..	..	@@ -1310,7 +1587,6 @@
1310	1587	.vsync_start = 800 + 3,
1311	1588	.vsync_end = 800 + 3 + 5,
1312	1589	.vtotal = 800 + 3 + 5 + 24,
1313		- .vrefresh = 48,
1314	1590	},
1315	1591	};
1316	1592
..	..	@@ -1329,6 +1605,214 @@
1329	1605	},
1330	1606	};
1331	1607
	1608	+/* Also used for boe_nv133fhm_n62 */
	1609	+static const struct drm_display_mode boe_nv133fhm_n61_modes = {
	1610	+ .clock = 147840,
	1611	+ .hdisplay = 1920,
	1612	+ .hsync_start = 1920 + 48,
	1613	+ .hsync_end = 1920 + 48 + 32,
	1614	+ .htotal = 1920 + 48 + 32 + 200,
	1615	+ .vdisplay = 1080,
	1616	+ .vsync_start = 1080 + 3,
	1617	+ .vsync_end = 1080 + 3 + 6,
	1618	+ .vtotal = 1080 + 3 + 6 + 31,
	1619	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1620	+};
	1621	+
	1622	+/* Also used for boe_nv133fhm_n62 */
	1623	+static const struct panel_desc boe_nv133fhm_n61 = {
	1624	+ .modes = &boe_nv133fhm_n61_modes,
	1625	+ .num_modes = 1,
	1626	+ .bpc = 6,
	1627	+ .size = {
	1628	+ .width = 294,
	1629	+ .height = 165,
	1630	+ },
	1631	+ .delay = {
	1632	+ /*
	1633	+ * When power is first given to the panel there's a short
	1634	+ * spike on the HPD line. It was explained that this spike
	1635	+ * was until the TCON data download was complete. On
	1636	+ * one system this was measured at 8 ms. We'll put 15 ms
	1637	+ * in the prepare delay just to be safe and take it away
	1638	+ * from the hpd_absent_delay (which would otherwise be 200 ms)
	1639	+ * to handle this. That means:
	1640	+ * - If HPD isn't hooked up you still have 200 ms delay.
	1641	+ * - If HPD is hooked up we won't try to look at it for the
	1642	+ * first 15 ms.
	1643	+ */
	1644	+ .prepare = 15,
	1645	+ .hpd_absent_delay = 185,
	1646	+
	1647	+ .unprepare = 500,
	1648	+ },
	1649	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	1650	+ .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
	1651	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	1652	+};
	1653	+
	1654	+static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
	1655	+ {
	1656	+ .clock = 148500,
	1657	+ .hdisplay = 1920,
	1658	+ .hsync_start = 1920 + 48,
	1659	+ .hsync_end = 1920 + 48 + 32,
	1660	+ .htotal = 2200,
	1661	+ .vdisplay = 1080,
	1662	+ .vsync_start = 1080 + 3,
	1663	+ .vsync_end = 1080 + 3 + 5,
	1664	+ .vtotal = 1125,
	1665	+ },
	1666	+};
	1667	+
	1668	+static const struct panel_desc boe_nv140fhmn49 = {
	1669	+ .modes = boe_nv140fhmn49_modes,
	1670	+ .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
	1671	+ .bpc = 6,
	1672	+ .size = {
	1673	+ .width = 309,
	1674	+ .height = 174,
	1675	+ },
	1676	+ .delay = {
	1677	+ .prepare = 210,
	1678	+ .enable = 50,
	1679	+ .unprepare = 160,
	1680	+ },
	1681	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1682	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	1683	+};
	1684	+
	1685	+static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
	1686	+ .clock = 9000,
	1687	+ .hdisplay = 480,
	1688	+ .hsync_start = 480 + 5,
	1689	+ .hsync_end = 480 + 5 + 5,
	1690	+ .htotal = 480 + 5 + 5 + 40,
	1691	+ .vdisplay = 272,
	1692	+ .vsync_start = 272 + 8,
	1693	+ .vsync_end = 272 + 8 + 8,
	1694	+ .vtotal = 272 + 8 + 8 + 8,
	1695	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1696	+};
	1697	+
	1698	+static const struct panel_desc cdtech_s043wq26h_ct7 = {
	1699	+ .modes = &cdtech_s043wq26h_ct7_mode,
	1700	+ .num_modes = 1,
	1701	+ .bpc = 8,
	1702	+ .size = {
	1703	+ .width = 95,
	1704	+ .height = 54,
	1705	+ },
	1706	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
	1707	+};
	1708	+
	1709	+/* S070PWS19HP-FC21 2017/04/22 */
	1710	+static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
	1711	+ .clock = 51200,
	1712	+ .hdisplay = 1024,
	1713	+ .hsync_start = 1024 + 160,
	1714	+ .hsync_end = 1024 + 160 + 20,
	1715	+ .htotal = 1024 + 160 + 20 + 140,
	1716	+ .vdisplay = 600,
	1717	+ .vsync_start = 600 + 12,
	1718	+ .vsync_end = 600 + 12 + 3,
	1719	+ .vtotal = 600 + 12 + 3 + 20,
	1720	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1721	+};
	1722	+
	1723	+static const struct panel_desc cdtech_s070pws19hp_fc21 = {
	1724	+ .modes = &cdtech_s070pws19hp_fc21_mode,
	1725	+ .num_modes = 1,
	1726	+ .bpc = 6,
	1727	+ .size = {
	1728	+ .width = 154,
	1729	+ .height = 86,
	1730	+ },
	1731	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1732	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	1733	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	1734	+};
	1735	+
	1736	+/* S070SWV29HG-DC44 2017/09/21 */
	1737	+static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
	1738	+ .clock = 33300,
	1739	+ .hdisplay = 800,
	1740	+ .hsync_start = 800 + 210,
	1741	+ .hsync_end = 800 + 210 + 2,
	1742	+ .htotal = 800 + 210 + 2 + 44,
	1743	+ .vdisplay = 480,
	1744	+ .vsync_start = 480 + 22,
	1745	+ .vsync_end = 480 + 22 + 2,
	1746	+ .vtotal = 480 + 22 + 2 + 21,
	1747	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1748	+};
	1749	+
	1750	+static const struct panel_desc cdtech_s070swv29hg_dc44 = {
	1751	+ .modes = &cdtech_s070swv29hg_dc44_mode,
	1752	+ .num_modes = 1,
	1753	+ .bpc = 6,
	1754	+ .size = {
	1755	+ .width = 154,
	1756	+ .height = 86,
	1757	+ },
	1758	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1759	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	1760	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	1761	+};
	1762	+
	1763	+static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
	1764	+ .clock = 35000,
	1765	+ .hdisplay = 800,
	1766	+ .hsync_start = 800 + 40,
	1767	+ .hsync_end = 800 + 40 + 40,
	1768	+ .htotal = 800 + 40 + 40 + 48,
	1769	+ .vdisplay = 480,
	1770	+ .vsync_start = 480 + 29,
	1771	+ .vsync_end = 480 + 29 + 13,
	1772	+ .vtotal = 480 + 29 + 13 + 3,
	1773	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1774	+};
	1775	+
	1776	+static const struct panel_desc cdtech_s070wv95_ct16 = {
	1777	+ .modes = &cdtech_s070wv95_ct16_mode,
	1778	+ .num_modes = 1,
	1779	+ .bpc = 8,
	1780	+ .size = {
	1781	+ .width = 154,
	1782	+ .height = 85,
	1783	+ },
	1784	+};
	1785	+
	1786	+static const struct display_timing chefree_ch101olhlwh_002_timing = {
	1787	+ .pixelclock = { 68900000, 71100000, 73400000 },
	1788	+ .hactive = { 1280, 1280, 1280 },
	1789	+ .hfront_porch = { 65, 80, 95 },
	1790	+ .hback_porch = { 64, 79, 94 },
	1791	+ .hsync_len = { 1, 1, 1 },
	1792	+ .vactive = { 800, 800, 800 },
	1793	+ .vfront_porch = { 7, 11, 14 },
	1794	+ .vback_porch = { 7, 11, 14 },
	1795	+ .vsync_len = { 1, 1, 1 },
	1796	+ .flags = DISPLAY_FLAGS_DE_HIGH,
	1797	+};
	1798	+
	1799	+static const struct panel_desc chefree_ch101olhlwh_002 = {
	1800	+ .timings = &chefree_ch101olhlwh_002_timing,
	1801	+ .num_timings = 1,
	1802	+ .bpc = 8,
	1803	+ .size = {
	1804	+ .width = 217,
	1805	+ .height = 135,
	1806	+ },
	1807	+ .delay = {
	1808	+ .enable = 200,
	1809	+ .disable = 200,
	1810	+ },
	1811	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1812	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1813	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1814	+};
	1815	+
1332	1816	static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1333	1817	.clock = 66770,
1334	1818	.hdisplay = 800,
..	..	@@ -1339,7 +1823,6 @@
1339	1823	.vsync_start = 1280 + 1,
1340	1824	.vsync_end = 1280 + 1 + 7,
1341	1825	.vtotal = 1280 + 1 + 7 + 15,
1342		- .vrefresh = 60,
1343	1826	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1344	1827	};
1345	1828
..	..	@@ -1351,6 +1834,9 @@
1351	1834	.width = 94,
1352	1835	.height = 150,
1353	1836	},
	1837	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1838	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1839	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1354	1840	};
1355	1841
1356	1842	static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
..	..	@@ -1363,7 +1849,6 @@
1363	1849	.vsync_start = 768 + 4,
1364	1850	.vsync_end = 768 + 4 + 4,
1365	1851	.vtotal = 768 + 4 + 4 + 4,
1366		- .vrefresh = 60,
1367	1852	};
1368	1853
1369	1854	static const struct panel_desc chunghwa_claa101wa01a = {
..	..	@@ -1374,6 +1859,9 @@
1374	1859	.width = 220,
1375	1860	.height = 120,
1376	1861	},
	1862	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1863	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1864	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1377	1865	};
1378	1866
1379	1867	static const struct drm_display_mode chunghwa_claa101wb01_mode = {
..	..	@@ -1386,7 +1874,6 @@
1386	1874	.vsync_start = 768 + 16,
1387	1875	.vsync_end = 768 + 16 + 8,
1388	1876	.vtotal = 768 + 16 + 8 + 16,
1389		- .vrefresh = 60,
1390	1877	};
1391	1878
1392	1879	static const struct panel_desc chunghwa_claa101wb01 = {
..	..	@@ -1397,6 +1884,9 @@
1397	1884	.width = 223,
1398	1885	.height = 125,
1399	1886	},
	1887	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1888	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1889	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1400	1890	};
1401	1891
1402	1892	static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
..	..	@@ -1409,7 +1899,6 @@
1409	1899	.vsync_start = 480 + 10,
1410	1900	.vsync_end = 480 + 10 + 2,
1411	1901	.vtotal = 480 + 10 + 2 + 33,
1412		- .vrefresh = 60,
1413	1902	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1414	1903	};
1415	1904
..	..	@@ -1422,7 +1911,7 @@
1422	1911	.height = 91,
1423	1912	},
1424	1913	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1425		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	1914	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1426	1915	};
1427	1916
1428	1917	static const struct display_timing dlc_dlc0700yzg_1_timing = {
..	..	@@ -1452,6 +1941,116 @@
1452	1941	.disable = 200,
1453	1942	},
1454	1943	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1944	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1945	+};
	1946	+
	1947	+static const struct display_timing dlc_dlc1010gig_timing = {
	1948	+ .pixelclock = { 68900000, 71100000, 73400000 },
	1949	+ .hactive = { 1280, 1280, 1280 },
	1950	+ .hfront_porch = { 43, 53, 63 },
	1951	+ .hback_porch = { 43, 53, 63 },
	1952	+ .hsync_len = { 44, 54, 64 },
	1953	+ .vactive = { 800, 800, 800 },
	1954	+ .vfront_porch = { 5, 8, 11 },
	1955	+ .vback_porch = { 5, 8, 11 },
	1956	+ .vsync_len = { 5, 7, 11 },
	1957	+ .flags = DISPLAY_FLAGS_DE_HIGH,
	1958	+};
	1959	+
	1960	+static const struct panel_desc dlc_dlc1010gig = {
	1961	+ .timings = &dlc_dlc1010gig_timing,
	1962	+ .num_timings = 1,
	1963	+ .bpc = 8,
	1964	+ .size = {
	1965	+ .width = 216,
	1966	+ .height = 135,
	1967	+ },
	1968	+ .delay = {
	1969	+ .prepare = 60,
	1970	+ .enable = 150,
	1971	+ .disable = 100,
	1972	+ .unprepare = 60,
	1973	+ },
	1974	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1975	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1976	+};
	1977	+
	1978	+static const struct drm_display_mode edt_et035012dm6_mode = {
	1979	+ .clock = 6500,
	1980	+ .hdisplay = 320,
	1981	+ .hsync_start = 320 + 20,
	1982	+ .hsync_end = 320 + 20 + 30,
	1983	+ .htotal = 320 + 20 + 68,
	1984	+ .vdisplay = 240,
	1985	+ .vsync_start = 240 + 4,
	1986	+ .vsync_end = 240 + 4 + 4,
	1987	+ .vtotal = 240 + 4 + 4 + 14,
	1988	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	1989	+};
	1990	+
	1991	+static const struct panel_desc edt_et035012dm6 = {
	1992	+ .modes = &edt_et035012dm6_mode,
	1993	+ .num_modes = 1,
	1994	+ .bpc = 8,
	1995	+ .size = {
	1996	+ .width = 70,
	1997	+ .height = 52,
	1998	+ },
	1999	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2000	+ .bus_flags = DRM_BUS_FLAG_DE_LOW \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
	2001	+};
	2002	+
	2003	+static const struct drm_display_mode edt_etm043080dh6gp_mode = {
	2004	+ .clock = 10870,
	2005	+ .hdisplay = 480,
	2006	+ .hsync_start = 480 + 8,
	2007	+ .hsync_end = 480 + 8 + 4,
	2008	+ .htotal = 480 + 8 + 4 + 41,
	2009	+
	2010	+ /*
	2011	+ * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
	2012	+ * fb_align
	2013	+ */
	2014	+
	2015	+ .vdisplay = 288,
	2016	+ .vsync_start = 288 + 2,
	2017	+ .vsync_end = 288 + 2 + 4,
	2018	+ .vtotal = 288 + 2 + 4 + 10,
	2019	+};
	2020	+
	2021	+static const struct panel_desc edt_etm043080dh6gp = {
	2022	+ .modes = &edt_etm043080dh6gp_mode,
	2023	+ .num_modes = 1,
	2024	+ .bpc = 8,
	2025	+ .size = {
	2026	+ .width = 100,
	2027	+ .height = 65,
	2028	+ },
	2029	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	2030	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	2031	+};
	2032	+
	2033	+static const struct drm_display_mode edt_etm0430g0dh6_mode = {
	2034	+ .clock = 9000,
	2035	+ .hdisplay = 480,
	2036	+ .hsync_start = 480 + 2,
	2037	+ .hsync_end = 480 + 2 + 41,
	2038	+ .htotal = 480 + 2 + 41 + 2,
	2039	+ .vdisplay = 272,
	2040	+ .vsync_start = 272 + 2,
	2041	+ .vsync_end = 272 + 2 + 10,
	2042	+ .vtotal = 272 + 2 + 10 + 2,
	2043	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2044	+};
	2045	+
	2046	+static const struct panel_desc edt_etm0430g0dh6 = {
	2047	+ .modes = &edt_etm0430g0dh6_mode,
	2048	+ .num_modes = 1,
	2049	+ .bpc = 6,
	2050	+ .size = {
	2051	+ .width = 95,
	2052	+ .height = 54,
	2053	+ },
1455	2054	};
1456	2055
1457	2056	static const struct drm_display_mode edt_et057090dhu_mode = {
..	..	@@ -1464,7 +2063,6 @@
1464	2063	.vsync_start = 480 + 10,
1465	2064	.vsync_end = 480 + 10 + 3,
1466	2065	.vtotal = 480 + 10 + 3 + 32,
1467		- .vrefresh = 60,
1468	2066	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1469	2067	};
1470	2068
..	..	@@ -1477,7 +2075,8 @@
1477	2075	.height = 86,
1478	2076	},
1479	2077	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1480		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_NEGEDGE,
	2078	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
	2079	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
1481	2080	};
1482	2081
1483	2082	static const struct drm_display_mode edt_etm0700g0dh6_mode = {
..	..	@@ -1490,7 +2089,6 @@
1490	2089	.vsync_start = 480 + 10,
1491	2090	.vsync_end = 480 + 10 + 2,
1492	2091	.vtotal = 480 + 10 + 2 + 33,
1493		- .vrefresh = 60,
1494	2092	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
1495	2093	};
1496	2094
..	..	@@ -1503,7 +2101,7 @@
1503	2101	.height = 91,
1504	2102	},
1505	2103	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1506		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_NEGEDGE,
	2104	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1507	2105	};
1508	2106
1509	2107	static const struct panel_desc edt_etm0700g0bdh6 = {
..	..	@@ -1515,7 +2113,34 @@
1515	2113	.height = 91,
1516	2114	},
1517	2115	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1518		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	2116	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
	2117	+};
	2118	+
	2119	+static const struct display_timing evervision_vgg804821_timing = {
	2120	+ .pixelclock = { 27600000, 33300000, 50000000 },
	2121	+ .hactive = { 800, 800, 800 },
	2122	+ .hfront_porch = { 40, 66, 70 },
	2123	+ .hback_porch = { 40, 67, 70 },
	2124	+ .hsync_len = { 40, 67, 70 },
	2125	+ .vactive = { 480, 480, 480 },
	2126	+ .vfront_porch = { 6, 10, 10 },
	2127	+ .vback_porch = { 7, 11, 11 },
	2128	+ .vsync_len = { 7, 11, 11 },
	2129	+ .flags = DISPLAY_FLAGS_HSYNC_HIGH \| DISPLAY_FLAGS_VSYNC_HIGH \|
	2130	+ DISPLAY_FLAGS_DE_HIGH \| DISPLAY_FLAGS_PIXDATA_NEGEDGE \|
	2131	+ DISPLAY_FLAGS_SYNC_NEGEDGE,
	2132	+};
	2133	+
	2134	+static const struct panel_desc evervision_vgg804821 = {
	2135	+ .timings = &evervision_vgg804821_timing,
	2136	+ .num_timings = 1,
	2137	+ .bpc = 8,
	2138	+ .size = {
	2139	+ .width = 108,
	2140	+ .height = 64,
	2141	+ },
	2142	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2143	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1519	2144	};
1520	2145
1521	2146	static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
..	..	@@ -1528,7 +2153,6 @@
1528	2153	.vsync_start = 480 + 37,
1529	2154	.vsync_end = 480 + 37 + 2,
1530	2155	.vtotal = 480 + 37 + 2 + 8,
1531		- .vrefresh = 60,
1532	2156	};
1533	2157
1534	2158	static const struct panel_desc foxlink_fl500wvr00_a0t = {
..	..	@@ -1542,6 +2166,68 @@
1542	2166	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1543	2167	};
1544	2168
	2169	+static const struct drm_display_mode frida_frd350h54004_modes[] = {
	2170	+ { /* 60 Hz */
	2171	+ .clock = 6000,
	2172	+ .hdisplay = 320,
	2173	+ .hsync_start = 320 + 44,
	2174	+ .hsync_end = 320 + 44 + 16,
	2175	+ .htotal = 320 + 44 + 16 + 20,
	2176	+ .vdisplay = 240,
	2177	+ .vsync_start = 240 + 2,
	2178	+ .vsync_end = 240 + 2 + 6,
	2179	+ .vtotal = 240 + 2 + 6 + 2,
	2180	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2181	+ },
	2182	+ { /* 50 Hz */
	2183	+ .clock = 5400,
	2184	+ .hdisplay = 320,
	2185	+ .hsync_start = 320 + 56,
	2186	+ .hsync_end = 320 + 56 + 16,
	2187	+ .htotal = 320 + 56 + 16 + 40,
	2188	+ .vdisplay = 240,
	2189	+ .vsync_start = 240 + 2,
	2190	+ .vsync_end = 240 + 2 + 6,
	2191	+ .vtotal = 240 + 2 + 6 + 2,
	2192	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2193	+ },
	2194	+};
	2195	+
	2196	+static const struct panel_desc frida_frd350h54004 = {
	2197	+ .modes = frida_frd350h54004_modes,
	2198	+ .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
	2199	+ .bpc = 8,
	2200	+ .size = {
	2201	+ .width = 77,
	2202	+ .height = 64,
	2203	+ },
	2204	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2205	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	2206	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	2207	+};
	2208	+
	2209	+static const struct drm_display_mode friendlyarm_hd702e_mode = {
	2210	+ .clock = 67185,
	2211	+ .hdisplay = 800,
	2212	+ .hsync_start = 800 + 20,
	2213	+ .hsync_end = 800 + 20 + 24,
	2214	+ .htotal = 800 + 20 + 24 + 20,
	2215	+ .vdisplay = 1280,
	2216	+ .vsync_start = 1280 + 4,
	2217	+ .vsync_end = 1280 + 4 + 8,
	2218	+ .vtotal = 1280 + 4 + 8 + 4,
	2219	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	2220	+};
	2221	+
	2222	+static const struct panel_desc friendlyarm_hd702e = {
	2223	+ .modes = &friendlyarm_hd702e_mode,
	2224	+ .num_modes = 1,
	2225	+ .size = {
	2226	+ .width = 94,
	2227	+ .height = 151,
	2228	+ },
	2229	+};
	2230	+
1545	2231	static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1546	2232	.clock = 9000,
1547	2233	.hdisplay = 480,
..	..	@@ -1552,7 +2238,6 @@
1552	2238	.vsync_start = 272 + 8,
1553	2239	.vsync_end = 272 + 8 + 1,
1554	2240	.vtotal = 272 + 8 + 1 + 8,
1555		- .vrefresh = 60,
1556	2241	};
1557	2242
1558	2243	static const struct panel_desc giantplus_gpg482739qs5 = {
..	..	@@ -1564,6 +2249,31 @@
1564	2249	.height = 54,
1565	2250	},
1566	2251	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2252	+};
	2253	+
	2254	+static const struct display_timing giantplus_gpm940b0_timing = {
	2255	+ .pixelclock = { 13500000, 27000000, 27500000 },
	2256	+ .hactive = { 320, 320, 320 },
	2257	+ .hfront_porch = { 14, 686, 718 },
	2258	+ .hback_porch = { 50, 70, 255 },
	2259	+ .hsync_len = { 1, 1, 1 },
	2260	+ .vactive = { 240, 240, 240 },
	2261	+ .vfront_porch = { 1, 1, 179 },
	2262	+ .vback_porch = { 1, 21, 31 },
	2263	+ .vsync_len = { 1, 1, 6 },
	2264	+ .flags = DISPLAY_FLAGS_HSYNC_LOW \| DISPLAY_FLAGS_VSYNC_LOW,
	2265	+};
	2266	+
	2267	+static const struct panel_desc giantplus_gpm940b0 = {
	2268	+ .timings = &giantplus_gpm940b0_timing,
	2269	+ .num_timings = 1,
	2270	+ .bpc = 8,
	2271	+ .size = {
	2272	+ .width = 60,
	2273	+ .height = 45,
	2274	+ },
	2275	+ .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
	2276	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1567	2277	};
1568	2278
1569	2279	static const struct display_timing hannstar_hsd070pww1_timing = {
..	..	@@ -1593,6 +2303,7 @@
1593	2303	.height = 94,
1594	2304	},
1595	2305	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2306	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1596	2307	};
1597	2308
1598	2309	static const struct display_timing hannstar_hsd100pxn1_timing = {
..	..	@@ -1617,6 +2328,7 @@
1617	2328	.height = 152,
1618	2329	},
1619	2330	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2331	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1620	2332	};
1621	2333
1622	2334	static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
..	..	@@ -1629,7 +2341,6 @@
1629	2341	.vsync_start = 480 + 16,
1630	2342	.vsync_end = 480 + 16 + 13,
1631	2343	.vtotal = 480 + 16 + 13 + 16,
1632		- .vrefresh = 60,
1633	2344	};
1634	2345
1635	2346	static const struct panel_desc hitachi_tx23d38vm0caa = {
..	..	@@ -1656,7 +2367,6 @@
1656	2367	.vsync_start = 272 + 2,
1657	2368	.vsync_end = 272 + 2 + 10,
1658	2369	.vtotal = 272 + 2 + 10 + 2,
1659		- .vrefresh = 60,
1660	2370	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
1661	2371	};
1662	2372
..	..	@@ -1669,7 +2379,7 @@
1669	2379	.height = 54,
1670	2380	},
1671	2381	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1672		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	2382	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1673	2383	};
1674	2384
1675	2385	static const struct drm_display_mode innolux_at070tn92_mode = {
..	..	@@ -1682,7 +2392,6 @@
1682	2392	.vsync_start = 480 + 22,
1683	2393	.vsync_end = 480 + 22 + 10,
1684	2394	.vtotal = 480 + 22 + 23 + 10,
1685		- .vrefresh = 60,
1686	2395	};
1687	2396
1688	2397	static const struct panel_desc innolux_at070tn92 = {
..	..	@@ -1711,7 +2420,7 @@
1711	2420	static const struct panel_desc innolux_g070y2_l01 = {
1712	2421	.timings = &innolux_g070y2_l01_timing,
1713	2422	.num_timings = 1,
1714		- .bpc = 6,
	2423	+ .bpc = 8,
1715	2424	.size = {
1716	2425	.width = 152,
1717	2426	.height = 91,
..	..	@@ -1723,6 +2432,8 @@
1723	2432	.unprepare = 800,
1724	2433	},
1725	2434	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2435	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	2436	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1726	2437	};
1727	2438
1728	2439	static const struct display_timing innolux_g101ice_l01_timing = {
..	..	@@ -1751,6 +2462,7 @@
1751	2462	.disable = 200,
1752	2463	},
1753	2464	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2465	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1754	2466	};
1755	2467
1756	2468	static const struct display_timing innolux_g121i1_l01_timing = {
..	..	@@ -1777,7 +2489,8 @@
1777	2489	.enable = 200,
1778	2490	.disable = 20,
1779	2491	},
1780		- .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2492	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2493	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1781	2494	};
1782	2495
1783	2496	static const struct drm_display_mode innolux_g121x1_l03_mode = {
..	..	@@ -1790,7 +2503,6 @@
1790	2503	.vsync_start = 768 + 38,
1791	2504	.vsync_end = 768 + 38 + 1,
1792	2505	.vtotal = 768 + 38 + 1 + 0,
1793		- .vrefresh = 60,
1794	2506	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
1795	2507	};
1796	2508
..	..	@@ -1809,23 +2521,32 @@
1809	2521	},
1810	2522	};
1811	2523
1812		-static const struct drm_display_mode innolux_n116bge_mode = {
1813		- .clock = 76420,
1814		- .hdisplay = 1366,
1815		- .hsync_start = 1366 + 136,
1816		- .hsync_end = 1366 + 136 + 30,
1817		- .htotal = 1366 + 136 + 30 + 60,
1818		- .vdisplay = 768,
1819		- .vsync_start = 768 + 8,
1820		- .vsync_end = 768 + 8 + 12,
1821		- .vtotal = 768 + 8 + 12 + 12,
1822		- .vrefresh = 60,
1823		- .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2524	+/*
	2525	+ * Datasheet specifies that at 60 Hz refresh rate:
	2526	+ * - total horizontal time: { 1506, 1592, 1716 }
	2527	+ * - total vertical time: { 788, 800, 868 }
	2528	+ *
	2529	+ * ...but doesn't go into exactly how that should be split into a front
	2530	+ * porch, back porch, or sync length. For now we'll leave a single setting
	2531	+ * here which allows a bit of tweaking of the pixel clock at the expense of
	2532	+ * refresh rate.
	2533	+ */
	2534	+static const struct display_timing innolux_n116bge_timing = {
	2535	+ .pixelclock = { 72600000, 76420000, 80240000 },
	2536	+ .hactive = { 1366, 1366, 1366 },
	2537	+ .hfront_porch = { 136, 136, 136 },
	2538	+ .hback_porch = { 60, 60, 60 },
	2539	+ .hsync_len = { 30, 30, 30 },
	2540	+ .vactive = { 768, 768, 768 },
	2541	+ .vfront_porch = { 8, 8, 8 },
	2542	+ .vback_porch = { 12, 12, 12 },
	2543	+ .vsync_len = { 12, 12, 12 },
	2544	+ .flags = DISPLAY_FLAGS_VSYNC_LOW \| DISPLAY_FLAGS_HSYNC_LOW,
1824	2545	};
1825	2546
1826	2547	static const struct panel_desc innolux_n116bge = {
1827		- .modes = &innolux_n116bge_mode,
1828		- .num_modes = 1,
	2548	+ .timings = &innolux_n116bge_timing,
	2549	+ .num_timings = 1,
1829	2550	.bpc = 6,
1830	2551	.size = {
1831	2552	.width = 256,
..	..	@@ -1843,7 +2564,6 @@
1843	2564	.vsync_start = 768 + 2,
1844	2565	.vsync_end = 768 + 2 + 6,
1845	2566	.vtotal = 768 + 2 + 6 + 12,
1846		- .vrefresh = 60,
1847	2567	};
1848	2568
1849	2569	static const struct panel_desc innolux_n156bge_l21 = {
..	..	@@ -1854,9 +2574,12 @@
1854	2574	.width = 344,
1855	2575	.height = 193,
1856	2576	},
	2577	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2578	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	2579	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1857	2580	};
1858	2581
1859		-static const struct drm_display_mode innolux_tv123wam_mode = {
	2582	+static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1860	2583	.clock = 206016,
1861	2584	.hdisplay = 2160,
1862	2585	.hsync_start = 2160 + 48,
..	..	@@ -1866,19 +2589,19 @@
1866	2589	.vsync_start = 1440 + 3,
1867	2590	.vsync_end = 1440 + 3 + 10,
1868	2591	.vtotal = 1440 + 3 + 10 + 27,
1869		- .vrefresh = 60,
1870	2592	.flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
1871	2593	};
1872	2594
1873		-static const struct panel_desc innolux_tv123wam = {
1874		- .modes = &innolux_tv123wam_mode,
	2595	+static const struct panel_desc innolux_p120zdg_bf1 = {
	2596	+ .modes = &innolux_p120zdg_bf1_mode,
1875	2597	.num_modes = 1,
1876	2598	.bpc = 8,
1877	2599	.size = {
1878		- .width = 259,
1879		- .height = 173,
	2600	+ .width = 254,
	2601	+ .height = 169,
1880	2602	},
1881	2603	.delay = {
	2604	+ .hpd_absent_delay = 200,
1882	2605	.unprepare = 500,
1883	2606	},
1884	2607	};
..	..	@@ -1893,7 +2616,6 @@
1893	2616	.vsync_start = 600 + 16,
1894	2617	.vsync_end = 600 + 16 + 4,
1895	2618	.vtotal = 600 + 16 + 4 + 16,
1896		- .vrefresh = 60,
1897	2619	};
1898	2620
1899	2621	static const struct panel_desc innolux_zj070na_01p = {
..	..	@@ -1904,6 +2626,118 @@
1904	2626	.width = 154,
1905	2627	.height = 90,
1906	2628	},
	2629	+};
	2630	+
	2631	+static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
	2632	+ .clock = 138778,
	2633	+ .hdisplay = 1920,
	2634	+ .hsync_start = 1920 + 24,
	2635	+ .hsync_end = 1920 + 24 + 48,
	2636	+ .htotal = 1920 + 24 + 48 + 88,
	2637	+ .vdisplay = 1080,
	2638	+ .vsync_start = 1080 + 3,
	2639	+ .vsync_end = 1080 + 3 + 12,
	2640	+ .vtotal = 1080 + 3 + 12 + 17,
	2641	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	2642	+};
	2643	+
	2644	+static const struct panel_desc ivo_m133nwf4_r0 = {
	2645	+ .modes = &ivo_m133nwf4_r0_mode,
	2646	+ .num_modes = 1,
	2647	+ .bpc = 8,
	2648	+ .size = {
	2649	+ .width = 294,
	2650	+ .height = 165,
	2651	+ },
	2652	+ .delay = {
	2653	+ .hpd_absent_delay = 200,
	2654	+ .unprepare = 500,
	2655	+ },
	2656	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2657	+ .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
	2658	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	2659	+};
	2660	+
	2661	+static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
	2662	+ .clock = 81000,
	2663	+ .hdisplay = 1366,
	2664	+ .hsync_start = 1366 + 40,
	2665	+ .hsync_end = 1366 + 40 + 32,
	2666	+ .htotal = 1366 + 40 + 32 + 62,
	2667	+ .vdisplay = 768,
	2668	+ .vsync_start = 768 + 5,
	2669	+ .vsync_end = 768 + 5 + 5,
	2670	+ .vtotal = 768 + 5 + 5 + 122,
	2671	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	2672	+};
	2673	+
	2674	+static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
	2675	+ .modes = &kingdisplay_kd116n21_30nv_a010_mode,
	2676	+ .num_modes = 1,
	2677	+ .bpc = 6,
	2678	+ .size = {
	2679	+ .width = 256,
	2680	+ .height = 144,
	2681	+ },
	2682	+ .delay = {
	2683	+ .hpd_absent_delay = 200,
	2684	+ },
	2685	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	2686	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	2687	+};
	2688	+
	2689	+static const struct display_timing koe_tx14d24vm1bpa_timing = {
	2690	+ .pixelclock = { 5580000, 5850000, 6200000 },
	2691	+ .hactive = { 320, 320, 320 },
	2692	+ .hfront_porch = { 30, 30, 30 },
	2693	+ .hback_porch = { 30, 30, 30 },
	2694	+ .hsync_len = { 1, 5, 17 },
	2695	+ .vactive = { 240, 240, 240 },
	2696	+ .vfront_porch = { 6, 6, 6 },
	2697	+ .vback_porch = { 5, 5, 5 },
	2698	+ .vsync_len = { 1, 2, 11 },
	2699	+ .flags = DISPLAY_FLAGS_DE_HIGH,
	2700	+};
	2701	+
	2702	+static const struct panel_desc koe_tx14d24vm1bpa = {
	2703	+ .timings = &koe_tx14d24vm1bpa_timing,
	2704	+ .num_timings = 1,
	2705	+ .bpc = 6,
	2706	+ .size = {
	2707	+ .width = 115,
	2708	+ .height = 86,
	2709	+ },
	2710	+};
	2711	+
	2712	+static const struct display_timing koe_tx26d202vm0bwa_timing = {
	2713	+ .pixelclock = { 151820000, 156720000, 159780000 },
	2714	+ .hactive = { 1920, 1920, 1920 },
	2715	+ .hfront_porch = { 105, 130, 142 },
	2716	+ .hback_porch = { 45, 70, 82 },
	2717	+ .hsync_len = { 30, 30, 30 },
	2718	+ .vactive = { 1200, 1200, 1200},
	2719	+ .vfront_porch = { 3, 5, 10 },
	2720	+ .vback_porch = { 2, 5, 10 },
	2721	+ .vsync_len = { 5, 5, 5 },
	2722	+};
	2723	+
	2724	+static const struct panel_desc koe_tx26d202vm0bwa = {
	2725	+ .timings = &koe_tx26d202vm0bwa_timing,
	2726	+ .num_timings = 1,
	2727	+ .bpc = 8,
	2728	+ .size = {
	2729	+ .width = 217,
	2730	+ .height = 136,
	2731	+ },
	2732	+ .delay = {
	2733	+ .prepare = 1000,
	2734	+ .enable = 1000,
	2735	+ .unprepare = 1000,
	2736	+ .disable = 1000,
	2737	+ },
	2738	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2739	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	2740	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1907	2741	};
1908	2742
1909	2743	static const struct display_timing koe_tx31d200vm0baa_timing = {
..	..	@@ -1928,6 +2762,7 @@
1928	2762	.height = 109,
1929	2763	},
1930	2764	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2765	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1931	2766	};
1932	2767
1933	2768	static const struct display_timing kyo_tcg121xglp_timing = {
..	..	@@ -1952,6 +2787,30 @@
1952	2787	.height = 184,
1953	2788	},
1954	2789	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2790	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	2791	+};
	2792	+
	2793	+static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
	2794	+ .clock = 7000,
	2795	+ .hdisplay = 320,
	2796	+ .hsync_start = 320 + 20,
	2797	+ .hsync_end = 320 + 20 + 30,
	2798	+ .htotal = 320 + 20 + 30 + 38,
	2799	+ .vdisplay = 240,
	2800	+ .vsync_start = 240 + 4,
	2801	+ .vsync_end = 240 + 4 + 3,
	2802	+ .vtotal = 240 + 4 + 3 + 15,
	2803	+};
	2804	+
	2805	+static const struct panel_desc lemaker_bl035_rgb_002 = {
	2806	+ .modes = &lemaker_bl035_rgb_002_mode,
	2807	+ .num_modes = 1,
	2808	+ .size = {
	2809	+ .width = 70,
	2810	+ .height = 52,
	2811	+ },
	2812	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2813	+ .bus_flags = DRM_BUS_FLAG_DE_LOW,
1955	2814	};
1956	2815
1957	2816	static const struct drm_display_mode lg_lb070wv8_mode = {
..	..	@@ -1964,7 +2823,6 @@
1964	2823	.vsync_start = 480 + 10,
1965	2824	.vsync_end = 480 + 10 + 25,
1966	2825	.vtotal = 480 + 10 + 25 + 10,
1967		- .vrefresh = 60,
1968	2826	};
1969	2827
1970	2828	static const struct panel_desc lg_lb070wv8 = {
..	..	@@ -1976,6 +2834,7 @@
1976	2834	.height = 91,
1977	2835	},
1978	2836	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2837	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1979	2838	};
1980	2839
1981	2840	static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
..	..	@@ -1988,7 +2847,6 @@
1988	2847	.vsync_start = 2048 + 8,
1989	2848	.vsync_end = 2048 + 8 + 4,
1990	2849	.vtotal = 2048 + 8 + 4 + 8,
1991		- .vrefresh = 60,
1992	2850	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1993	2851	};
1994	2852
..	..	@@ -2011,7 +2869,6 @@
2011	2869	.vsync_start = 1536 + 3,
2012	2870	.vsync_end = 1536 + 3 + 1,
2013	2871	.vtotal = 1536 + 3 + 1 + 9,
2014		- .vrefresh = 60,
2015	2872	};
2016	2873
2017	2874	static const struct panel_desc lg_lp097qx1_spa1 = {
..	..	@@ -2033,7 +2890,6 @@
2033	2890	.vsync_start = 1280 + 4,
2034	2891	.vsync_end = 1280 + 4 + 4,
2035	2892	.vtotal = 1280 + 4 + 4 + 12,
2036		- .vrefresh = 60,
2037	2893	};
2038	2894
2039	2895	static const struct panel_desc lg_lp120up1 = {
..	..	@@ -2044,6 +2900,7 @@
2044	2900	.width = 267,
2045	2901	.height = 183,
2046	2902	},
	2903	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
2047	2904	};
2048	2905
2049	2906	static const struct drm_display_mode lg_lp129qe_mode = {
..	..	@@ -2056,7 +2913,6 @@
2056	2913	.vsync_start = 1700 + 3,
2057	2914	.vsync_end = 1700 + 3 + 10,
2058	2915	.vtotal = 1700 + 3 + 10 + 36,
2059		- .vrefresh = 60,
2060	2916	};
2061	2917
2062	2918	static const struct panel_desc lg_lp129qe = {
..	..	@@ -2069,6 +2925,64 @@
2069	2925	},
2070	2926	};
2071	2927
	2928	+static const struct display_timing logictechno_lt161010_2nh_timing = {
	2929	+ .pixelclock = { 26400000, 33300000, 46800000 },
	2930	+ .hactive = { 800, 800, 800 },
	2931	+ .hfront_porch = { 16, 210, 354 },
	2932	+ .hback_porch = { 46, 46, 46 },
	2933	+ .hsync_len = { 1, 20, 40 },
	2934	+ .vactive = { 480, 480, 480 },
	2935	+ .vfront_porch = { 7, 22, 147 },
	2936	+ .vback_porch = { 23, 23, 23 },
	2937	+ .vsync_len = { 1, 10, 20 },
	2938	+ .flags = DISPLAY_FLAGS_HSYNC_LOW \| DISPLAY_FLAGS_VSYNC_LOW \|
	2939	+ DISPLAY_FLAGS_DE_HIGH \| DISPLAY_FLAGS_PIXDATA_POSEDGE \|
	2940	+ DISPLAY_FLAGS_SYNC_POSEDGE,
	2941	+};
	2942	+
	2943	+static const struct panel_desc logictechno_lt161010_2nh = {
	2944	+ .timings = &logictechno_lt161010_2nh_timing,
	2945	+ .num_timings = 1,
	2946	+ .bpc = 6,
	2947	+ .size = {
	2948	+ .width = 154,
	2949	+ .height = 86,
	2950	+ },
	2951	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	2952	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \|
	2953	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	2954	+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
	2955	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	2956	+};
	2957	+
	2958	+static const struct display_timing logictechno_lt170410_2whc_timing = {
	2959	+ .pixelclock = { 68900000, 71100000, 73400000 },
	2960	+ .hactive = { 1280, 1280, 1280 },
	2961	+ .hfront_porch = { 23, 60, 71 },
	2962	+ .hback_porch = { 23, 60, 71 },
	2963	+ .hsync_len = { 15, 40, 47 },
	2964	+ .vactive = { 800, 800, 800 },
	2965	+ .vfront_porch = { 5, 7, 10 },
	2966	+ .vback_porch = { 5, 7, 10 },
	2967	+ .vsync_len = { 6, 9, 12 },
	2968	+ .flags = DISPLAY_FLAGS_HSYNC_LOW \| DISPLAY_FLAGS_VSYNC_LOW \|
	2969	+ DISPLAY_FLAGS_DE_HIGH \| DISPLAY_FLAGS_PIXDATA_POSEDGE \|
	2970	+ DISPLAY_FLAGS_SYNC_POSEDGE,
	2971	+};
	2972	+
	2973	+static const struct panel_desc logictechno_lt170410_2whc = {
	2974	+ .timings = &logictechno_lt170410_2whc_timing,
	2975	+ .num_timings = 1,
	2976	+ .bpc = 8,
	2977	+ .size = {
	2978	+ .width = 217,
	2979	+ .height = 136,
	2980	+ },
	2981	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2982	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	2983	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	2984	+};
	2985	+
2072	2986	static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2073	2987	.clock = 30400,
2074	2988	.hdisplay = 800,
..	..	@@ -2079,8 +2993,41 @@
2079	2993	.vsync_start = 480 + 0,
2080	2994	.vsync_end = 480 + 48 + 1,
2081	2995	.vtotal = 480 + 48 + 1 + 0,
2082		- .vrefresh = 60,
2083	2996	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2997	+};
	2998	+
	2999	+static const struct drm_display_mode logicpd_type_28_mode = {
	3000	+ .clock = 9107,
	3001	+ .hdisplay = 480,
	3002	+ .hsync_start = 480 + 3,
	3003	+ .hsync_end = 480 + 3 + 42,
	3004	+ .htotal = 480 + 3 + 42 + 2,
	3005	+
	3006	+ .vdisplay = 272,
	3007	+ .vsync_start = 272 + 2,
	3008	+ .vsync_end = 272 + 2 + 11,
	3009	+ .vtotal = 272 + 2 + 11 + 3,
	3010	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	3011	+};
	3012	+
	3013	+static const struct panel_desc logicpd_type_28 = {
	3014	+ .modes = &logicpd_type_28_mode,
	3015	+ .num_modes = 1,
	3016	+ .bpc = 8,
	3017	+ .size = {
	3018	+ .width = 105,
	3019	+ .height = 67,
	3020	+ },
	3021	+ .delay = {
	3022	+ .prepare = 200,
	3023	+ .enable = 200,
	3024	+ .unprepare = 200,
	3025	+ .disable = 200,
	3026	+ },
	3027	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3028	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE \|
	3029	+ DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
	3030	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
2084	3031	};
2085	3032
2086	3033	static const struct panel_desc mitsubishi_aa070mc01 = {
..	..	@@ -2098,6 +3045,7 @@
2098	3045	.disable = 400,
2099	3046	},
2100	3047	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3048	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2101	3049	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2102	3050	};
2103	3051
..	..	@@ -2126,6 +3074,7 @@
2126	3074	.disable = 50,
2127	3075	},
2128	3076	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3077	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2129	3078	};
2130	3079
2131	3080	static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
..	..	@@ -2138,7 +3087,6 @@
2138	3087	.vsync_start = 272 + 2,
2139	3088	.vsync_end = 272 + 2 + 4,
2140	3089	.vtotal = 272 + 2 + 4 + 2,
2141		- .vrefresh = 74,
2142	3090	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2143	3091	};
2144	3092
..	..	@@ -2151,7 +3099,7 @@
2151	3099	.height = 54,
2152	3100	},
2153	3101	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2154		- .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
	3102	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2155	3103	};
2156	3104
2157	3105	static const struct drm_display_mode netron_dy_e231732_mode = {
..	..	@@ -2164,7 +3112,6 @@
2164	3112	.vsync_start = 600 + 127,
2165	3113	.vsync_end = 600 + 127 + 20,
2166	3114	.vtotal = 600 + 127 + 20 + 3,
2167		- .vrefresh = 60,
2168	3115	};
2169	3116
2170	3117	static const struct panel_desc netron_dy_e231732 = {
..	..	@@ -2177,6 +3124,49 @@
2177	3124	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2178	3125	};
2179	3126
	3127	+static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
	3128	+ {
	3129	+ .clock = 138500,
	3130	+ .hdisplay = 1920,
	3131	+ .hsync_start = 1920 + 48,
	3132	+ .hsync_end = 1920 + 48 + 32,
	3133	+ .htotal = 1920 + 48 + 32 + 80,
	3134	+ .vdisplay = 1080,
	3135	+ .vsync_start = 1080 + 3,
	3136	+ .vsync_end = 1080 + 3 + 5,
	3137	+ .vtotal = 1080 + 3 + 5 + 23,
	3138	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3139	+ }, {
	3140	+ .clock = 110920,
	3141	+ .hdisplay = 1920,
	3142	+ .hsync_start = 1920 + 48,
	3143	+ .hsync_end = 1920 + 48 + 32,
	3144	+ .htotal = 1920 + 48 + 32 + 80,
	3145	+ .vdisplay = 1080,
	3146	+ .vsync_start = 1080 + 3,
	3147	+ .vsync_end = 1080 + 3 + 5,
	3148	+ .vtotal = 1080 + 3 + 5 + 23,
	3149	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3150	+ }
	3151	+};
	3152	+
	3153	+static const struct panel_desc neweast_wjfh116008a = {
	3154	+ .modes = neweast_wjfh116008a_modes,
	3155	+ .num_modes = 2,
	3156	+ .bpc = 6,
	3157	+ .size = {
	3158	+ .width = 260,
	3159	+ .height = 150,
	3160	+ },
	3161	+ .delay = {
	3162	+ .prepare = 110,
	3163	+ .enable = 20,
	3164	+ .unprepare = 500,
	3165	+ },
	3166	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	3167	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	3168	+};
	3169	+
2180	3170	static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2181	3171	.clock = 9000,
2182	3172	.hdisplay = 480,
..	..	@@ -2187,7 +3177,6 @@
2187	3177	.vsync_start = 272 + 2,
2188	3178	.vsync_end = 272 + 2 + 10,
2189	3179	.vtotal = 272 + 2 + 10 + 2,
2190		- .vrefresh = 60,
2191	3180	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2192	3181	};
2193	3182
..	..	@@ -2200,8 +3189,9 @@
2200	3189	.height = 54,
2201	3190	},
2202	3191	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2203		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE \|
2204		- DRM_BUS_FLAG_SYNC_POSEDGE,
	3192	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE \|
	3193	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3194	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
2205	3195	};
2206	3196
2207	3197	static const struct display_timing nlt_nl192108ac18_02d_timing = {
..	..	@@ -2228,6 +3218,7 @@
2228	3218	.unprepare = 500,
2229	3219	},
2230	3220	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3221	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2231	3222	};
2232	3223
2233	3224	static const struct drm_display_mode nvd_9128_mode = {
..	..	@@ -2251,6 +3242,7 @@
2251	3242	.height = 88,
2252	3243	},
2253	3244	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3245	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2254	3246	};
2255	3247
2256	3248	static const struct display_timing okaya_rs800480t_7x0gp_timing = {
..	..	@@ -2293,7 +3285,6 @@
2293	3285	.vsync_start = 272 + 8,
2294	3286	.vsync_end = 272 + 8 + 5,
2295	3287	.vtotal = 272 + 8 + 5 + 3,
2296		- .vrefresh = 60,
2297	3288	};
2298	3289
2299	3290	static const struct panel_desc olimex_lcd_olinuxino_43ts = {
..	..	@@ -2321,7 +3312,6 @@
2321	3312	.vsync_start = 483,
2322	3313	.vsync_end = 493,
2323	3314	.vtotal = 500,
2324		- .vrefresh = 60,
2325	3315	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2326	3316	};
2327	3317
..	..	@@ -2340,6 +3330,32 @@
2340	3330	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2341	3331	};
2342	3332
	3333	+static const struct drm_display_mode ortustech_com37h3m_mode = {
	3334	+ .clock = 22230,
	3335	+ .hdisplay = 480,
	3336	+ .hsync_start = 480 + 40,
	3337	+ .hsync_end = 480 + 40 + 10,
	3338	+ .htotal = 480 + 40 + 10 + 40,
	3339	+ .vdisplay = 640,
	3340	+ .vsync_start = 640 + 4,
	3341	+ .vsync_end = 640 + 4 + 2,
	3342	+ .vtotal = 640 + 4 + 2 + 4,
	3343	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3344	+};
	3345	+
	3346	+static const struct panel_desc ortustech_com37h3m = {
	3347	+ .modes = &ortustech_com37h3m_mode,
	3348	+ .num_modes = 1,
	3349	+ .bpc = 8,
	3350	+ .size = {
	3351	+ .width = 56, /* 56.16mm */
	3352	+ .height = 75, /* 74.88mm */
	3353	+ },
	3354	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3355	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	3356	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3357	+};
	3358	+
2343	3359	static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2344	3360	.clock = 25000,
2345	3361	.hdisplay = 480,
..	..	@@ -2350,19 +3366,94 @@
2350	3366	.vsync_start = 800 + 3,
2351	3367	.vsync_end = 800 + 3 + 3,
2352	3368	.vtotal = 800 + 3 + 3 + 3,
2353		- .vrefresh = 60,
2354	3369	};
2355	3370
2356	3371	static const struct panel_desc ortustech_com43h4m85ulc = {
2357	3372	.modes = &ortustech_com43h4m85ulc_mode,
2358	3373	.num_modes = 1,
2359		- .bpc = 8,
	3374	+ .bpc = 6,
2360	3375	.size = {
2361	3376	.width = 56,
2362	3377	.height = 93,
2363	3378	},
	3379	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	3380	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
	3381	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	3382	+};
	3383	+
	3384	+static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
	3385	+ .clock = 33000,
	3386	+ .hdisplay = 800,
	3387	+ .hsync_start = 800 + 210,
	3388	+ .hsync_end = 800 + 210 + 30,
	3389	+ .htotal = 800 + 210 + 30 + 16,
	3390	+ .vdisplay = 480,
	3391	+ .vsync_start = 480 + 22,
	3392	+ .vsync_end = 480 + 22 + 13,
	3393	+ .vtotal = 480 + 22 + 13 + 10,
	3394	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3395	+};
	3396	+
	3397	+static const struct panel_desc osddisplays_osd070t1718_19ts = {
	3398	+ .modes = &osddisplays_osd070t1718_19ts_mode,
	3399	+ .num_modes = 1,
	3400	+ .bpc = 8,
	3401	+ .size = {
	3402	+ .width = 152,
	3403	+ .height = 91,
	3404	+ },
2364	3405	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2365		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	3406	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE \|
	3407	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3408	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	3409	+};
	3410	+
	3411	+static const struct drm_display_mode pda_91_00156_a0_mode = {
	3412	+ .clock = 33300,
	3413	+ .hdisplay = 800,
	3414	+ .hsync_start = 800 + 1,
	3415	+ .hsync_end = 800 + 1 + 64,
	3416	+ .htotal = 800 + 1 + 64 + 64,
	3417	+ .vdisplay = 480,
	3418	+ .vsync_start = 480 + 1,
	3419	+ .vsync_end = 480 + 1 + 23,
	3420	+ .vtotal = 480 + 1 + 23 + 22,
	3421	+};
	3422	+
	3423	+static const struct panel_desc pda_91_00156_a0 = {
	3424	+ .modes = &pda_91_00156_a0_mode,
	3425	+ .num_modes = 1,
	3426	+ .size = {
	3427	+ .width = 152,
	3428	+ .height = 91,
	3429	+ },
	3430	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3431	+};
	3432	+
	3433	+static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
	3434	+ .clock = 24750,
	3435	+ .hdisplay = 800,
	3436	+ .hsync_start = 800 + 54,
	3437	+ .hsync_end = 800 + 54 + 2,
	3438	+ .htotal = 800 + 54 + 2 + 44,
	3439	+ .vdisplay = 480,
	3440	+ .vsync_start = 480 + 49,
	3441	+ .vsync_end = 480 + 49 + 2,
	3442	+ .vtotal = 480 + 49 + 2 + 22,
	3443	+};
	3444	+
	3445	+static const struct panel_desc powertip_ph800480t013_idf02 = {
	3446	+ .modes = &powertip_ph800480t013_idf02_mode,
	3447	+ .num_modes = 1,
	3448	+ .size = {
	3449	+ .width = 152,
	3450	+ .height = 91,
	3451	+ },
	3452	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \|
	3453	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	3454	+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
	3455	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3456	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
2366	3457	};
2367	3458
2368	3459	static const struct drm_display_mode qd43003c0_40_mode = {
..	..	@@ -2375,7 +3466,6 @@
2375	3466	.vsync_start = 272 + 4,
2376	3467	.vsync_end = 272 + 4 + 10,
2377	3468	.vtotal = 272 + 4 + 10 + 2,
2378		- .vrefresh = 60,
2379	3469	};
2380	3470
2381	3471	static const struct panel_desc qd43003c0_40 = {
..	..	@@ -2419,6 +3509,34 @@
2419	3509	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2420	3510	};
2421	3511
	3512	+static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
	3513	+ .clock = 71100,
	3514	+ .hdisplay = 1280,
	3515	+ .hsync_start = 1280 + 48,
	3516	+ .hsync_end = 1280 + 48 + 32,
	3517	+ .htotal = 1280 + 48 + 32 + 80,
	3518	+ .vdisplay = 800,
	3519	+ .vsync_start = 800 + 2,
	3520	+ .vsync_end = 800 + 2 + 5,
	3521	+ .vtotal = 800 + 2 + 5 + 16,
	3522	+};
	3523	+
	3524	+static const struct panel_desc rocktech_rk101ii01d_ct = {
	3525	+ .modes = &rocktech_rk101ii01d_ct_mode,
	3526	+ .num_modes = 1,
	3527	+ .size = {
	3528	+ .width = 217,
	3529	+ .height = 136,
	3530	+ },
	3531	+ .delay = {
	3532	+ .prepare = 50,
	3533	+ .disable = 50,
	3534	+ },
	3535	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	3536	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3537	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3538	+};
	3539	+
2422	3540	static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2423	3541	.clock = 271560,
2424	3542	.hdisplay = 2560,
..	..	@@ -2429,7 +3547,6 @@
2429	3547	.vsync_start = 1600 + 2,
2430	3548	.vsync_end = 1600 + 2 + 5,
2431	3549	.vtotal = 1600 + 2 + 5 + 57,
2432		- .vrefresh = 60,
2433	3550	};
2434	3551
2435	3552	static const struct panel_desc samsung_lsn122dl01_c01 = {
..	..	@@ -2451,7 +3568,6 @@
2451	3568	.vsync_start = 600 + 3,
2452	3569	.vsync_end = 600 + 3 + 6,
2453	3570	.vtotal = 600 + 3 + 6 + 61,
2454		- .vrefresh = 60,
2455	3571	};
2456	3572
2457	3573	static const struct panel_desc samsung_ltn101nt05 = {
..	..	@@ -2462,6 +3578,9 @@
2462	3578	.width = 223,
2463	3579	.height = 125,
2464	3580	},
	3581	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	3582	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	3583	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2465	3584	};
2466	3585
2467	3586	static const struct drm_display_mode samsung_ltn140at29_301_mode = {
..	..	@@ -2474,7 +3593,6 @@
2474	3593	.vsync_start = 768 + 2,
2475	3594	.vsync_end = 768 + 2 + 5,
2476	3595	.vtotal = 768 + 2 + 5 + 17,
2477		- .vrefresh = 60,
2478	3596	};
2479	3597
2480	3598	static const struct panel_desc samsung_ltn140at29_301 = {
..	..	@@ -2487,6 +3605,81 @@
2487	3605	},
2488	3606	};
2489	3607
	3608	+static const struct display_timing satoz_sat050at40h12r2_timing = {
	3609	+ .pixelclock = {33300000, 33300000, 50000000},
	3610	+ .hactive = {800, 800, 800},
	3611	+ .hfront_porch = {16, 210, 354},
	3612	+ .hback_porch = {46, 46, 46},
	3613	+ .hsync_len = {1, 1, 40},
	3614	+ .vactive = {480, 480, 480},
	3615	+ .vfront_porch = {7, 22, 147},
	3616	+ .vback_porch = {23, 23, 23},
	3617	+ .vsync_len = {1, 1, 20},
	3618	+};
	3619	+
	3620	+static const struct panel_desc satoz_sat050at40h12r2 = {
	3621	+ .timings = &satoz_sat050at40h12r2_timing,
	3622	+ .num_timings = 1,
	3623	+ .bpc = 8,
	3624	+ .size = {
	3625	+ .width = 108,
	3626	+ .height = 65,
	3627	+ },
	3628	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3629	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3630	+};
	3631	+
	3632	+static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
	3633	+ .clock = 168480,
	3634	+ .hdisplay = 1920,
	3635	+ .hsync_start = 1920 + 48,
	3636	+ .hsync_end = 1920 + 48 + 32,
	3637	+ .htotal = 1920 + 48 + 32 + 80,
	3638	+ .vdisplay = 1280,
	3639	+ .vsync_start = 1280 + 3,
	3640	+ .vsync_end = 1280 + 3 + 10,
	3641	+ .vtotal = 1280 + 3 + 10 + 57,
	3642	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	3643	+};
	3644	+
	3645	+static const struct panel_desc sharp_ld_d5116z01b = {
	3646	+ .modes = &sharp_ld_d5116z01b_mode,
	3647	+ .num_modes = 1,
	3648	+ .bpc = 8,
	3649	+ .size = {
	3650	+ .width = 260,
	3651	+ .height = 120,
	3652	+ },
	3653	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3654	+ .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
	3655	+};
	3656	+
	3657	+static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
	3658	+ .clock = 33260,
	3659	+ .hdisplay = 800,
	3660	+ .hsync_start = 800 + 64,
	3661	+ .hsync_end = 800 + 64 + 128,
	3662	+ .htotal = 800 + 64 + 128 + 64,
	3663	+ .vdisplay = 480,
	3664	+ .vsync_start = 480 + 8,
	3665	+ .vsync_end = 480 + 8 + 2,
	3666	+ .vtotal = 480 + 8 + 2 + 35,
	3667	+ .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
	3668	+};
	3669	+
	3670	+static const struct panel_desc sharp_lq070y3dg3b = {
	3671	+ .modes = &sharp_lq070y3dg3b_mode,
	3672	+ .num_modes = 1,
	3673	+ .bpc = 8,
	3674	+ .size = {
	3675	+ .width = 152, /* 152.4mm */
	3676	+ .height = 91, /* 91.4mm */
	3677	+ },
	3678	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3679	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	3680	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3681	+};
	3682	+
2490	3683	static const struct drm_display_mode sharp_lq035q7db03_mode = {
2491	3684	.clock = 5500,
2492	3685	.hdisplay = 240,
..	..	@@ -2497,7 +3690,6 @@
2497	3690	.vsync_start = 320 + 9,
2498	3691	.vsync_end = 320 + 9 + 1,
2499	3692	.vtotal = 320 + 9 + 1 + 7,
2500		- .vrefresh = 60,
2501	3693	};
2502	3694
2503	3695	static const struct panel_desc sharp_lq035q7db03 = {
..	..	@@ -2533,6 +3725,7 @@
2533	3725	.height = 136,
2534	3726	},
2535	3727	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
	3728	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2536	3729	};
2537	3730
2538	3731	static const struct display_timing sharp_lq123p1jx31_timing = {
..	..	@@ -2563,28 +3756,45 @@
2563	3756	},
2564	3757	};
2565	3758
2566		-static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2567		- .clock = 71100,
2568		- .hdisplay = 1024,
2569		- .hsync_start = 1024 + 168,
2570		- .hsync_end = 1024 + 168 + 64,
2571		- .htotal = 1024 + 168 + 64 + 88,
2572		- .vdisplay = 768,
2573		- .vsync_start = 768 + 37,
2574		- .vsync_end = 768 + 37 + 2,
2575		- .vtotal = 768 + 37 + 2 + 8,
2576		- .vrefresh = 60,
	3759	+static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
	3760	+ { /* 50 Hz */
	3761	+ .clock = 3000,
	3762	+ .hdisplay = 240,
	3763	+ .hsync_start = 240 + 58,
	3764	+ .hsync_end = 240 + 58 + 1,
	3765	+ .htotal = 240 + 58 + 1 + 1,
	3766	+ .vdisplay = 160,
	3767	+ .vsync_start = 160 + 24,
	3768	+ .vsync_end = 160 + 24 + 10,
	3769	+ .vtotal = 160 + 24 + 10 + 6,
	3770	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC,
	3771	+ },
	3772	+ { /* 60 Hz */
	3773	+ .clock = 3000,
	3774	+ .hdisplay = 240,
	3775	+ .hsync_start = 240 + 8,
	3776	+ .hsync_end = 240 + 8 + 1,
	3777	+ .htotal = 240 + 8 + 1 + 1,
	3778	+ .vdisplay = 160,
	3779	+ .vsync_start = 160 + 24,
	3780	+ .vsync_end = 160 + 24 + 10,
	3781	+ .vtotal = 160 + 24 + 10 + 6,
	3782	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC,
	3783	+ },
2577	3784	};
2578	3785
2579		-static const struct panel_desc sharp_lq150x1lg11 = {
2580		- .modes = &sharp_lq150x1lg11_mode,
2581		- .num_modes = 1,
	3786	+static const struct panel_desc sharp_ls020b1dd01d = {
	3787	+ .modes = sharp_ls020b1dd01d_modes,
	3788	+ .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
2582	3789	.bpc = 6,
2583	3790	.size = {
2584		- .width = 304,
2585		- .height = 228,
	3791	+ .width = 42,
	3792	+ .height = 28,
2586	3793	},
2587	3794	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
	3795	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH
	3796	+ \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
	3797	+ \| DRM_BUS_FLAG_SHARP_SIGNALS,
2588	3798	};
2589	3799
2590	3800	static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
..	..	@@ -2597,7 +3807,6 @@
2597	3807	.vsync_start = 480 + 1,
2598	3808	.vsync_end = 480 + 1 + 23,
2599	3809	.vtotal = 480 + 1 + 23 + 22,
2600		- .vrefresh = 60,
2601	3810	};
2602	3811
2603	3812	static const struct panel_desc shelly_sca07010_bfn_lnn = {
..	..	@@ -2610,6 +3819,31 @@
2610	3819	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2611	3820	};
2612	3821
	3822	+static const struct drm_display_mode starry_kr070pe2t_mode = {
	3823	+ .clock = 33000,
	3824	+ .hdisplay = 800,
	3825	+ .hsync_start = 800 + 209,
	3826	+ .hsync_end = 800 + 209 + 1,
	3827	+ .htotal = 800 + 209 + 1 + 45,
	3828	+ .vdisplay = 480,
	3829	+ .vsync_start = 480 + 22,
	3830	+ .vsync_end = 480 + 22 + 1,
	3831	+ .vtotal = 480 + 22 + 1 + 22,
	3832	+};
	3833	+
	3834	+static const struct panel_desc starry_kr070pe2t = {
	3835	+ .modes = &starry_kr070pe2t_mode,
	3836	+ .num_modes = 1,
	3837	+ .bpc = 8,
	3838	+ .size = {
	3839	+ .width = 152,
	3840	+ .height = 86,
	3841	+ },
	3842	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3843	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
	3844	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	3845	+};
	3846	+
2613	3847	static const struct drm_display_mode starry_kr122ea0sra_mode = {
2614	3848	.clock = 147000,
2615	3849	.hdisplay = 1920,
..	..	@@ -2620,7 +3854,6 @@
2620	3854	.vsync_start = 1200 + 15,
2621	3855	.vsync_end = 1200 + 15 + 2,
2622	3856	.vtotal = 1200 + 15 + 2 + 18,
2623		- .vrefresh = 60,
2624	3857	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2625	3858	};
2626	3859
..	..	@@ -2636,6 +3869,30 @@
2636	3869	.enable = 50,
2637	3870	.unprepare = 10 + 500,
2638	3871	},
	3872	+};
	3873	+
	3874	+static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
	3875	+ .clock = 30000,
	3876	+ .hdisplay = 800,
	3877	+ .hsync_start = 800 + 39,
	3878	+ .hsync_end = 800 + 39 + 47,
	3879	+ .htotal = 800 + 39 + 47 + 39,
	3880	+ .vdisplay = 480,
	3881	+ .vsync_start = 480 + 13,
	3882	+ .vsync_end = 480 + 13 + 2,
	3883	+ .vtotal = 480 + 13 + 2 + 29,
	3884	+};
	3885	+
	3886	+static const struct panel_desc tfc_s9700rtwv43tr_01b = {
	3887	+ .modes = &tfc_s9700rtwv43tr_01b_mode,
	3888	+ .num_modes = 1,
	3889	+ .bpc = 8,
	3890	+ .size = {
	3891	+ .width = 155,
	3892	+ .height = 90,
	3893	+ },
	3894	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3895	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2639	3896	};
2640	3897
2641	3898	static const struct display_timing tianma_tm070jdhg30_timing = {
..	..	@@ -2660,6 +3917,19 @@
2660	3917	.height = 95,
2661	3918	},
2662	3919	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3920	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3921	+};
	3922	+
	3923	+static const struct panel_desc tianma_tm070jvhg33 = {
	3924	+ .timings = &tianma_tm070jdhg30_timing,
	3925	+ .num_timings = 1,
	3926	+ .bpc = 8,
	3927	+ .size = {
	3928	+ .width = 150,
	3929	+ .height = 94,
	3930	+ },
	3931	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3932	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2663	3933	};
2664	3934
2665	3935	static const struct display_timing tianma_tm070rvhg71_timing = {
..	..	@@ -2684,6 +3954,63 @@
2684	3954	.height = 86,
2685	3955	},
2686	3956	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3957	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3958	+};
	3959	+
	3960	+static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
	3961	+ {
	3962	+ .clock = 10000,
	3963	+ .hdisplay = 320,
	3964	+ .hsync_start = 320 + 50,
	3965	+ .hsync_end = 320 + 50 + 6,
	3966	+ .htotal = 320 + 50 + 6 + 38,
	3967	+ .vdisplay = 240,
	3968	+ .vsync_start = 240 + 3,
	3969	+ .vsync_end = 240 + 3 + 1,
	3970	+ .vtotal = 240 + 3 + 1 + 17,
	3971	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3972	+ },
	3973	+};
	3974	+
	3975	+static const struct panel_desc ti_nspire_cx_lcd_panel = {
	3976	+ .modes = ti_nspire_cx_lcd_mode,
	3977	+ .num_modes = 1,
	3978	+ .bpc = 8,
	3979	+ .size = {
	3980	+ .width = 65,
	3981	+ .height = 49,
	3982	+ },
	3983	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3984	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
	3985	+};
	3986	+
	3987	+static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
	3988	+ {
	3989	+ .clock = 10000,
	3990	+ .hdisplay = 320,
	3991	+ .hsync_start = 320 + 6,
	3992	+ .hsync_end = 320 + 6 + 6,
	3993	+ .htotal = 320 + 6 + 6 + 6,
	3994	+ .vdisplay = 240,
	3995	+ .vsync_start = 240 + 0,
	3996	+ .vsync_end = 240 + 0 + 1,
	3997	+ .vtotal = 240 + 0 + 1 + 0,
	3998	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	3999	+ },
	4000	+};
	4001	+
	4002	+static const struct panel_desc ti_nspire_classic_lcd_panel = {
	4003	+ .modes = ti_nspire_classic_lcd_mode,
	4004	+ .num_modes = 1,
	4005	+ /* The grayscale panel has 8 bit for the color .. Y (black) */
	4006	+ .bpc = 8,
	4007	+ .size = {
	4008	+ .width = 71,
	4009	+ .height = 53,
	4010	+ },
	4011	+ /* This is the grayscale bus format */
	4012	+ .bus_format = MEDIA_BUS_FMT_Y8_1X8,
	4013	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2687	4014	};
2688	4015
2689	4016	static const struct drm_display_mode toshiba_lt089ac29000_mode = {
..	..	@@ -2696,7 +4023,6 @@
2696	4023	.vsync_start = 768 + 20,
2697	4024	.vsync_end = 768 + 20 + 7,
2698	4025	.vtotal = 768 + 20 + 7 + 3,
2699		- .vrefresh = 60,
2700	4026	};
2701	4027
2702	4028	static const struct panel_desc toshiba_lt089ac29000 = {
..	..	@@ -2706,8 +4032,9 @@
2706	4032	.width = 194,
2707	4033	.height = 116,
2708	4034	},
2709		- .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2710		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	4035	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
	4036	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	4037	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2711	4038	};
2712	4039
2713	4040	static const struct drm_display_mode tpk_f07a_0102_mode = {
..	..	@@ -2720,7 +4047,6 @@
2720	4047	.vsync_start = 480 + 10,
2721	4048	.vsync_end = 480 + 10 + 2,
2722	4049	.vtotal = 480 + 10 + 2 + 33,
2723		- .vrefresh = 60,
2724	4050	};
2725	4051
2726	4052	static const struct panel_desc tpk_f07a_0102 = {
..	..	@@ -2730,7 +4056,7 @@
2730	4056	.width = 152,
2731	4057	.height = 91,
2732	4058	},
2733		- .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
	4059	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2734	4060	};
2735	4061
2736	4062	static const struct drm_display_mode tpk_f10a_0102_mode = {
..	..	@@ -2743,7 +4069,6 @@
2743	4069	.vsync_start = 600 + 20,
2744	4070	.vsync_end = 600 + 20 + 5,
2745	4071	.vtotal = 600 + 20 + 5 + 25,
2746		- .vrefresh = 60,
2747	4072	};
2748	4073
2749	4074	static const struct panel_desc tpk_f10a_0102 = {
..	..	@@ -2778,6 +4103,7 @@
2778	4103	.height = 91,
2779	4104	},
2780	4105	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	4106	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2781	4107	};
2782	4108
2783	4109	static const struct panel_desc urt_umsh_8596md_parallel = {
..	..	@@ -2791,6 +4117,31 @@
2791	4117	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2792	4118	};
2793	4119
	4120	+static const struct drm_display_mode vl050_8048nt_c01_mode = {
	4121	+ .clock = 33333,
	4122	+ .hdisplay = 800,
	4123	+ .hsync_start = 800 + 210,
	4124	+ .hsync_end = 800 + 210 + 20,
	4125	+ .htotal = 800 + 210 + 20 + 46,
	4126	+ .vdisplay = 480,
	4127	+ .vsync_start = 480 + 22,
	4128	+ .vsync_end = 480 + 22 + 10,
	4129	+ .vtotal = 480 + 22 + 10 + 23,
	4130	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	4131	+};
	4132	+
	4133	+static const struct panel_desc vl050_8048nt_c01 = {
	4134	+ .modes = &vl050_8048nt_c01_mode,
	4135	+ .num_modes = 1,
	4136	+ .bpc = 8,
	4137	+ .size = {
	4138	+ .width = 120,
	4139	+ .height = 76,
	4140	+ },
	4141	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	4142	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	4143	+};
	4144	+
2794	4145	static const struct drm_display_mode winstar_wf35ltiacd_mode = {
2795	4146	.clock = 6410,
2796	4147	.hdisplay = 320,
..	..	@@ -2801,7 +4152,6 @@
2801	4152	.vsync_start = 240 + 4,
2802	4153	.vsync_end = 240 + 4 + 3,
2803	4154	.vtotal = 240 + 4 + 3 + 15,
2804		- .vrefresh = 60,
2805	4155	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2806	4156	};
2807	4157
..	..	@@ -2816,17 +4166,48 @@
2816	4166	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2817	4167	};
2818	4168
	4169	+static const struct drm_display_mode arm_rtsm_mode[] = {
	4170	+ {
	4171	+ .clock = 65000,
	4172	+ .hdisplay = 1024,
	4173	+ .hsync_start = 1024 + 24,
	4174	+ .hsync_end = 1024 + 24 + 136,
	4175	+ .htotal = 1024 + 24 + 136 + 160,
	4176	+ .vdisplay = 768,
	4177	+ .vsync_start = 768 + 3,
	4178	+ .vsync_end = 768 + 3 + 6,
	4179	+ .vtotal = 768 + 3 + 6 + 29,
	4180	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	4181	+ },
	4182	+};
	4183	+
	4184	+static const struct panel_desc arm_rtsm = {
	4185	+ .modes = arm_rtsm_mode,
	4186	+ .num_modes = 1,
	4187	+ .bpc = 8,
	4188	+ .size = {
	4189	+ .width = 400,
	4190	+ .height = 300,
	4191	+ },
	4192	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	4193	+};
	4194	+
2819	4195	static const struct of_device_id platform_of_match[] = {
2820	4196	{
2821	4197	.compatible = "simple-panel",
2822	4198	.data = NULL,
2823		-#ifndef CONFIG_DRM_PANEL_SIMPLE_OF_ONLY
	4199	+ }, {
	4200	+ .compatible = "ampire,am-1280800n3tzqw-t00h",
	4201	+ .data = &ampire_am_1280800n3tzqw_t00h,
2824	4202	}, {
2825	4203	.compatible = "ampire,am-480272h3tmqw-t01h",
2826	4204	.data = &ampire_am_480272h3tmqw_t01h,
2827	4205	}, {
2828	4206	.compatible = "ampire,am800480r3tmqwa1h",
2829	4207	.data = &ampire_am800480r3tmqwa1h,
	4208	+ }, {
	4209	+ .compatible = "arm,rtsm-display",
	4210	+ .data = &arm_rtsm,
2830	4211	}, {
2831	4212	.compatible = "armadeus,st0700-adapt",
2832	4213	.data = &armadeus_st0700_adapt,
..	..	@@ -2840,6 +4221,9 @@
2840	4221	.compatible = "auo,b101xtn01",
2841	4222	.data = &auo_b101xtn01,
2842	4223	}, {
	4224	+ .compatible = "auo,b116xa01",
	4225	+ .data = &auo_b116xak01,
	4226	+ }, {
2843	4227	.compatible = "auo,b116xw03",
2844	4228	.data = &auo_b116xw03,
2845	4229	}, {
..	..	@@ -2852,14 +4236,26 @@
2852	4236	.compatible = "auo,g070vvn01",
2853	4237	.data = &auo_g070vvn01,
2854	4238	}, {
	4239	+ .compatible = "auo,g101evn010",
	4240	+ .data = &auo_g101evn010,
	4241	+ }, {
2855	4242	.compatible = "auo,g104sn02",
2856	4243	.data = &auo_g104sn02,
	4244	+ }, {
	4245	+ .compatible = "auo,g121ean01",
	4246	+ .data = &auo_g121ean01,
2857	4247	}, {
2858	4248	.compatible = "auo,g133han01",
2859	4249	.data = &auo_g133han01,
2860	4250	}, {
	4251	+ .compatible = "auo,g156xtn01",
	4252	+ .data = &auo_g156xtn01,
	4253	+ }, {
2861	4254	.compatible = "auo,g185han01",
2862	4255	.data = &auo_g185han01,
	4256	+ }, {
	4257	+ .compatible = "auo,g190ean01",
	4258	+ .data = &auo_g190ean01,
2863	4259	}, {
2864	4260	.compatible = "auo,p320hvn03",
2865	4261	.data = &auo_p320hvn03,
..	..	@@ -2870,11 +4266,38 @@
2870	4266	.compatible = "avic,tm070ddh03",
2871	4267	.data = &avic_tm070ddh03,
2872	4268	}, {
	4269	+ .compatible = "bananapi,s070wv20-ct16",
	4270	+ .data = &bananapi_s070wv20_ct16,
	4271	+ }, {
2873	4272	.compatible = "boe,hv070wsa-100",
2874	4273	.data = &boe_hv070wsa
2875	4274	}, {
2876	4275	.compatible = "boe,nv101wxmn51",
2877	4276	.data = &boe_nv101wxmn51,
	4277	+ }, {
	4278	+ .compatible = "boe,nv133fhm-n61",
	4279	+ .data = &boe_nv133fhm_n61,
	4280	+ }, {
	4281	+ .compatible = "boe,nv133fhm-n62",
	4282	+ .data = &boe_nv133fhm_n61,
	4283	+ }, {
	4284	+ .compatible = "boe,nv140fhmn49",
	4285	+ .data = &boe_nv140fhmn49,
	4286	+ }, {
	4287	+ .compatible = "cdtech,s043wq26h-ct7",
	4288	+ .data = &cdtech_s043wq26h_ct7,
	4289	+ }, {
	4290	+ .compatible = "cdtech,s070pws19hp-fc21",
	4291	+ .data = &cdtech_s070pws19hp_fc21,
	4292	+ }, {
	4293	+ .compatible = "cdtech,s070swv29hg-dc44",
	4294	+ .data = &cdtech_s070swv29hg_dc44,
	4295	+ }, {
	4296	+ .compatible = "cdtech,s070wv95-ct16",
	4297	+ .data = &cdtech_s070wv95_ct16,
	4298	+ }, {
	4299	+ .compatible = "chefree,ch101olhlwh-002",
	4300	+ .data = &chefree_ch101olhlwh_002,
2878	4301	}, {
2879	4302	.compatible = "chunghwa,claa070wp03xg",
2880	4303	.data = &chunghwa_claa070wp03xg,
..	..	@@ -2891,6 +4314,18 @@
2891	4314	.compatible = "dlc,dlc0700yzg-1",
2892	4315	.data = &dlc_dlc0700yzg_1,
2893	4316	}, {
	4317	+ .compatible = "dlc,dlc1010gig",
	4318	+ .data = &dlc_dlc1010gig,
	4319	+ }, {
	4320	+ .compatible = "edt,et035012dm6",
	4321	+ .data = &edt_et035012dm6,
	4322	+ }, {
	4323	+ .compatible = "edt,etm043080dh6gp",
	4324	+ .data = &edt_etm043080dh6gp,
	4325	+ }, {
	4326	+ .compatible = "edt,etm0430g0dh6",
	4327	+ .data = &edt_etm0430g0dh6,
	4328	+ }, {
2894	4329	.compatible = "edt,et057090dhu",
2895	4330	.data = &edt_et057090dhu,
2896	4331	}, {
..	..	@@ -2906,11 +4341,23 @@
2906	4341	.compatible = "edt,etm0700g0edh6",
2907	4342	.data = &edt_etm0700g0bdh6,
2908	4343	}, {
	4344	+ .compatible = "evervision,vgg804821",
	4345	+ .data = &evervision_vgg804821,
	4346	+ }, {
2909	4347	.compatible = "foxlink,fl500wvr00-a0t",
2910	4348	.data = &foxlink_fl500wvr00_a0t,
2911	4349	}, {
	4350	+ .compatible = "frida,frd350h54004",
	4351	+ .data = &frida_frd350h54004,
	4352	+ }, {
	4353	+ .compatible = "friendlyarm,hd702e",
	4354	+ .data = &friendlyarm_hd702e,
	4355	+ }, {
2912	4356	.compatible = "giantplus,gpg482739qs5",
2913	4357	.data = &giantplus_gpg482739qs5
	4358	+ }, {
	4359	+ .compatible = "giantplus,gpm940b0",
	4360	+ .data = &giantplus_gpm940b0,
2914	4361	}, {
2915	4362	.compatible = "hannstar,hsd070pww1",
2916	4363	.data = &hannstar_hsd070pww1,
..	..	@@ -2945,17 +4392,32 @@
2945	4392	.compatible = "innolux,n156bge-l21",
2946	4393	.data = &innolux_n156bge_l21,
2947	4394	}, {
2948		- .compatible = "innolux,tv123wam",
2949		- .data = &innolux_tv123wam,
	4395	+ .compatible = "innolux,p120zdg-bf1",
	4396	+ .data = &innolux_p120zdg_bf1,
2950	4397	}, {
2951	4398	.compatible = "innolux,zj070na-01p",
2952	4399	.data = &innolux_zj070na_01p,
	4400	+ }, {
	4401	+ .compatible = "ivo,m133nwf4-r0",
	4402	+ .data = &ivo_m133nwf4_r0,
	4403	+ }, {
	4404	+ .compatible = "kingdisplay,kd116n21-30nv-a010",
	4405	+ .data = &kingdisplay_kd116n21_30nv_a010,
	4406	+ }, {
	4407	+ .compatible = "koe,tx14d24vm1bpa",
	4408	+ .data = &koe_tx14d24vm1bpa,
	4409	+ }, {
	4410	+ .compatible = "koe,tx26d202vm0bwa",
	4411	+ .data = &koe_tx26d202vm0bwa,
2953	4412	}, {
2954	4413	.compatible = "koe,tx31d200vm0baa",
2955	4414	.data = &koe_tx31d200vm0baa,
2956	4415	}, {
2957	4416	.compatible = "kyo,tcg121xglp",
2958	4417	.data = &kyo_tcg121xglp,
	4418	+ }, {
	4419	+ .compatible = "lemaker,bl035-rgb-002",
	4420	+ .data = &lemaker_bl035_rgb_002,
2959	4421	}, {
2960	4422	.compatible = "lg,lb070wv8",
2961	4423	.data = &lg_lb070wv8,
..	..	@@ -2972,6 +4434,18 @@
2972	4434	.compatible = "lg,lp129qe",
2973	4435	.data = &lg_lp129qe,
2974	4436	}, {
	4437	+ .compatible = "logicpd,type28",
	4438	+ .data = &logicpd_type_28,
	4439	+ }, {
	4440	+ .compatible = "logictechno,lt161010-2nhc",
	4441	+ .data = &logictechno_lt161010_2nh,
	4442	+ }, {
	4443	+ .compatible = "logictechno,lt161010-2nhr",
	4444	+ .data = &logictechno_lt161010_2nh,
	4445	+ }, {
	4446	+ .compatible = "logictechno,lt170410-2whc",
	4447	+ .data = &logictechno_lt170410_2whc,
	4448	+ }, {
2975	4449	.compatible = "mitsubishi,aa070mc01-ca1",
2976	4450	.data = &mitsubishi_aa070mc01,
2977	4451	}, {
..	..	@@ -2983,6 +4457,9 @@
2983	4457	}, {
2984	4458	.compatible = "netron-dy,e231732",
2985	4459	.data = &netron_dy_e231732,
	4460	+ }, {
	4461	+ .compatible = "neweast,wjfh116008a",
	4462	+ .data = &neweast_wjfh116008a,
2986	4463	}, {
2987	4464	.compatible = "newhaven,nhd-4.3-480272ef-atxl",
2988	4465	.data = &newhaven_nhd_43_480272ef_atxl,
..	..	@@ -3002,14 +4479,32 @@
3002	4479	.compatible = "ontat,yx700wv03",
3003	4480	.data = &ontat_yx700wv03,
3004	4481	}, {
	4482	+ .compatible = "ortustech,com37h3m05dtc",
	4483	+ .data = &ortustech_com37h3m,
	4484	+ }, {
	4485	+ .compatible = "ortustech,com37h3m99dtc",
	4486	+ .data = &ortustech_com37h3m,
	4487	+ }, {
3005	4488	.compatible = "ortustech,com43h4m85ulc",
3006	4489	.data = &ortustech_com43h4m85ulc,
	4490	+ }, {
	4491	+ .compatible = "osddisplays,osd070t1718-19ts",
	4492	+ .data = &osddisplays_osd070t1718_19ts,
	4493	+ }, {
	4494	+ .compatible = "pda,91-00156-a0",
	4495	+ .data = &pda_91_00156_a0,
	4496	+ }, {
	4497	+ .compatible = "powertip,ph800480t013-idf02",
	4498	+ .data = &powertip_ph800480t013_idf02,
3007	4499	}, {
3008	4500	.compatible = "qiaodian,qd43003c0-40",
3009	4501	.data = &qd43003c0_40,
3010	4502	}, {
3011	4503	.compatible = "rocktech,rk070er9427",
3012	4504	.data = &rocktech_rk070er9427,
	4505	+ }, {
	4506	+ .compatible = "rocktech,rk101ii01d-ct",
	4507	+ .data = &rocktech_rk101ii01d_ct,
3013	4508	}, {
3014	4509	.compatible = "samsung,lsn122dl01-c01",
3015	4510	.data = &samsung_lsn122dl01_c01,
..	..	@@ -3020,8 +4515,17 @@
3020	4515	.compatible = "samsung,ltn140at29-301",
3021	4516	.data = &samsung_ltn140at29_301,
3022	4517	}, {
	4518	+ .compatible = "satoz,sat050at40h12r2",
	4519	+ .data = &satoz_sat050at40h12r2,
	4520	+ }, {
	4521	+ .compatible = "sharp,ld-d5116z01b",
	4522	+ .data = &sharp_ld_d5116z01b,
	4523	+ }, {
3023	4524	.compatible = "sharp,lq035q7db03",
3024	4525	.data = &sharp_lq035q7db03,
	4526	+ }, {
	4527	+ .compatible = "sharp,lq070y3dg3b",
	4528	+ .data = &sharp_lq070y3dg3b,
3025	4529	}, {
3026	4530	.compatible = "sharp,lq101k1ly04",
3027	4531	.data = &sharp_lq101k1ly04,
..	..	@@ -3029,20 +4533,35 @@
3029	4533	.compatible = "sharp,lq123p1jx31",
3030	4534	.data = &sharp_lq123p1jx31,
3031	4535	}, {
3032		- .compatible = "sharp,lq150x1lg11",
3033		- .data = &sharp_lq150x1lg11,
	4536	+ .compatible = "sharp,ls020b1dd01d",
	4537	+ .data = &sharp_ls020b1dd01d,
3034	4538	}, {
3035	4539	.compatible = "shelly,sca07010-bfn-lnn",
3036	4540	.data = &shelly_sca07010_bfn_lnn,
3037	4541	}, {
	4542	+ .compatible = "starry,kr070pe2t",
	4543	+ .data = &starry_kr070pe2t,
	4544	+ }, {
3038	4545	.compatible = "starry,kr122ea0sra",
3039	4546	.data = &starry_kr122ea0sra,
	4547	+ }, {
	4548	+ .compatible = "tfc,s9700rtwv43tr-01b",
	4549	+ .data = &tfc_s9700rtwv43tr_01b,
3040	4550	}, {
3041	4551	.compatible = "tianma,tm070jdhg30",
3042	4552	.data = &tianma_tm070jdhg30,
3043	4553	}, {
	4554	+ .compatible = "tianma,tm070jvhg33",
	4555	+ .data = &tianma_tm070jvhg33,
	4556	+ }, {
3044	4557	.compatible = "tianma,tm070rvhg71",
3045	4558	.data = &tianma_tm070rvhg71,
	4559	+ }, {
	4560	+ .compatible = "ti,nspire-cx-lcd-panel",
	4561	+ .data = &ti_nspire_cx_lcd_panel,
	4562	+ }, {
	4563	+ .compatible = "ti,nspire-classic-lcd-panel",
	4564	+ .data = &ti_nspire_classic_lcd_panel,
3046	4565	}, {
3047	4566	.compatible = "toshiba,lt089ac29000",
3048	4567	.data = &toshiba_lt089ac29000,
..	..	@@ -3071,35 +4590,74 @@
3071	4590	.compatible = "urt,umsh-8596md-20t",
3072	4591	.data = &urt_umsh_8596md_parallel,
3073	4592	}, {
	4593	+ .compatible = "vxt,vl050-8048nt-c01",
	4594	+ .data = &vl050_8048nt_c01,
	4595	+ }, {
3074	4596	.compatible = "winstar,wf35ltiacd",
3075	4597	.data = &winstar_wf35ltiacd,
3076		-#endif /* !CONFIG_DRM_PANEL_SIMPLE_OF_ONLY */
	4598	+ }, {
	4599	+ /* Must be the last entry */
	4600	+ .compatible = "panel-dpi",
	4601	+ .data = &panel_dpi,
3077	4602	}, {
3078	4603	/* sentinel */
3079	4604	}
3080	4605	};
3081	4606	MODULE_DEVICE_TABLE(of, platform_of_match);
3082	4607
	4608	+static bool of_child_node_is_present(const struct device_node *node,
	4609	+ const char *name)
	4610	+{
	4611	+ struct device_node *child;
	4612	+
	4613	+ child = of_get_child_by_name(node, name);
	4614	+ of_node_put(child);
	4615	+
	4616	+ return !!child;
	4617	+}
	4618	+
3083	4619	static int panel_simple_of_get_desc_data(struct device *dev,
3084	4620	struct panel_desc *desc)
3085	4621	{
3086	4622	struct device_node *np = dev->of_node;
3087		- struct drm_display_mode *mode;
3088	4623	u32 bus_flags;
3089	4624	const void *data;
3090	4625	int len;
3091	4626	int err;
3092	4627
3093		- mode = devm_kzalloc(dev, sizeof(*mode), GFP_KERNEL);
3094		- if (!mode)
3095		- return -ENOMEM;
	4628	+ if (of_child_node_is_present(np, "display-timings")) {
	4629	+ struct drm_display_mode *mode;
3096	4630
3097		- err = of_get_drm_display_mode(np, mode, &bus_flags, OF_USE_NATIVE_MODE);
3098		- if (!err) {
3099		- desc->modes = mode;
3100		- desc->num_modes = 1;
3101		- desc->bus_flags = bus_flags;
	4631	+ mode = devm_kzalloc(dev, sizeof(*mode), GFP_KERNEL);
	4632	+ if (!mode)
	4633	+ return -ENOMEM;
3102	4634
	4635	+ if (!of_get_drm_display_mode(np, mode, &bus_flags,
	4636	+ OF_USE_NATIVE_MODE)) {
	4637	+ desc->modes = mode;
	4638	+ desc->num_modes = 1;
	4639	+ desc->bus_flags = bus_flags;
	4640	+ }
	4641	+ } else if (of_child_node_is_present(np, "panel-timing")) {
	4642	+ struct display_timing *timing;
	4643	+ struct videomode vm;
	4644	+
	4645	+ timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
	4646	+ if (!timing)
	4647	+ return -ENOMEM;
	4648	+
	4649	+ if (!of_get_display_timing(np, "panel-timing", timing)) {
	4650	+ desc->timings = timing;
	4651	+ desc->num_timings = 1;
	4652	+
	4653	+ bus_flags = 0;
	4654	+ vm.flags = timing->flags;
	4655	+ drm_bus_flags_from_videomode(&vm, &bus_flags);
	4656	+ desc->bus_flags = bus_flags;
	4657	+ }
	4658	+ }
	4659	+
	4660	+ if (desc->num_modes \|\| desc->num_timings) {
3103	4661	of_property_read_u32(np, "bpc", &desc->bpc);
3104	4662	of_property_read_u32(np, "bus-format", &desc->bus_format);
3105	4663	of_property_read_u32(np, "width-mm", &desc->size.width);
..	..	@@ -3213,7 +4771,6 @@
3213	4771	.vsync_start = 1920 + 9,
3214	4772	.vsync_end = 1920 + 9 + 2,
3215	4773	.vtotal = 1920 + 9 + 2 + 8,
3216		- .vrefresh = 60,
3217	4774	};
3218	4775
3219	4776	static const struct panel_desc_dsi auo_b080uan01 = {
..	..	@@ -3225,6 +4782,7 @@
3225	4782	.width = 108,
3226	4783	.height = 272,
3227	4784	},
	4785	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3228	4786	},
3229	4787	.flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_CLOCK_NON_CONTINUOUS,
3230	4788	.format = MIPI_DSI_FMT_RGB888,
..	..	@@ -3241,7 +4799,6 @@
3241	4799	.vsync_start = 1920 + 21,
3242	4800	.vsync_end = 1920 + 21 + 3,
3243	4801	.vtotal = 1920 + 21 + 3 + 18,
3244		- .vrefresh = 60,
3245	4802	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
3246	4803	};
3247	4804
..	..	@@ -3253,6 +4810,7 @@
3253	4810	.width = 107,
3254	4811	.height = 172,
3255	4812	},
	4813	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3256	4814	},
3257	4815	.flags = MIPI_DSI_MODE_VIDEO \|
3258	4816	MIPI_DSI_MODE_VIDEO_BURST \|
..	..	@@ -3271,7 +4829,6 @@
3271	4829	.vsync_start = 1280 + 28,
3272	4830	.vsync_end = 1280 + 28 + 1,
3273	4831	.vtotal = 1280 + 28 + 1 + 14,
3274		- .vrefresh = 60,
3275	4832	};
3276	4833
3277	4834	static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
..	..	@@ -3283,6 +4840,7 @@
3283	4840	.width = 94,
3284	4841	.height = 151,
3285	4842	},
	4843	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3286	4844	},
3287	4845	.flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_CLOCK_NON_CONTINUOUS,
3288	4846	.format = MIPI_DSI_FMT_RGB888,
..	..	@@ -3299,7 +4857,6 @@
3299	4857	.vsync_start = 1280 + 8,
3300	4858	.vsync_end = 1280 + 8 + 4,
3301	4859	.vtotal = 1280 + 8 + 4 + 12,
3302		- .vrefresh = 60,
3303	4860	};
3304	4861
3305	4862	static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
..	..	@@ -3311,6 +4868,7 @@
3311	4868	.width = 62,
3312	4869	.height = 110,
3313	4870	},
	4871	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3314	4872	},
3315	4873	.flags = MIPI_DSI_MODE_VIDEO,
3316	4874	.format = MIPI_DSI_FMT_RGB888,
..	..	@@ -3327,7 +4885,6 @@
3327	4885	.vsync_start = 1200 + 17,
3328	4886	.vsync_end = 1200 + 17 + 2,
3329	4887	.vtotal = 1200 + 17 + 2 + 16,
3330		- .vrefresh = 60,
3331	4888	};
3332	4889
3333	4890	static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
..	..	@@ -3339,9 +4896,69 @@
3339	4896	.width = 217,
3340	4897	.height = 136,
3341	4898	},
	4899	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3342	4900	},
3343	4901	.flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_SYNC_PULSE \|
3344	4902	MIPI_DSI_CLOCK_NON_CONTINUOUS,
	4903	+ .format = MIPI_DSI_FMT_RGB888,
	4904	+ .lanes = 4,
	4905	+};
	4906	+
	4907	+static const struct drm_display_mode lg_acx467akm_7_mode = {
	4908	+ .clock = 150000,
	4909	+ .hdisplay = 1080,
	4910	+ .hsync_start = 1080 + 2,
	4911	+ .hsync_end = 1080 + 2 + 2,
	4912	+ .htotal = 1080 + 2 + 2 + 2,
	4913	+ .vdisplay = 1920,
	4914	+ .vsync_start = 1920 + 2,
	4915	+ .vsync_end = 1920 + 2 + 2,
	4916	+ .vtotal = 1920 + 2 + 2 + 2,
	4917	+};
	4918	+
	4919	+static const struct panel_desc_dsi lg_acx467akm_7 = {
	4920	+ .desc = {
	4921	+ .modes = &lg_acx467akm_7_mode,
	4922	+ .num_modes = 1,
	4923	+ .bpc = 8,
	4924	+ .size = {
	4925	+ .width = 62,
	4926	+ .height = 110,
	4927	+ },
	4928	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
	4929	+ },
	4930	+ .flags = 0,
	4931	+ .format = MIPI_DSI_FMT_RGB888,
	4932	+ .lanes = 4,
	4933	+};
	4934	+
	4935	+static const struct drm_display_mode osd101t2045_53ts_mode = {
	4936	+ .clock = 154500,
	4937	+ .hdisplay = 1920,
	4938	+ .hsync_start = 1920 + 112,
	4939	+ .hsync_end = 1920 + 112 + 16,
	4940	+ .htotal = 1920 + 112 + 16 + 32,
	4941	+ .vdisplay = 1200,
	4942	+ .vsync_start = 1200 + 16,
	4943	+ .vsync_end = 1200 + 16 + 2,
	4944	+ .vtotal = 1200 + 16 + 2 + 16,
	4945	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	4946	+};
	4947	+
	4948	+static const struct panel_desc_dsi osd101t2045_53ts = {
	4949	+ .desc = {
	4950	+ .modes = &osd101t2045_53ts_mode,
	4951	+ .num_modes = 1,
	4952	+ .bpc = 8,
	4953	+ .size = {
	4954	+ .width = 217,
	4955	+ .height = 136,
	4956	+ },
	4957	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
	4958	+ },
	4959	+ .flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_BURST \|
	4960	+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE \|
	4961	+ MIPI_DSI_MODE_EOT_PACKET,
3345	4962	.format = MIPI_DSI_FMT_RGB888,
3346	4963	.lanes = 4,
3347	4964	};
..	..	@@ -3350,7 +4967,6 @@
3350	4967	{
3351	4968	.compatible = "simple-panel-dsi",
3352	4969	.data = NULL,
3353		-#ifndef CONFIG_DRM_PANEL_SIMPLE_OF_ONLY
3354	4970	}, {
3355	4971	.compatible = "auo,b080uan01",
3356	4972	.data = &auo_b080uan01
..	..	@@ -3366,7 +4982,12 @@
3366	4982	}, {
3367	4983	.compatible = "panasonic,vvx10f004b00",
3368	4984	.data = &panasonic_vvx10f004b00
3369		-#endif /* !CONFIG_DRM_PANEL_SIMPLE_OF_ONLY */
	4985	+ }, {
	4986	+ .compatible = "lg,acx467akm-7",
	4987	+ .data = &lg_acx467akm_7
	4988	+ }, {
	4989	+ .compatible = "osddisplays,osd101t2045-53ts",
	4990	+ .data = &osd101t2045_53ts
3370	4991	}, {
3371	4992	/* sentinel */
3372	4993	}
..	..	@@ -3428,6 +5049,26 @@
3428	5049	panel = dev_get_drvdata(dev);
3429	5050	panel->dsi = dsi;
3430	5051
	5052	+ if (!panel->base.backlight) {
	5053	+ struct backlight_properties props;
	5054	+
	5055	+ memset(&props, 0, sizeof(props));
	5056	+ props.type = BACKLIGHT_RAW;
	5057	+ props.brightness = 255;
	5058	+ props.max_brightness = 255;
	5059	+
	5060	+ panel->base.backlight =
	5061	+ devm_backlight_device_register(dev, "dcs-backlight",
	5062	+ dev, panel, &dcs_bl_ops,
	5063	+ &props);
	5064	+ if (IS_ERR(panel->base.backlight)) {
	5065	+ err = PTR_ERR(panel->base.backlight);
	5066	+ dev_err(dev, "failed to register dcs backlight: %d\n",
	5067	+ err);
	5068	+ return err;
	5069	+ }
	5070	+ }
	5071	+
3431	5072	dsi->mode_flags = desc->flags;
3432	5073	dsi->format = desc->format;
3433	5074	dsi->lanes = desc->lanes;
..	..	@@ -3484,11 +5125,7 @@
3484	5125
3485	5126	return 0;
3486	5127	}
3487		-#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
3488		-rootfs_initcall(panel_simple_init);
3489		-#else
3490	5128	module_init(panel_simple_init);
3491		-#endif
3492	5129
3493	5130	static void __exit panel_simple_exit(void)
3494	5131	{