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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/gpu/drm/msm/adreno/adreno_gpu.h
....@@ -1,52 +1,23 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) 2013 Red Hat
34  * Author: Rob Clark <robdclark@gmail.com>
45  *
5
- * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
6
- *
7
- * This program is free software; you can redistribute it and/or modify it
8
- * under the terms of the GNU General Public License version 2 as published by
9
- * the Free Software Foundation.
10
- *
11
- * This program is distributed in the hope that it will be useful, but WITHOUT
12
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14
- * more details.
15
- *
16
- * You should have received a copy of the GNU General Public License along with
17
- * this program.  If not, see <http://www.gnu.org/licenses/>.
6
+ * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
187  */
198 
209 #ifndef __ADRENO_GPU_H__
2110 #define __ADRENO_GPU_H__
2211 
2312 #include <linux/firmware.h>
13
+#include <linux/iopoll.h>
2414 
2515 #include "msm_gpu.h"
2616 
2717 #include "adreno_common.xml.h"
2818 #include "adreno_pm4.xml.h"
2919 
30
-#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
31
-#define REG_SKIP ~0
32
-#define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
33
-
34
-/**
35
- * adreno_regs: List of registers that are used in across all
36
- * 3D devices. Each device type has different offset value for the same
37
- * register, so an array of register offsets are declared for every device
38
- * and are indexed by the enumeration values defined in this enum
39
- */
40
-enum adreno_regs {
41
-	REG_ADRENO_CP_RB_BASE,
42
-	REG_ADRENO_CP_RB_BASE_HI,
43
-	REG_ADRENO_CP_RB_RPTR_ADDR,
44
-	REG_ADRENO_CP_RB_RPTR_ADDR_HI,
45
-	REG_ADRENO_CP_RB_RPTR,
46
-	REG_ADRENO_CP_RB_WPTR,
47
-	REG_ADRENO_CP_RB_CNTL,
48
-	REG_ADRENO_REGISTER_MAX,
49
-};
20
+extern bool snapshot_debugbus;
5021 
5122 enum {
5223 	ADRENO_FW_PM4 = 0,
....@@ -60,6 +31,7 @@
6031 enum adreno_quirks {
6132 	ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
6233 	ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
34
+	ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
6335 };
6436 
6537 struct adreno_rev {
....@@ -77,6 +49,13 @@
7749 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
7850 };
7951 
52
+struct adreno_reglist {
53
+	u32 offset;
54
+	u32 value;
55
+};
56
+
57
+extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[];
58
+
8059 struct adreno_info {
8160 	struct adreno_rev rev;
8261 	uint32_t revn;
....@@ -87,6 +66,7 @@
8766 	struct msm_gpu *(*init)(struct drm_device *dev);
8867 	const char *zapfw;
8968 	u32 inactive_period;
69
+	const struct adreno_reglist *hwcg;
9070 };
9171 
9272 const struct adreno_info *adreno_info(struct adreno_rev rev);
....@@ -135,6 +115,12 @@
135115 };
136116 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
137117 
118
+struct adreno_ocmem {
119
+	struct ocmem *ocmem;
120
+	unsigned long base;
121
+	void *hdl;
122
+};
123
+
138124 /* platform config data (ie. from DT, or pdata) */
139125 struct adreno_platform_config {
140126 	struct adreno_rev rev;
....@@ -154,10 +140,19 @@
154140 	__ret;                                             \
155141 })
156142 
157
-
158
-static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
143
+static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
159144 {
160
-	return (gpu->revn >= 300) && (gpu->revn < 400);
145
+	return (gpu->revn < 300);
146
+}
147
+
148
+static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
149
+{
150
+	return (gpu->revn < 210);
151
+}
152
+
153
+static inline bool adreno_is_a225(struct adreno_gpu *gpu)
154
+{
155
+	return gpu->revn == 225;
161156 }
162157 
163158 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
....@@ -186,9 +181,9 @@
186181 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
187182 }
188183 
189
-static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
184
+static inline int adreno_is_a405(struct adreno_gpu *gpu)
190185 {
191
-	return (gpu->revn >= 400) && (gpu->revn < 500);
186
+	return gpu->revn == 405;
192187 }
193188 
194189 static inline int adreno_is_a420(struct adreno_gpu *gpu)
....@@ -201,9 +196,39 @@
201196        return gpu->revn == 430;
202197 }
203198 
199
+static inline int adreno_is_a510(struct adreno_gpu *gpu)
200
+{
201
+	return gpu->revn == 510;
202
+}
203
+
204204 static inline int adreno_is_a530(struct adreno_gpu *gpu)
205205 {
206206 	return gpu->revn == 530;
207
+}
208
+
209
+static inline int adreno_is_a540(struct adreno_gpu *gpu)
210
+{
211
+	return gpu->revn == 540;
212
+}
213
+
214
+static inline int adreno_is_a618(struct adreno_gpu *gpu)
215
+{
216
+       return gpu->revn == 618;
217
+}
218
+
219
+static inline int adreno_is_a630(struct adreno_gpu *gpu)
220
+{
221
+       return gpu->revn == 630;
222
+}
223
+
224
+static inline int adreno_is_a640(struct adreno_gpu *gpu)
225
+{
226
+       return gpu->revn == 640;
227
+}
228
+
229
+static inline int adreno_is_a650(struct adreno_gpu *gpu)
230
+{
231
+       return gpu->revn == 650;
207232 }
208233 
209234 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
....@@ -213,9 +238,7 @@
213238 		const struct firmware *fw, u64 *iova);
214239 int adreno_hw_init(struct msm_gpu *gpu);
215240 void adreno_recover(struct msm_gpu *gpu);
216
-void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
217
-		struct msm_file_private *ctx);
218
-void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
241
+void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
219242 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
220243 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
221244 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
....@@ -225,6 +248,10 @@
225248 void adreno_dump(struct msm_gpu *gpu);
226249 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
227250 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
251
+
252
+int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
253
+			  struct adreno_ocmem *ocmem);
254
+void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
228255 
229256 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
230257 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
....@@ -236,6 +263,20 @@
236263 
237264 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
238265 int adreno_gpu_state_put(struct msm_gpu_state *state);
266
+
267
+/*
268
+ * Common helper function to initialize the default address space for arm-smmu
269
+ * attached targets
270
+ */
271
+struct msm_gem_address_space *
272
+adreno_iommu_create_address_space(struct msm_gpu *gpu,
273
+		struct platform_device *pdev);
274
+
275
+/*
276
+ * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
277
+ * out of secure mode
278
+ */
279
+int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
239280 
240281 /* ringbuffer helpers (the parts that are adreno specific) */
241282 
....@@ -291,60 +332,11 @@
291332 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
292333 }
293334 
294
-/*
295
- * adreno_reg_check() - Checks the validity of a register enum
296
- * @gpu:		Pointer to struct adreno_gpu
297
- * @offset_name:	The register enum that is checked
298
- */
299
-static inline bool adreno_reg_check(struct adreno_gpu *gpu,
300
-		enum adreno_regs offset_name)
301
-{
302
-	if (offset_name >= REG_ADRENO_REGISTER_MAX ||
303
-			!gpu->reg_offsets[offset_name]) {
304
-		BUG();
305
-	}
306
-
307
-	/*
308
-	 * REG_SKIP is a special value that tell us that the register in
309
-	 * question isn't implemented on target but don't trigger a BUG(). This
310
-	 * is used to cleanly implement adreno_gpu_write64() and
311
-	 * adreno_gpu_read64() in a generic fashion
312
-	 */
313
-	if (gpu->reg_offsets[offset_name] == REG_SKIP)
314
-		return false;
315
-
316
-	return true;
317
-}
318
-
319
-static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
320
-		enum adreno_regs offset_name)
321
-{
322
-	u32 reg = gpu->reg_offsets[offset_name];
323
-	u32 val = 0;
324
-	if(adreno_reg_check(gpu,offset_name))
325
-		val = gpu_read(&gpu->base, reg - 1);
326
-	return val;
327
-}
328
-
329
-static inline void adreno_gpu_write(struct adreno_gpu *gpu,
330
-		enum adreno_regs offset_name, u32 data)
331
-{
332
-	u32 reg = gpu->reg_offsets[offset_name];
333
-	if(adreno_reg_check(gpu, offset_name))
334
-		gpu_write(&gpu->base, reg - 1, data);
335
-}
336
-
335
+struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
337336 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
338337 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
339338 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
340339 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
341
-
342
-static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
343
-		enum adreno_regs lo, enum adreno_regs hi, u64 data)
344
-{
345
-	adreno_gpu_write(gpu, lo, lower_32_bits(data));
346
-	adreno_gpu_write(gpu, hi, upper_32_bits(data));
347
-}
348340 
349341 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
350342 {
....@@ -375,4 +367,9 @@
375367 	((1 << 29) \
376368 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
377369 
370
+
371
+#define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
372
+	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
373
+		interval, timeout)
374
+
378375 #endif /* __ADRENO_GPU_H__ */