forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
....@@ -1,302 +1,41 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2015 MediaTek Inc.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
124  */
135 
14
-#include <linux/clk.h>
15
-#include <linux/clk-provider.h>
16
-#include <linux/delay.h>
17
-#include <linux/io.h>
18
-#include <linux/module.h>
19
-#include <linux/of_device.h>
20
-#include <linux/platform_device.h>
21
-#include <linux/phy/phy.h>
6
+#include "mtk_mipi_tx.h"
227 
23
-#define MIPITX_DSI_CON		0x00
24
-#define RG_DSI_LDOCORE_EN		BIT(0)
25
-#define RG_DSI_CKG_LDOOUT_EN		BIT(1)
26
-#define RG_DSI_BCLK_SEL			(3 << 2)
27
-#define RG_DSI_LD_IDX_SEL		(7 << 4)
28
-#define RG_DSI_PHYCLK_SEL		(2 << 8)
29
-#define RG_DSI_DSICLK_FREQ_SEL		BIT(10)
30
-#define RG_DSI_LPTX_CLMP_EN		BIT(11)
31
-
32
-#define MIPITX_DSI_CLOCK_LANE	0x04
33
-#define MIPITX_DSI_DATA_LANE0	0x08
34
-#define MIPITX_DSI_DATA_LANE1	0x0c
35
-#define MIPITX_DSI_DATA_LANE2	0x10
36
-#define MIPITX_DSI_DATA_LANE3	0x14
37
-#define RG_DSI_LNTx_LDOOUT_EN		BIT(0)
38
-#define RG_DSI_LNTx_CKLANE_EN		BIT(1)
39
-#define RG_DSI_LNTx_LPTX_IPLUS1		BIT(2)
40
-#define RG_DSI_LNTx_LPTX_IPLUS2		BIT(3)
41
-#define RG_DSI_LNTx_LPTX_IMINUS		BIT(4)
42
-#define RG_DSI_LNTx_LPCD_IPLUS		BIT(5)
43
-#define RG_DSI_LNTx_LPCD_IMINUS		BIT(6)
44
-#define RG_DSI_LNTx_RT_CODE		(0xf << 8)
45
-
46
-#define MIPITX_DSI_TOP_CON	0x40
47
-#define RG_DSI_LNT_INTR_EN		BIT(0)
48
-#define RG_DSI_LNT_HS_BIAS_EN		BIT(1)
49
-#define RG_DSI_LNT_IMP_CAL_EN		BIT(2)
50
-#define RG_DSI_LNT_TESTMODE_EN		BIT(3)
51
-#define RG_DSI_LNT_IMP_CAL_CODE		(0xf << 4)
52
-#define RG_DSI_LNT_AIO_SEL		(7 << 8)
53
-#define RG_DSI_PAD_TIE_LOW_EN		BIT(11)
54
-#define RG_DSI_DEBUG_INPUT_EN		BIT(12)
55
-#define RG_DSI_PRESERVE			(7 << 13)
56
-
57
-#define MIPITX_DSI_BG_CON	0x44
58
-#define RG_DSI_BG_CORE_EN		BIT(0)
59
-#define RG_DSI_BG_CKEN			BIT(1)
60
-#define RG_DSI_BG_DIV			(0x3 << 2)
61
-#define RG_DSI_BG_FAST_CHARGE		BIT(4)
62
-#define RG_DSI_VOUT_MSK			(0x3ffff << 5)
63
-#define RG_DSI_V12_SEL			(7 << 5)
64
-#define RG_DSI_V10_SEL			(7 << 8)
65
-#define RG_DSI_V072_SEL			(7 << 11)
66
-#define RG_DSI_V04_SEL			(7 << 14)
67
-#define RG_DSI_V032_SEL			(7 << 17)
68
-#define RG_DSI_V02_SEL			(7 << 20)
69
-#define RG_DSI_BG_R1_TRIM		(0xf << 24)
70
-#define RG_DSI_BG_R2_TRIM		(0xf << 28)
71
-
72
-#define MIPITX_DSI_PLL_CON0	0x50
73
-#define RG_DSI_MPPLL_PLL_EN		BIT(0)
74
-#define RG_DSI_MPPLL_DIV_MSK		(0x1ff << 1)
75
-#define RG_DSI_MPPLL_PREDIV		(3 << 1)
76
-#define RG_DSI_MPPLL_TXDIV0		(3 << 3)
77
-#define RG_DSI_MPPLL_TXDIV1		(3 << 5)
78
-#define RG_DSI_MPPLL_POSDIV		(7 << 7)
79
-#define RG_DSI_MPPLL_MONVC_EN		BIT(10)
80
-#define RG_DSI_MPPLL_MONREF_EN		BIT(11)
81
-#define RG_DSI_MPPLL_VOD_EN		BIT(12)
82
-
83
-#define MIPITX_DSI_PLL_CON1	0x54
84
-#define RG_DSI_MPPLL_SDM_FRA_EN		BIT(0)
85
-#define RG_DSI_MPPLL_SDM_SSC_PH_INIT	BIT(1)
86
-#define RG_DSI_MPPLL_SDM_SSC_EN		BIT(2)
87
-#define RG_DSI_MPPLL_SDM_SSC_PRD	(0xffff << 16)
88
-
89
-#define MIPITX_DSI_PLL_CON2	0x58
90
-
91
-#define MIPITX_DSI_PLL_TOP	0x64
92
-#define RG_DSI_MPPLL_PRESERVE		(0xff << 8)
93
-
94
-#define MIPITX_DSI_PLL_PWR	0x68
95
-#define RG_DSI_MPPLL_SDM_PWR_ON		BIT(0)
96
-#define RG_DSI_MPPLL_SDM_ISO_EN		BIT(1)
97
-#define RG_DSI_MPPLL_SDM_PWR_ACK	BIT(8)
98
-
99
-#define MIPITX_DSI_SW_CTRL	0x80
100
-#define SW_CTRL_EN			BIT(0)
101
-
102
-#define MIPITX_DSI_SW_CTRL_CON0	0x84
103
-#define SW_LNTC_LPTX_PRE_OE		BIT(0)
104
-#define SW_LNTC_LPTX_OE			BIT(1)
105
-#define SW_LNTC_LPTX_P			BIT(2)
106
-#define SW_LNTC_LPTX_N			BIT(3)
107
-#define SW_LNTC_HSTX_PRE_OE		BIT(4)
108
-#define SW_LNTC_HSTX_OE			BIT(5)
109
-#define SW_LNTC_HSTX_ZEROCLK		BIT(6)
110
-#define SW_LNT0_LPTX_PRE_OE		BIT(7)
111
-#define SW_LNT0_LPTX_OE			BIT(8)
112
-#define SW_LNT0_LPTX_P			BIT(9)
113
-#define SW_LNT0_LPTX_N			BIT(10)
114
-#define SW_LNT0_HSTX_PRE_OE		BIT(11)
115
-#define SW_LNT0_HSTX_OE			BIT(12)
116
-#define SW_LNT0_LPRX_EN			BIT(13)
117
-#define SW_LNT1_LPTX_PRE_OE		BIT(14)
118
-#define SW_LNT1_LPTX_OE			BIT(15)
119
-#define SW_LNT1_LPTX_P			BIT(16)
120
-#define SW_LNT1_LPTX_N			BIT(17)
121
-#define SW_LNT1_HSTX_PRE_OE		BIT(18)
122
-#define SW_LNT1_HSTX_OE			BIT(19)
123
-#define SW_LNT2_LPTX_PRE_OE		BIT(20)
124
-#define SW_LNT2_LPTX_OE			BIT(21)
125
-#define SW_LNT2_LPTX_P			BIT(22)
126
-#define SW_LNT2_LPTX_N			BIT(23)
127
-#define SW_LNT2_HSTX_PRE_OE		BIT(24)
128
-#define SW_LNT2_HSTX_OE			BIT(25)
129
-
130
-struct mtk_mipitx_data {
131
-	const u32 mppll_preserve;
132
-};
133
-
134
-struct mtk_mipi_tx {
135
-	struct device *dev;
136
-	void __iomem *regs;
137
-	u32 data_rate;
138
-	const struct mtk_mipitx_data *driver_data;
139
-	struct clk_hw pll_hw;
140
-	struct clk *pll;
141
-};
142
-
143
-static inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
8
+inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
1449 {
14510 	return container_of(hw, struct mtk_mipi_tx, pll_hw);
14611 }
14712 
148
-static void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
149
-				   u32 bits)
13
+void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
14
+			    u32 bits)
15015 {
15116 	u32 temp = readl(mipi_tx->regs + offset);
15217 
15318 	writel(temp & ~bits, mipi_tx->regs + offset);
15419 }
15520 
156
-static void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
157
-				 u32 bits)
21
+void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
22
+			  u32 bits)
15823 {
15924 	u32 temp = readl(mipi_tx->regs + offset);
16025 
16126 	writel(temp | bits, mipi_tx->regs + offset);
16227 }
16328 
164
-static void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
165
-				    u32 mask, u32 data)
29
+void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
30
+			     u32 mask, u32 data)
16631 {
16732 	u32 temp = readl(mipi_tx->regs + offset);
16833 
16934 	writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
17035 }
17136 
172
-static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
173
-{
174
-	struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
175
-	u8 txdiv, txdiv0, txdiv1;
176
-	u64 pcw;
177
-
178
-	dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate);
179
-
180
-	if (mipi_tx->data_rate >= 500000000) {
181
-		txdiv = 1;
182
-		txdiv0 = 0;
183
-		txdiv1 = 0;
184
-	} else if (mipi_tx->data_rate >= 250000000) {
185
-		txdiv = 2;
186
-		txdiv0 = 1;
187
-		txdiv1 = 0;
188
-	} else if (mipi_tx->data_rate >= 125000000) {
189
-		txdiv = 4;
190
-		txdiv0 = 2;
191
-		txdiv1 = 0;
192
-	} else if (mipi_tx->data_rate > 62000000) {
193
-		txdiv = 8;
194
-		txdiv0 = 2;
195
-		txdiv1 = 1;
196
-	} else if (mipi_tx->data_rate >= 50000000) {
197
-		txdiv = 16;
198
-		txdiv0 = 2;
199
-		txdiv1 = 2;
200
-	} else {
201
-		return -EINVAL;
202
-	}
203
-
204
-	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON,
205
-				RG_DSI_VOUT_MSK |
206
-				RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN,
207
-				(4 << 20) | (4 << 17) | (4 << 14) |
208
-				(4 << 11) | (4 << 8) | (4 << 5) |
209
-				RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
210
-
211
-	usleep_range(30, 100);
212
-
213
-	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON,
214
-				RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
215
-				(8 << 4) | RG_DSI_LNT_HS_BIAS_EN);
216
-
217
-	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON,
218
-			     RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
219
-
220
-	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
221
-				RG_DSI_MPPLL_SDM_PWR_ON |
222
-				RG_DSI_MPPLL_SDM_ISO_EN,
223
-				RG_DSI_MPPLL_SDM_PWR_ON);
224
-
225
-	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
226
-			       RG_DSI_MPPLL_PLL_EN);
227
-
228
-	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
229
-				RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
230
-				RG_DSI_MPPLL_PREDIV,
231
-				(txdiv0 << 3) | (txdiv1 << 5));
232
-
233
-	/*
234
-	 * PLL PCW config
235
-	 * PCW bit 24~30 = integer part of pcw
236
-	 * PCW bit 0~23 = fractional part of pcw
237
-	 * pcw = data_Rate*4*txdiv/(Ref_clk*2);
238
-	 * Post DIV =4, so need data_Rate*4
239
-	 * Ref_clk is 26MHz
240
-	 */
241
-	pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24,
242
-		      26000000);
243
-	writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2);
244
-
245
-	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
246
-			     RG_DSI_MPPLL_SDM_FRA_EN);
247
-
248
-	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
249
-
250
-	usleep_range(20, 100);
251
-
252
-	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
253
-			       RG_DSI_MPPLL_SDM_SSC_EN);
254
-
255
-	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
256
-				RG_DSI_MPPLL_PRESERVE,
257
-				mipi_tx->driver_data->mppll_preserve);
258
-
259
-	return 0;
260
-}
261
-
262
-static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
263
-{
264
-	struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
265
-
266
-	dev_dbg(mipi_tx->dev, "unprepare\n");
267
-
268
-	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
269
-			       RG_DSI_MPPLL_PLL_EN);
270
-
271
-	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
272
-				RG_DSI_MPPLL_PRESERVE, 0);
273
-
274
-	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
275
-				RG_DSI_MPPLL_SDM_ISO_EN |
276
-				RG_DSI_MPPLL_SDM_PWR_ON,
277
-				RG_DSI_MPPLL_SDM_ISO_EN);
278
-
279
-	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
280
-			       RG_DSI_LNT_HS_BIAS_EN);
281
-
282
-	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON,
283
-			       RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
284
-
285
-	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON,
286
-			       RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
287
-
288
-	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
289
-			       RG_DSI_MPPLL_DIV_MSK);
290
-}
291
-
292
-static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
293
-				       unsigned long *prate)
294
-{
295
-	return clamp_val(rate, 50000000, 1250000000);
296
-}
297
-
298
-static int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
299
-				    unsigned long parent_rate)
37
+int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
38
+			     unsigned long parent_rate)
30039 {
30140 	struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
30241 
....@@ -307,35 +46,12 @@
30746 	return 0;
30847 }
30948 
310
-static unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
311
-						 unsigned long parent_rate)
49
+unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
50
+					  unsigned long parent_rate)
31251 {
31352 	struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
31453 
31554 	return mipi_tx->data_rate;
316
-}
317
-
318
-static const struct clk_ops mtk_mipi_tx_pll_ops = {
319
-	.prepare = mtk_mipi_tx_pll_prepare,
320
-	.unprepare = mtk_mipi_tx_pll_unprepare,
321
-	.round_rate = mtk_mipi_tx_pll_round_rate,
322
-	.set_rate = mtk_mipi_tx_pll_set_rate,
323
-	.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
324
-};
325
-
326
-static int mtk_mipi_tx_power_on_signal(struct phy *phy)
327
-{
328
-	struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
329
-	u32 reg;
330
-
331
-	for (reg = MIPITX_DSI_CLOCK_LANE;
332
-	     reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
333
-		mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
334
-
335
-	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
336
-			       RG_DSI_PAD_TIE_LOW_EN);
337
-
338
-	return 0;
33955 }
34056 
34157 static int mtk_mipi_tx_power_on(struct phy *phy)
....@@ -349,22 +65,8 @@
34965 		return ret;
35066 
35167 	/* Enable DSI Lane LDO outputs, disable pad tie low */
352
-	mtk_mipi_tx_power_on_signal(phy);
353
-
68
+	mipi_tx->driver_data->mipi_tx_enable_signal(phy);
35469 	return 0;
355
-}
356
-
357
-static void mtk_mipi_tx_power_off_signal(struct phy *phy)
358
-{
359
-	struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
360
-	u32 reg;
361
-
362
-	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON,
363
-			     RG_DSI_PAD_TIE_LOW_EN);
364
-
365
-	for (reg = MIPITX_DSI_CLOCK_LANE;
366
-	     reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
367
-		mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
36870 }
36971 
37072 static int mtk_mipi_tx_power_off(struct phy *phy)
....@@ -372,7 +74,7 @@
37274 	struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
37375 
37476 	/* Enable pad tie low, disable DSI Lane LDO outputs */
375
-	mtk_mipi_tx_power_off_signal(phy);
77
+	mipi_tx->driver_data->mipi_tx_disable_signal(phy);
37678 
37779 	/* Disable PLL and power down core */
37880 	clk_disable_unprepare(mipi_tx->pll);
....@@ -386,15 +88,52 @@
38688 	.owner = THIS_MODULE,
38789 };
38890 
91
+static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx)
92
+{
93
+	struct nvmem_cell *cell;
94
+	size_t len;
95
+	u32 *buf;
96
+
97
+	cell = nvmem_cell_get(mipi_tx->dev, "calibration-data");
98
+	if (IS_ERR(cell)) {
99
+		dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n");
100
+		return;
101
+	}
102
+	buf = (u32 *)nvmem_cell_read(cell, &len);
103
+	nvmem_cell_put(cell);
104
+
105
+	if (IS_ERR(buf)) {
106
+		dev_info(mipi_tx->dev, "can't get data, ignore it\n");
107
+		return;
108
+	}
109
+
110
+	if (len < 3 * sizeof(u32)) {
111
+		dev_info(mipi_tx->dev, "invalid calibration data\n");
112
+		kfree(buf);
113
+		return;
114
+	}
115
+
116
+	mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) |
117
+			       (buf[0] >> 11 & 0x1f);
118
+	mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) |
119
+			       (buf[0] >> 1 & 0x1f);
120
+	mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) |
121
+			       (buf[1] >> 22 & 0x1f);
122
+	mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) |
123
+			       (buf[1] >> 12 & 0x1f);
124
+	mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) |
125
+			       (buf[1] >> 2 & 0x1f);
126
+	kfree(buf);
127
+}
128
+
389129 static int mtk_mipi_tx_probe(struct platform_device *pdev)
390130 {
391131 	struct device *dev = &pdev->dev;
392132 	struct mtk_mipi_tx *mipi_tx;
393133 	struct resource *mem;
394
-	struct clk *ref_clk;
395134 	const char *ref_clk_name;
135
+	struct clk *ref_clk;
396136 	struct clk_init_data clk_init = {
397
-		.ops = &mtk_mipi_tx_pll_ops,
398137 		.num_parents = 1,
399138 		.parent_names = (const char * const *)&ref_clk_name,
400139 		.flags = CLK_SET_RATE_GATE,
....@@ -408,6 +147,9 @@
408147 		return -ENOMEM;
409148 
410149 	mipi_tx->driver_data = of_device_get_match_data(dev);
150
+	if (!mipi_tx->driver_data)
151
+		return -ENODEV;
152
+
411153 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
412154 	mipi_tx->regs = devm_ioremap_resource(dev, mem);
413155 	if (IS_ERR(mipi_tx->regs)) {
....@@ -422,6 +164,21 @@
422164 		dev_err(dev, "Failed to get reference clock: %d\n", ret);
423165 		return ret;
424166 	}
167
+
168
+	ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
169
+				   &mipi_tx->mipitx_drive);
170
+	/* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
171
+	if (ret < 0)
172
+		mipi_tx->mipitx_drive = 4600;
173
+
174
+	/* check the mipitx_drive valid */
175
+	if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) {
176
+		dev_warn(dev, "drive-strength-microamp is invalid %d, not in 3000 ~ 6000\n",
177
+			 mipi_tx->mipitx_drive);
178
+		mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000,
179
+						  6000);
180
+	}
181
+
425182 	ref_clk_name = __clk_get_name(ref_clk);
426183 
427184 	ret = of_property_read_string(dev->of_node, "clock-output-names",
....@@ -430,6 +187,8 @@
430187 		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
431188 		return ret;
432189 	}
190
+
191
+	clk_init.ops = mipi_tx->driver_data->mipi_tx_clk_ops;
433192 
434193 	mipi_tx->pll_hw.init = &clk_init;
435194 	mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
....@@ -455,6 +214,8 @@
455214 
456215 	mipi_tx->dev = dev;
457216 
217
+	mtk_mipi_tx_get_calibration_datal(mipi_tx);
218
+
458219 	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
459220 				   mipi_tx->pll);
460221 }
....@@ -465,20 +226,14 @@
465226 	return 0;
466227 }
467228 
468
-static const struct mtk_mipitx_data mt2701_mipitx_data = {
469
-	.mppll_preserve = (3 << 8)
470
-};
471
-
472
-static const struct mtk_mipitx_data mt8173_mipitx_data = {
473
-	.mppll_preserve = (0 << 8)
474
-};
475
-
476229 static const struct of_device_id mtk_mipi_tx_match[] = {
477230 	{ .compatible = "mediatek,mt2701-mipi-tx",
478231 	  .data = &mt2701_mipitx_data },
479232 	{ .compatible = "mediatek,mt8173-mipi-tx",
480233 	  .data = &mt8173_mipitx_data },
481
-	{},
234
+	{ .compatible = "mediatek,mt8183-mipi-tx",
235
+	  .data = &mt8183_mipitx_data },
236
+	{ },
482237 };
483238 
484239 struct platform_driver mtk_mipi_tx_driver = {
....@@ -489,3 +244,4 @@
489244 		.of_match_table = mtk_mipi_tx_match,
490245 	},
491246 };
247
+