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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
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@@ -31,6 +31,9 @@
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 	dcc_control__256_256_xxx,
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 	dcc_control__128_128_xxx,
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 	dcc_control__256_64_64,
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+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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+	dcc_control__256_128_128,
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+#endif
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 };
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 enum segment_order {
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@@ -39,11 +42,82 @@
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 	segment_order__non_contiguous,
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 };
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+struct dcn_hubbub_wm_set {
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+	uint32_t wm_set;
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+	uint32_t data_urgent;
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+	uint32_t pte_meta_urgent;
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+	uint32_t sr_enter;
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+	uint32_t sr_exit;
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+	uint32_t dram_clk_chanage;
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+};
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+
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+struct dcn_hubbub_wm {
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+	struct dcn_hubbub_wm_set sets[4];
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+};
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+
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+enum dcn_hubbub_page_table_depth {
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+	DCN_PAGE_TABLE_DEPTH_1_LEVEL,
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+	DCN_PAGE_TABLE_DEPTH_2_LEVEL,
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+	DCN_PAGE_TABLE_DEPTH_3_LEVEL,
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+	DCN_PAGE_TABLE_DEPTH_4_LEVEL
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+};
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+
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+enum dcn_hubbub_page_table_block_size {
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+	DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0,
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+	DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4,
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+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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+	DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3
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+#endif
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+};
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+
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+struct dcn_hubbub_phys_addr_config {
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+	struct {
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+		uint64_t fb_top;
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+		uint64_t fb_offset;
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+		uint64_t fb_base;
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+		uint64_t agp_top;
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+		uint64_t agp_bot;
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+		uint64_t agp_base;
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+	} system_aperture;
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+
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+	struct {
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+		uint64_t page_table_start_addr;
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+		uint64_t page_table_end_addr;
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+		uint64_t page_table_base_addr;
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+	} gart_config;
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+
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+	uint64_t page_table_default_page_addr;
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+};
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+
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+struct dcn_hubbub_virt_addr_config {
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+	uint64_t				page_table_start_addr;
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+	uint64_t				page_table_end_addr;
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+	enum dcn_hubbub_page_table_block_size	page_table_block_size;
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+	enum dcn_hubbub_page_table_depth	page_table_depth;
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+	uint64_t				page_table_base_addr;
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+};
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+
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+struct hubbub_addr_config {
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+	struct dcn_hubbub_phys_addr_config pa_config;
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+	struct dcn_hubbub_virt_addr_config va_config;
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+	struct {
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+		uint64_t aperture_check_fault;
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+		uint64_t generic_fault;
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+	} default_addrs;
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+};
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 struct hubbub_funcs {
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 	void (*update_dchub)(
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 			struct hubbub *hubbub,
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 			struct dchub_init_data *dh_data);
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+
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+	int (*init_dchub_sys_ctx)(
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+			struct hubbub *hubbub,
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+			struct dcn_hubbub_phys_addr_config *pa_config);
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+	void (*init_vm_ctx)(
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+			struct hubbub *hubbub,
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+			struct dcn_hubbub_virt_addr_config *va_config,
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+			int vmid);
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 	bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
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 			const struct dc_dcc_surface_param *input,
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@@ -58,7 +132,31 @@
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 	bool (*dcc_support_pixel_format)(
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 			enum surface_pixel_format format,
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 			unsigned int *bytes_per_element);
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+
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+	void (*wm_read_state)(struct hubbub *hubbub,
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+			struct dcn_hubbub_wm *wm);
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+
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+	void (*get_dchub_ref_freq)(struct hubbub *hubbub,
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+			unsigned int dccg_ref_freq_inKhz,
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+			unsigned int *dchub_ref_freq_inKhz);
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+
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+	bool (*program_watermarks)(
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+			struct hubbub *hubbub,
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+			struct dcn_watermark_set *watermarks,
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+			unsigned int refclk_mhz,
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+			bool safe_to_lower);
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+
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+	bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
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+	void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
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+
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+	void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub);
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+
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+	void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub);
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 };
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+struct hubbub {
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+	const struct hubbub_funcs *funcs;
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+	struct dc_context *ctx;
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+};
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 #endif