forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/gpu/drm/amd/amdgpu/sid.h
....@@ -47,8 +47,7 @@
4747 #define SI_MAX_LDS_NUM           	0xFFFF
4848 #define SI_MAX_TCC               	16
4949 #define SI_MAX_TCC_MASK          	0xFFFF
50
-
51
-#define AMDGPU_NUM_OF_VMIDS 		8
50
+#define SI_MAX_CTLACKS_ASSERTION_WAIT   100
5251 
5352 /* SMC IND accessor regs */
5453 #define SMC_IND_INDEX_0                              0x80
....@@ -1646,9 +1645,10 @@
16461645 /*
16471646  * PM4
16481647  */
1649
-#define PACKET0(reg, n)	((RADEON_PACKET_TYPE0 << 30) |			\
1650
-			 (((reg) >> 2) & 0xFFFF) |			\
1651
-			 ((n) & 0x3FFF) << 16)
1648
+#define PACKET_TYPE0    0
1649
+#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) |				\
1650
+                         ((reg) & 0xFFFF) |				\
1651
+                         ((n) & 0x3FFF) << 16)
16521652 #define CP_PACKET2			0x80000000
16531653 #define		PACKET2_PAD_SHIFT		0
16541654 #define		PACKET2_PAD_MASK		(0x3fffffff << 0)
....@@ -2201,6 +2201,26 @@
22012201 #       define EVERGREEN_GRPH_ENDIAN_8IN16              1
22022202 #       define EVERGREEN_GRPH_ENDIAN_8IN32              2
22032203 #       define EVERGREEN_GRPH_ENDIAN_8IN64              3
2204
+#define EVERGREEN_GRPH_RED_CROSSBAR(x)           (((x) & 0x3) << 4)
2205
+#       define EVERGREEN_GRPH_RED_SEL_R                 0
2206
+#       define EVERGREEN_GRPH_RED_SEL_G                 1
2207
+#       define EVERGREEN_GRPH_RED_SEL_B                 2
2208
+#       define EVERGREEN_GRPH_RED_SEL_A                 3
2209
+#define EVERGREEN_GRPH_GREEN_CROSSBAR(x)         (((x) & 0x3) << 6)
2210
+#       define EVERGREEN_GRPH_GREEN_SEL_G               0
2211
+#       define EVERGREEN_GRPH_GREEN_SEL_B               1
2212
+#       define EVERGREEN_GRPH_GREEN_SEL_A               2
2213
+#       define EVERGREEN_GRPH_GREEN_SEL_R               3
2214
+#define EVERGREEN_GRPH_BLUE_CROSSBAR(x)          (((x) & 0x3) << 8)
2215
+#       define EVERGREEN_GRPH_BLUE_SEL_B                0
2216
+#       define EVERGREEN_GRPH_BLUE_SEL_A                1
2217
+#       define EVERGREEN_GRPH_BLUE_SEL_R                2
2218
+#       define EVERGREEN_GRPH_BLUE_SEL_G                3
2219
+#define EVERGREEN_GRPH_ALPHA_CROSSBAR(x)         (((x) & 0x3) << 10)
2220
+#       define EVERGREEN_GRPH_ALPHA_SEL_A               0
2221
+#       define EVERGREEN_GRPH_ALPHA_SEL_R               1
2222
+#       define EVERGREEN_GRPH_ALPHA_SEL_G               2
2223
+#       define EVERGREEN_GRPH_ALPHA_SEL_B               3
22042224 
22052225 #define EVERGREEN_D3VGA_CONTROL                         0xf8
22062226 #define EVERGREEN_D4VGA_CONTROL                         0xf9
....@@ -2320,11 +2340,6 @@
23202340 #       define NI_INPUT_GAMMA_XVYCC_222                3
23212341 #       define NI_OVL_INPUT_GAMMA_MODE(x)              (((x) & 0x3) << 4)
23222342 
2323
-#define IH_RB_WPTR__RB_OVERFLOW_MASK	0x1
2324
-#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
2325
-#define SRBM_STATUS__IH_BUSY_MASK	0x20000
2326
-#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK	0x400
2327
-
23282343 #define	BLACKOUT_MODE_MASK			0x00000007
23292344 #define	VGA_RENDER_CONTROL			0xC0
23302345 #define R_000300_VGA_RENDER_CONTROL             0xC0
....@@ -2411,18 +2426,6 @@
24112426 #define MC_SEQ_MISC0__MT__HBM    0x60000000
24122427 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
24132428 
2414
-#define SRBM_STATUS__MCB_BUSY_MASK 0x200
2415
-#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
2416
-#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
2417
-#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
2418
-#define SRBM_STATUS__MCC_BUSY_MASK 0x800
2419
-#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
2420
-#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
2421
-#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
2422
-#define SRBM_STATUS__VMC_BUSY_MASK 0x100
2423
-#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
2424
-
2425
-
24262429 #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
24272430 #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000
24282431 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
....@@ -2447,8 +2450,6 @@
24472450 
24482451 #define PCIE_BUS_CLK    10000
24492452 #define TCLK            (PCIE_BUS_CLK / 10)
2450
-#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK		0xf0000000
2451
-#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
24522453 #define	PCIE_PORT_INDEX					0xe
24532454 #define	PCIE_PORT_DATA					0xf
24542455 #define EVERGREEN_PIF_PHY0_INDEX                        0x8
....@@ -2458,4 +2459,36 @@
24582459 
24592460 #define	MC_VM_FB_OFFSET					0x81a
24602461 
2462
+/* Discrete VCE clocks */
2463
+#define CG_VCEPLL_FUNC_CNTL                             0xc0030600
2464
+#define    VCEPLL_RESET_MASK                            0x00000001
2465
+#define    VCEPLL_SLEEP_MASK                            0x00000002
2466
+#define    VCEPLL_BYPASS_EN_MASK                        0x00000004
2467
+#define    VCEPLL_CTLREQ_MASK                           0x00000008
2468
+#define    VCEPLL_VCO_MODE_MASK                         0x00000600
2469
+#define    VCEPLL_REF_DIV_MASK                          0x003F0000
2470
+#define    VCEPLL_CTLACK_MASK                           0x40000000
2471
+#define    VCEPLL_CTLACK2_MASK                          0x80000000
2472
+
2473
+#define CG_VCEPLL_FUNC_CNTL_2                           0xc0030601
2474
+#define    VCEPLL_PDIV_A(x)                             ((x) << 0)
2475
+#define    VCEPLL_PDIV_A_MASK                           0x0000007F
2476
+#define    VCEPLL_PDIV_B(x)                             ((x) << 8)
2477
+#define    VCEPLL_PDIV_B_MASK                           0x00007F00
2478
+#define    EVCLK_SRC_SEL(x)                             ((x) << 20)
2479
+#define    EVCLK_SRC_SEL_MASK                           0x01F00000
2480
+#define    ECCLK_SRC_SEL(x)                             ((x) << 25)
2481
+#define    ECCLK_SRC_SEL_MASK                           0x3E000000
2482
+
2483
+#define CG_VCEPLL_FUNC_CNTL_3                           0xc0030602
2484
+#define    VCEPLL_FB_DIV(x)                             ((x) << 0)
2485
+#define    VCEPLL_FB_DIV_MASK                           0x01FFFFFF
2486
+
2487
+#define CG_VCEPLL_FUNC_CNTL_4                           0xc0030603
2488
+
2489
+#define CG_VCEPLL_FUNC_CNTL_5                           0xc0030604
2490
+#define CG_VCEPLL_SPREAD_SPECTRUM                       0xc0030606
2491
+#define    VCEPLL_SSEN_MASK                             0x00000001
2492
+
2493
+
24612494 #endif