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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
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@@ -30,6 +30,9 @@
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 #include <drm/amdgpu_drm.h>
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 #include "amdgpu.h"
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+#ifdef CONFIG_MMU_NOTIFIER
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+#include <linux/mmu_notifier.h>
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+#endif
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 #define AMDGPU_BO_INVALID_OFFSET	LONG_MAX
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 #define AMDGPU_BO_MAX_PLACEMENTS	3
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@@ -41,7 +44,8 @@
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 	u32				preferred_domain;
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 	u64				flags;
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 	enum ttm_bo_type		type;
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-	struct reservation_object	*resv;
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+	bool				no_wait_gpu;
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+	struct dma_resv	*resv;
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 };
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 /* bo virtual addresses in a vm */
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@@ -72,6 +76,8 @@
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 	/* If the mappings are cleared or filled */
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 	bool				cleared;
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+
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+	bool				is_xgmi;
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 };
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 struct amdgpu_bo {
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@@ -89,20 +95,21 @@
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 	void				*metadata;
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 	u32				metadata_size;
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 	unsigned			prime_shared_count;
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-	/* list of all virtual address to which this bo is associated to */
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-	struct list_head		va;
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+	/* per VM structure for page tables and with virtual addresses */
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+	struct amdgpu_vm_bo_base	*vm_bo;
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 	/* Constant after initialization */
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-	struct drm_gem_object		gem_base;
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 	struct amdgpu_bo		*parent;
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 	struct amdgpu_bo		*shadow;
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 	struct ttm_bo_kmap_obj		dma_buf_vmap;
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 	struct amdgpu_mn		*mn;
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-	union {
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-		struct list_head	mn_list;
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-		struct list_head	shadow_list;
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-	};
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+
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+#ifdef CONFIG_MMU_NOTIFIER
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+	struct mmu_interval_notifier	notifier;
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+#endif
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+
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+	struct list_head		shadow_list;
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 	struct kgd_mem                  *kfd_bo;
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 };
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@@ -190,20 +197,7 @@
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  */
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 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
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 {
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-	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
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-}
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-
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-/**
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- * amdgpu_bo_gpu_accessible - return whether the bo is currently in memory that
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- * is accessible to the GPU.
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- */
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-static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
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-{
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-	switch (bo->tbo.mem.mem_type) {
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-	case TTM_PL_TT: return amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem);
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-	case TTM_PL_VRAM: return true;
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-	default: return false;
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-	}
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+	return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
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 }
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 /**
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@@ -235,6 +229,17 @@
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 	return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
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 }
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+/**
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+ * amdgpu_bo_encrypted - test if the BO is encrypted
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+ * @bo: pointer to a buffer object
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+ *
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+ * Return true if the buffer object is encrypted, false otherwise.
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+ */
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+static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
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+{
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+	return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
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+}
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+
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 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
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 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
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@@ -249,6 +254,9 @@
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 			    unsigned long size, int align,
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 			    u32 domain, struct amdgpu_bo **bo_ptr,
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 			    u64 *gpu_addr, void **cpu_addr);
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+int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
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+			       uint64_t offset, uint64_t size, uint32_t domain,
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+			       struct amdgpu_bo **bo_ptr, void **cpu_addr);
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 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
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 			   void **cpu_addr);
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 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
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@@ -275,23 +283,20 @@
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 			   uint64_t *flags);
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 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
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 			   bool evict,
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-			   struct ttm_mem_reg *new_mem);
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+			   struct ttm_resource *new_mem);
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+void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
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 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
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 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
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 		     bool shared);
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+int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
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+			     enum amdgpu_sync_mode sync_mode, void *owner,
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+			     bool intr);
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+int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
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 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
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-int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
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-			       struct amdgpu_ring *ring,
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-			       struct amdgpu_bo *bo,
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-			       struct reservation_object *resv,
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-			       struct dma_fence **fence, bool direct);
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+u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
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 int amdgpu_bo_validate(struct amdgpu_bo *bo);
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-int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
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-				  struct amdgpu_ring *ring,
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-				  struct amdgpu_bo *bo,
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-				  struct reservation_object *resv,
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-				  struct dma_fence **fence,
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-				  bool direct);
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+int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
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+			     struct dma_fence **fence);
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 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
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 					    uint32_t domain);
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@@ -326,6 +331,9 @@
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 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
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 					 struct seq_file *m);
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 #endif
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+int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
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+
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+bool amdgpu_bo_support_uswc(u64 bo_flags);
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 #endif