移去rt

hc

2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
..
..
@@ -38,7 +38,7 @@
38
38
 #include <drm/drm_crtc_helper.h>
39
39
 #include <drm/drm_fb_helper.h>
40
40
 #include <drm/drm_plane_helper.h>
41
-#include <drm/drm_fb_helper.h>
41
+#include <drm/drm_probe_helper.h>
42
42
 #include <linux/i2c.h>
43
43
 #include <linux/i2c-algo-bit.h>
44
44
 #include <linux/hrtimer.h>
..
..
@@ -46,6 +46,7 @@
46
46
 
47
47
 #include <drm/drm_dp_mst_helper.h>
48
48
 #include "modules/inc/mod_freesync.h"
49
+#include "amdgpu_dm_irq_params.h"
49
50
 
50
51
 struct amdgpu_bo;
51
52
 struct amdgpu_device;
..
..
@@ -57,9 +58,8 @@
57
58
 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
58
59
 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
59
60
 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
60
-#define to_amdgpu_plane(x)	container_of(x, struct amdgpu_plane, base)
61
61
 
62
-#define to_dm_plane_state(x)	container_of(x, struct dm_plane_state, base);
62
+#define to_dm_plane_state(x)	container_of(x, struct dm_plane_state, base)
63
63
 
64
64
 #define AMDGPU_MAX_HPD_PINS 6
65
65
 #define AMDGPU_MAX_CRTCS 6
..
..
@@ -295,13 +295,6 @@
295
295
 			      uint16_t connector_object_id,
296
296
 			      struct amdgpu_hpd *hpd,
297
297
 			      struct amdgpu_router *router);
298
-	/* it is used to enter or exit into free sync mode */
299
-	int (*notify_freesync)(struct drm_device *dev, void *data,
300
-			       struct drm_file *filp);
301
-	/* it is used to allow enablement of freesync mode */
302
-	int (*set_freesync_property)(struct drm_connector *connector,
303
-				     struct drm_property *property,
304
-				     uint64_t val);
305
298
 
306
299
 
307
300
 };
..
..
@@ -325,7 +318,7 @@
325
318
 	struct card_info *atom_card_info;
326
319
 	bool mode_config_initialized;
327
320
 	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
328
-	struct amdgpu_plane *planes[AMDGPU_MAX_PLANES];
321
+	struct drm_plane *planes[AMDGPU_MAX_PLANES];
329
322
 	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
330
323
 	/* DVI-I properties */
331
324
 	struct drm_property *coherent_mode_property;
..
..
@@ -339,8 +332,8 @@
339
332
 	struct drm_property *audio_property;
340
333
 	/* FMT dithering */
341
334
 	struct drm_property *dither_property;
342
-	/* maximum number of bits per channel for monitor color */
343
-	struct drm_property *max_bpc_property;
335
+	/* Adaptive Backlight Modulation (power feature) */
336
+	struct drm_property *abm_level_property;
344
337
 	/* hardcoded DFP edid from BIOS */
345
338
 	struct edid *bios_hardcoded_edid;
346
339
 	int bios_hardcoded_edid_size;
..
..
@@ -412,6 +405,8 @@
412
405
 	struct amdgpu_flip_work *pflip_works;
413
406
 	enum amdgpu_flip_status pflip_status;
414
407
 	int deferred_flip_completion;
408
+	/* parameters access from DM IRQ handler */
409
+	struct dm_irq_params dm_irq_params;
415
410
 	/* pll sharing */
416
411
 	struct amdgpu_atom_ss ss;
417
412
 	bool ss_enabled;
..
..
@@ -434,11 +429,6 @@
434
429
 
435
430
 	int otg_inst;
436
431
 	struct drm_pending_vblank_event *event;
437
-};
438
-
439
-struct amdgpu_plane {
440
-	struct drm_plane base;
441
-	enum drm_plane_type plane_type;
442
432
 };
443
433
 
444
434
 struct amdgpu_encoder_atom_dig {
..
..
@@ -481,6 +471,7 @@
481
471
 struct amdgpu_connector_atom_dig {
482
472
 	/* displayport */
483
473
 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
474
+	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
484
475
 	u8 dp_sink_type;
485
476
 	int dp_clock;
486
477
 	int dp_lane_count;
..
..
@@ -624,6 +615,11 @@
624
615
 			     struct drm_display_mode *adjusted_mode);
625
616
 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
626
617
 
618
+bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
619
+			bool in_vblank_irq, int *vpos,
620
+			int *hpos, ktime_t *stime, ktime_t *etime,
621
+			const struct drm_display_mode *mode);
622
+
627
623
 /* fbdev layer */
628
624
 int amdgpu_fbdev_init(struct amdgpu_device *adev);
629
625
 void amdgpu_fbdev_fini(struct amdgpu_device *adev);