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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
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@@ -25,7 +25,10 @@
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  *          Alex Deucher
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  *          Jerome Glisse
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  */
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-#include <drm/drmP.h>
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+
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+#include <linux/pci.h>
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+#include <linux/vmalloc.h>
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+
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 #include <drm/amdgpu_drm.h>
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 #ifdef CONFIG_X86
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 #include <asm/set_memory.h>
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@@ -68,7 +71,7 @@
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  */
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 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
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 {
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-	struct page *dummy_page = adev->mman.bdev.glob->dummy_read_page;
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+	struct page *dummy_page = ttm_bo_glob.dummy_read_page;
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 	if (adev->dummy_page_addr)
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 		return 0;
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@@ -112,7 +115,7 @@
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 {
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 	int r;
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-	if (adev->gart.robj == NULL) {
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+	if (adev->gart.bo == NULL) {
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 		struct amdgpu_bo_param bp;
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 		memset(&bp, 0, sizeof(bp));
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@@ -123,7 +126,7 @@
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 			AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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 		bp.type = ttm_bo_type_kernel;
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 		bp.resv = NULL;
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-		r = amdgpu_bo_create(adev, &bp, &adev->gart.robj);
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+		r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
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 		if (r) {
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 			return r;
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 		}
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@@ -145,19 +148,18 @@
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 {
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 	int r;
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-	r = amdgpu_bo_reserve(adev->gart.robj, false);
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+	r = amdgpu_bo_reserve(adev->gart.bo, false);
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 	if (unlikely(r != 0))
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 		return r;
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-	r = amdgpu_bo_pin(adev->gart.robj, AMDGPU_GEM_DOMAIN_VRAM);
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+	r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
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 	if (r) {
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-		amdgpu_bo_unreserve(adev->gart.robj);
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+		amdgpu_bo_unreserve(adev->gart.bo);
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 		return r;
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 	}
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-	r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
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+	r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
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 	if (r)
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-		amdgpu_bo_unpin(adev->gart.robj);
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-	amdgpu_bo_unreserve(adev->gart.robj);
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-	adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.robj);
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+		amdgpu_bo_unpin(adev->gart.bo);
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+	amdgpu_bo_unreserve(adev->gart.bo);
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 	return r;
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 }
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@@ -173,14 +175,14 @@
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 {
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 	int r;
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-	if (adev->gart.robj == NULL) {
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+	if (adev->gart.bo == NULL) {
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 		return;
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 	}
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-	r = amdgpu_bo_reserve(adev->gart.robj, true);
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+	r = amdgpu_bo_reserve(adev->gart.bo, true);
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 	if (likely(r == 0)) {
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-		amdgpu_bo_kunmap(adev->gart.robj);
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-		amdgpu_bo_unpin(adev->gart.robj);
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-		amdgpu_bo_unreserve(adev->gart.robj);
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+		amdgpu_bo_kunmap(adev->gart.bo);
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+		amdgpu_bo_unpin(adev->gart.bo);
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+		amdgpu_bo_unreserve(adev->gart.bo);
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 		adev->gart.ptr = NULL;
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 	}
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 }
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@@ -196,10 +198,10 @@
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  */
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 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
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 {
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-	if (adev->gart.robj == NULL) {
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+	if (adev->gart.bo == NULL) {
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 		return;
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 	}
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-	amdgpu_bo_unref(&adev->gart.robj);
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+	amdgpu_bo_unref(&adev->gart.bo);
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 }
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 /*
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@@ -249,7 +251,9 @@
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 	}
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 	mb();
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 	amdgpu_asic_flush_hdp(adev, NULL);
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-	amdgpu_gmc_flush_gpu_tlb(adev, 0);
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+	for (i = 0; i < adev->num_vmhubs; i++)
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+		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
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+
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 	return 0;
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 }
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@@ -260,6 +264,8 @@
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  * @offset: offset into the GPU's gart aperture
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  * @pages: number of pages to bind
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  * @dma_addr: DMA addresses of pages
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+ * @flags: page table entry flags
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+ * @dst: CPU address of the gart table
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  *
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  * Map the dma_addresses into GART entries (all asics).
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  * Returns 0 for success, -EINVAL for failure.
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@@ -296,6 +302,7 @@
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  * @pages: number of pages to bind
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  * @pagelist: pages to bind
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  * @dma_addr: DMA addresses of pages
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+ * @flags: page table entry flags
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  *
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  * Binds the requested pages to the gart page table
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  * (all asics).
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@@ -306,9 +313,9 @@
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 		     uint64_t flags)
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 {
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 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
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-	unsigned i,t,p;
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+	unsigned t,p;
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 #endif
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-	int r;
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+	int r, i;
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 	if (!adev->gart.ready) {
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 		WARN(1, "trying to bind memory to uninitialized GART !\n");
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@@ -332,7 +339,8 @@
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 	mb();
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 	amdgpu_asic_flush_hdp(adev, NULL);
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-	amdgpu_gmc_flush_gpu_tlb(adev, 0);
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+	for (i = 0; i < adev->num_vmhubs; i++)
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+		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
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 	return 0;
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 }
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