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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/drivers/gpio/gpio-lpc32xx.c
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@@ -1,19 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * GPIO driver for LPC32xx SoC
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  *
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  * Author: Kevin Wells <kevin.wells@nxp.com>
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  *
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  * Copyright (C) 2010 NXP Semiconductors
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #include <linux/kernel.h>
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@@ -25,36 +16,33 @@
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 #include <linux/platform_device.h>
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 #include <linux/module.h>
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18
 
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-#include <mach/hardware.h>
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-#include <mach/platform.h>
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-
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-#define LPC32XX_GPIO_P3_INP_STATE		_GPREG(0x000)
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-#define LPC32XX_GPIO_P3_OUTP_SET		_GPREG(0x004)
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-#define LPC32XX_GPIO_P3_OUTP_CLR		_GPREG(0x008)
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-#define LPC32XX_GPIO_P3_OUTP_STATE		_GPREG(0x00C)
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-#define LPC32XX_GPIO_P2_DIR_SET			_GPREG(0x010)
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-#define LPC32XX_GPIO_P2_DIR_CLR			_GPREG(0x014)
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-#define LPC32XX_GPIO_P2_DIR_STATE		_GPREG(0x018)
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-#define LPC32XX_GPIO_P2_INP_STATE		_GPREG(0x01C)
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-#define LPC32XX_GPIO_P2_OUTP_SET		_GPREG(0x020)
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-#define LPC32XX_GPIO_P2_OUTP_CLR		_GPREG(0x024)
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-#define LPC32XX_GPIO_P2_MUX_SET			_GPREG(0x028)
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-#define LPC32XX_GPIO_P2_MUX_CLR			_GPREG(0x02C)
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-#define LPC32XX_GPIO_P2_MUX_STATE		_GPREG(0x030)
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-#define LPC32XX_GPIO_P0_INP_STATE		_GPREG(0x040)
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-#define LPC32XX_GPIO_P0_OUTP_SET		_GPREG(0x044)
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-#define LPC32XX_GPIO_P0_OUTP_CLR		_GPREG(0x048)
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-#define LPC32XX_GPIO_P0_OUTP_STATE		_GPREG(0x04C)
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-#define LPC32XX_GPIO_P0_DIR_SET			_GPREG(0x050)
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-#define LPC32XX_GPIO_P0_DIR_CLR			_GPREG(0x054)
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-#define LPC32XX_GPIO_P0_DIR_STATE		_GPREG(0x058)
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-#define LPC32XX_GPIO_P1_INP_STATE		_GPREG(0x060)
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-#define LPC32XX_GPIO_P1_OUTP_SET		_GPREG(0x064)
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-#define LPC32XX_GPIO_P1_OUTP_CLR		_GPREG(0x068)
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-#define LPC32XX_GPIO_P1_OUTP_STATE		_GPREG(0x06C)
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-#define LPC32XX_GPIO_P1_DIR_SET			_GPREG(0x070)
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-#define LPC32XX_GPIO_P1_DIR_CLR			_GPREG(0x074)
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-#define LPC32XX_GPIO_P1_DIR_STATE		_GPREG(0x078)
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+#define LPC32XX_GPIO_P3_INP_STATE		(0x000)
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+#define LPC32XX_GPIO_P3_OUTP_SET		(0x004)
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+#define LPC32XX_GPIO_P3_OUTP_CLR		(0x008)
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+#define LPC32XX_GPIO_P3_OUTP_STATE		(0x00C)
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+#define LPC32XX_GPIO_P2_DIR_SET			(0x010)
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+#define LPC32XX_GPIO_P2_DIR_CLR			(0x014)
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+#define LPC32XX_GPIO_P2_DIR_STATE		(0x018)
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+#define LPC32XX_GPIO_P2_INP_STATE		(0x01C)
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+#define LPC32XX_GPIO_P2_OUTP_SET		(0x020)
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+#define LPC32XX_GPIO_P2_OUTP_CLR		(0x024)
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+#define LPC32XX_GPIO_P2_MUX_SET			(0x028)
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+#define LPC32XX_GPIO_P2_MUX_CLR			(0x02C)
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+#define LPC32XX_GPIO_P2_MUX_STATE		(0x030)
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+#define LPC32XX_GPIO_P0_INP_STATE		(0x040)
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+#define LPC32XX_GPIO_P0_OUTP_SET		(0x044)
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+#define LPC32XX_GPIO_P0_OUTP_CLR		(0x048)
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+#define LPC32XX_GPIO_P0_OUTP_STATE		(0x04C)
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+#define LPC32XX_GPIO_P0_DIR_SET			(0x050)
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+#define LPC32XX_GPIO_P0_DIR_CLR			(0x054)
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+#define LPC32XX_GPIO_P0_DIR_STATE		(0x058)
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+#define LPC32XX_GPIO_P1_INP_STATE		(0x060)
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+#define LPC32XX_GPIO_P1_OUTP_SET		(0x064)
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+#define LPC32XX_GPIO_P1_OUTP_CLR		(0x068)
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+#define LPC32XX_GPIO_P1_OUTP_STATE		(0x06C)
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+#define LPC32XX_GPIO_P1_DIR_SET			(0x070)
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+#define LPC32XX_GPIO_P1_DIR_CLR			(0x074)
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+#define LPC32XX_GPIO_P1_DIR_STATE		(0x078)
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 #define GPIO012_PIN_TO_BIT(x)			(1 << (x))
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 #define GPIO3_PIN_TO_BIT(x)			(1 << ((x) + 25))
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@@ -81,12 +69,12 @@
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 #define LPC32XX_GPO_P3_GRP	(LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
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 struct gpio_regs {
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-	void __iomem *inp_state;
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-	void __iomem *outp_state;
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-	void __iomem *outp_set;
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-	void __iomem *outp_clr;
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-	void __iomem *dir_set;
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-	void __iomem *dir_clr;
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+	unsigned long inp_state;
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+	unsigned long outp_state;
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+	unsigned long outp_set;
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+	unsigned long outp_clr;
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+	unsigned long dir_set;
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+	unsigned long dir_clr;
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 };
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 /*
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@@ -174,16 +162,27 @@
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 struct lpc32xx_gpio_chip {
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 	struct gpio_chip	chip;
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 	struct gpio_regs	*gpio_grp;
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+	void __iomem		*reg_base;
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 };
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+
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+static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset)
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+{
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+	return __raw_readl(group->reg_base + offset);
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+}
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+
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+static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset)
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+{
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+	__raw_writel(val, group->reg_base + offset);
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+}
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 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
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 	unsigned pin, int input)
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 {
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 	if (input)
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-		__raw_writel(GPIO012_PIN_TO_BIT(pin),
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+		gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
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 			group->gpio_grp->dir_clr);
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 	else
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-		__raw_writel(GPIO012_PIN_TO_BIT(pin),
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+		gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
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 			group->gpio_grp->dir_set);
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 }
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@@ -193,19 +192,19 @@
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 	u32 u = GPIO3_PIN_TO_BIT(pin);
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 	if (input)
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-		__raw_writel(u, group->gpio_grp->dir_clr);
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+		gpreg_write(group, u, group->gpio_grp->dir_clr);
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 	else
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-		__raw_writel(u, group->gpio_grp->dir_set);
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+		gpreg_write(group, u, group->gpio_grp->dir_set);
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 }
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 static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
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 	unsigned pin, int high)
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 {
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 	if (high)
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-		__raw_writel(GPIO012_PIN_TO_BIT(pin),
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+		gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
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 			group->gpio_grp->outp_set);
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 	else
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-		__raw_writel(GPIO012_PIN_TO_BIT(pin),
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+		gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
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 			group->gpio_grp->outp_clr);
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 }
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@@ -215,31 +214,31 @@
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 	u32 u = GPIO3_PIN_TO_BIT(pin);
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 	if (high)
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-		__raw_writel(u, group->gpio_grp->outp_set);
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+		gpreg_write(group, u, group->gpio_grp->outp_set);
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 	else
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-		__raw_writel(u, group->gpio_grp->outp_clr);
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+		gpreg_write(group, u, group->gpio_grp->outp_clr);
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 }
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 static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
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 	unsigned pin, int high)
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 {
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 	if (high)
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-		__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
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+		gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
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 	else
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-		__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
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+		gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
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 }
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 static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
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 	unsigned pin)
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 {
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-	return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
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+	return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state),
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 		pin);
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 }
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 static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
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 	unsigned pin)
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 {
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-	int state = __raw_readl(group->gpio_grp->inp_state);
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+	int state = gpreg_read(group, group->gpio_grp->inp_state);
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 	/*
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 	 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
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@@ -251,13 +250,13 @@
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 static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
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 	unsigned pin)
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 {
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-	return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
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+	return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin);
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 }
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 static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
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 	unsigned pin)
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 {
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-	return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
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+	return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin);
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 }
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 /*
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@@ -506,12 +505,18 @@
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 static int lpc32xx_gpio_probe(struct platform_device *pdev)
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 {
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 	int i;
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+	void __iomem *reg_base;
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+
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+	reg_base = devm_platform_ioremap_resource(pdev, 0);
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+	if (IS_ERR(reg_base))
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+		return PTR_ERR(reg_base);
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 	for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
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 		if (pdev->dev.of_node) {
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 			lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
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 			lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
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 			lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
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+			lpc32xx_gpiochip[i].reg_base = reg_base;
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 		}
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 		devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
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 				  &lpc32xx_gpiochip[i]);
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@@ -536,3 +541,7 @@
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 };
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 module_platform_driver(lpc32xx_gpio_driver);
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+
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+MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
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+MODULE_LICENSE("GPL");
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+MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");