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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/gpio/gpio-lpc18xx.c
....@@ -1,20 +1,21 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * GPIO driver for NXP LPC18xx/43xx.
34  *
5
+ * Copyright (C) 2018 Vladimir Zapolskiy <vz@mleia.com>
46  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
97  *
108  */
119 
1210 #include <linux/clk.h>
1311 #include <linux/gpio/driver.h>
1412 #include <linux/io.h>
13
+#include <linux/irqdomain.h>
1514 #include <linux/module.h>
1615 #include <linux/of.h>
16
+#include <linux/of_address.h>
1717 #include <linux/of_gpio.h>
18
+#include <linux/of_irq.h>
1819 #include <linux/pinctrl/consumer.h>
1920 #include <linux/platform_device.h>
2021 
....@@ -24,12 +25,245 @@
2425 #define LPC18XX_MAX_PORTS	8
2526 #define LPC18XX_PINS_PER_PORT	32
2627 
28
+/* LPC18xx GPIO pin interrupt controller register offsets */
29
+#define LPC18XX_GPIO_PIN_IC_ISEL	0x00
30
+#define LPC18XX_GPIO_PIN_IC_IENR	0x04
31
+#define LPC18XX_GPIO_PIN_IC_SIENR	0x08
32
+#define LPC18XX_GPIO_PIN_IC_CIENR	0x0c
33
+#define LPC18XX_GPIO_PIN_IC_IENF	0x10
34
+#define LPC18XX_GPIO_PIN_IC_SIENF	0x14
35
+#define LPC18XX_GPIO_PIN_IC_CIENF	0x18
36
+#define LPC18XX_GPIO_PIN_IC_RISE	0x1c
37
+#define LPC18XX_GPIO_PIN_IC_FALL	0x20
38
+#define LPC18XX_GPIO_PIN_IC_IST		0x24
39
+
40
+#define NR_LPC18XX_GPIO_PIN_IC_IRQS	8
41
+
42
+struct lpc18xx_gpio_pin_ic {
43
+	void __iomem *base;
44
+	struct irq_domain *domain;
45
+	struct raw_spinlock lock;
46
+};
47
+
2748 struct lpc18xx_gpio_chip {
2849 	struct gpio_chip gpio;
2950 	void __iomem *base;
3051 	struct clk *clk;
52
+	struct lpc18xx_gpio_pin_ic *pin_ic;
3153 	spinlock_t lock;
3254 };
55
+
56
+static inline void lpc18xx_gpio_pin_ic_isel(struct lpc18xx_gpio_pin_ic *ic,
57
+					    u32 pin, bool set)
58
+{
59
+	u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL);
60
+
61
+	if (set)
62
+		val &= ~BIT(pin);
63
+	else
64
+		val |= BIT(pin);
65
+
66
+	writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL);
67
+}
68
+
69
+static inline void lpc18xx_gpio_pin_ic_set(struct lpc18xx_gpio_pin_ic *ic,
70
+					   u32 pin, u32 reg)
71
+{
72
+	writel_relaxed(BIT(pin), ic->base + reg);
73
+}
74
+
75
+static void lpc18xx_gpio_pin_ic_mask(struct irq_data *d)
76
+{
77
+	struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
78
+	u32 type = irqd_get_trigger_type(d);
79
+
80
+	raw_spin_lock(&ic->lock);
81
+
82
+	if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING)
83
+		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
84
+					LPC18XX_GPIO_PIN_IC_CIENR);
85
+
86
+	if (type & IRQ_TYPE_EDGE_FALLING)
87
+		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
88
+					LPC18XX_GPIO_PIN_IC_CIENF);
89
+
90
+	raw_spin_unlock(&ic->lock);
91
+
92
+	irq_chip_mask_parent(d);
93
+}
94
+
95
+static void lpc18xx_gpio_pin_ic_unmask(struct irq_data *d)
96
+{
97
+	struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
98
+	u32 type = irqd_get_trigger_type(d);
99
+
100
+	raw_spin_lock(&ic->lock);
101
+
102
+	if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING)
103
+		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
104
+					LPC18XX_GPIO_PIN_IC_SIENR);
105
+
106
+	if (type & IRQ_TYPE_EDGE_FALLING)
107
+		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
108
+					LPC18XX_GPIO_PIN_IC_SIENF);
109
+
110
+	raw_spin_unlock(&ic->lock);
111
+
112
+	irq_chip_unmask_parent(d);
113
+}
114
+
115
+static void lpc18xx_gpio_pin_ic_eoi(struct irq_data *d)
116
+{
117
+	struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
118
+	u32 type = irqd_get_trigger_type(d);
119
+
120
+	raw_spin_lock(&ic->lock);
121
+
122
+	if (type & IRQ_TYPE_EDGE_BOTH)
123
+		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
124
+					LPC18XX_GPIO_PIN_IC_IST);
125
+
126
+	raw_spin_unlock(&ic->lock);
127
+
128
+	irq_chip_eoi_parent(d);
129
+}
130
+
131
+static int lpc18xx_gpio_pin_ic_set_type(struct irq_data *d, unsigned int type)
132
+{
133
+	struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
134
+
135
+	raw_spin_lock(&ic->lock);
136
+
137
+	if (type & IRQ_TYPE_LEVEL_HIGH) {
138
+		lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true);
139
+		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
140
+					LPC18XX_GPIO_PIN_IC_SIENF);
141
+	} else if (type & IRQ_TYPE_LEVEL_LOW) {
142
+		lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true);
143
+		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
144
+					LPC18XX_GPIO_PIN_IC_CIENF);
145
+	} else {
146
+		lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, false);
147
+	}
148
+
149
+	raw_spin_unlock(&ic->lock);
150
+
151
+	return 0;
152
+}
153
+
154
+static struct irq_chip lpc18xx_gpio_pin_ic = {
155
+	.name		= "LPC18xx GPIO pin",
156
+	.irq_mask	= lpc18xx_gpio_pin_ic_mask,
157
+	.irq_unmask	= lpc18xx_gpio_pin_ic_unmask,
158
+	.irq_eoi	= lpc18xx_gpio_pin_ic_eoi,
159
+	.irq_set_type	= lpc18xx_gpio_pin_ic_set_type,
160
+	.flags		= IRQCHIP_SET_TYPE_MASKED,
161
+};
162
+
163
+static int lpc18xx_gpio_pin_ic_domain_alloc(struct irq_domain *domain,
164
+					    unsigned int virq,
165
+					    unsigned int nr_irqs, void *data)
166
+{
167
+	struct irq_fwspec parent_fwspec, *fwspec = data;
168
+	struct lpc18xx_gpio_pin_ic *ic = domain->host_data;
169
+	irq_hw_number_t hwirq;
170
+	int ret;
171
+
172
+	if (nr_irqs != 1)
173
+		return -EINVAL;
174
+
175
+	hwirq = fwspec->param[0];
176
+	if (hwirq >= NR_LPC18XX_GPIO_PIN_IC_IRQS)
177
+		return -EINVAL;
178
+
179
+	/*
180
+	 * All LPC18xx/LPC43xx GPIO pin hardware interrupts are translated
181
+	 * into edge interrupts 32...39 on parent Cortex-M3/M4 NVIC
182
+	 */
183
+	parent_fwspec.fwnode = domain->parent->fwnode;
184
+	parent_fwspec.param_count = 1;
185
+	parent_fwspec.param[0] = hwirq + 32;
186
+
187
+	ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
188
+	if (ret < 0) {
189
+		pr_err("failed to allocate parent irq %u: %d\n",
190
+		       parent_fwspec.param[0], ret);
191
+		return ret;
192
+	}
193
+
194
+	return irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
195
+					     &lpc18xx_gpio_pin_ic, ic);
196
+}
197
+
198
+static const struct irq_domain_ops lpc18xx_gpio_pin_ic_domain_ops = {
199
+	.alloc	= lpc18xx_gpio_pin_ic_domain_alloc,
200
+	.xlate	= irq_domain_xlate_twocell,
201
+	.free	= irq_domain_free_irqs_common,
202
+};
203
+
204
+static int lpc18xx_gpio_pin_ic_probe(struct lpc18xx_gpio_chip *gc)
205
+{
206
+	struct device *dev = gc->gpio.parent;
207
+	struct irq_domain *parent_domain;
208
+	struct device_node *parent_node;
209
+	struct lpc18xx_gpio_pin_ic *ic;
210
+	struct resource res;
211
+	int ret, index;
212
+
213
+	parent_node = of_irq_find_parent(dev->of_node);
214
+	if (!parent_node)
215
+		return -ENXIO;
216
+
217
+	parent_domain = irq_find_host(parent_node);
218
+	of_node_put(parent_node);
219
+	if (!parent_domain)
220
+		return -ENXIO;
221
+
222
+	ic = devm_kzalloc(dev, sizeof(*ic), GFP_KERNEL);
223
+	if (!ic)
224
+		return -ENOMEM;
225
+
226
+	index = of_property_match_string(dev->of_node, "reg-names",
227
+					 "gpio-pin-ic");
228
+	if (index < 0) {
229
+		ret = -ENODEV;
230
+		goto free_ic;
231
+	}
232
+
233
+	ret = of_address_to_resource(dev->of_node, index, &res);
234
+	if (ret < 0)
235
+		goto free_ic;
236
+
237
+	ic->base = devm_ioremap_resource(dev, &res);
238
+	if (IS_ERR(ic->base)) {
239
+		ret = PTR_ERR(ic->base);
240
+		goto free_ic;
241
+	}
242
+
243
+	raw_spin_lock_init(&ic->lock);
244
+
245
+	ic->domain = irq_domain_add_hierarchy(parent_domain, 0,
246
+					      NR_LPC18XX_GPIO_PIN_IC_IRQS,
247
+					      dev->of_node,
248
+					      &lpc18xx_gpio_pin_ic_domain_ops,
249
+					      ic);
250
+	if (!ic->domain) {
251
+		pr_err("unable to add irq domain\n");
252
+		ret = -ENODEV;
253
+		goto free_iomap;
254
+	}
255
+
256
+	gc->pin_ic = ic;
257
+
258
+	return 0;
259
+
260
+free_iomap:
261
+	devm_iounmap(dev, ic->base);
262
+free_ic:
263
+	devm_kfree(dev, ic);
264
+
265
+	return ret;
266
+}
33267 
34268 static void lpc18xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
35269 {
....@@ -92,44 +326,58 @@
92326 
93327 static int lpc18xx_gpio_probe(struct platform_device *pdev)
94328 {
329
+	struct device *dev = &pdev->dev;
95330 	struct lpc18xx_gpio_chip *gc;
96
-	struct resource *res;
97
-	int ret;
331
+	int index, ret;
98332 
99
-	gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
333
+	gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
100334 	if (!gc)
101335 		return -ENOMEM;
102336 
103337 	gc->gpio = lpc18xx_chip;
104338 	platform_set_drvdata(pdev, gc);
105339 
106
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
107
-	gc->base = devm_ioremap_resource(&pdev->dev, res);
340
+	index = of_property_match_string(dev->of_node, "reg-names", "gpio");
341
+	if (index < 0) {
342
+		/* To support backward compatibility take the first resource */
343
+		gc->base = devm_platform_ioremap_resource(pdev, 0);
344
+	} else {
345
+		struct resource res;
346
+
347
+		ret = of_address_to_resource(dev->of_node, index, &res);
348
+		if (ret < 0)
349
+			return ret;
350
+
351
+		gc->base = devm_ioremap_resource(dev, &res);
352
+	}
108353 	if (IS_ERR(gc->base))
109354 		return PTR_ERR(gc->base);
110355 
111
-	gc->clk = devm_clk_get(&pdev->dev, NULL);
356
+	gc->clk = devm_clk_get(dev, NULL);
112357 	if (IS_ERR(gc->clk)) {
113
-		dev_err(&pdev->dev, "input clock not found\n");
358
+		dev_err(dev, "input clock not found\n");
114359 		return PTR_ERR(gc->clk);
115360 	}
116361 
117362 	ret = clk_prepare_enable(gc->clk);
118363 	if (ret) {
119
-		dev_err(&pdev->dev, "unable to enable clock\n");
364
+		dev_err(dev, "unable to enable clock\n");
120365 		return ret;
121366 	}
122367 
123368 	spin_lock_init(&gc->lock);
124369 
125
-	gc->gpio.parent = &pdev->dev;
370
+	gc->gpio.parent = dev;
126371 
127
-	ret = gpiochip_add_data(&gc->gpio, gc);
372
+	ret = devm_gpiochip_add_data(dev, &gc->gpio, gc);
128373 	if (ret) {
129
-		dev_err(&pdev->dev, "failed to add gpio chip\n");
374
+		dev_err(dev, "failed to add gpio chip\n");
130375 		clk_disable_unprepare(gc->clk);
131376 		return ret;
132377 	}
378
+
379
+	/* On error GPIO pin interrupt controller just won't be registered */
380
+	lpc18xx_gpio_pin_ic_probe(gc);
133381 
134382 	return 0;
135383 }
....@@ -138,7 +386,9 @@
138386 {
139387 	struct lpc18xx_gpio_chip *gc = platform_get_drvdata(pdev);
140388 
141
-	gpiochip_remove(&gc->gpio);
389
+	if (gc->pin_ic)
390
+		irq_domain_remove(gc->pin_ic->domain);
391
+
142392 	clk_disable_unprepare(gc->clk);
143393 
144394 	return 0;
....@@ -161,5 +411,6 @@
161411 module_platform_driver(lpc18xx_gpio_driver);
162412 
163413 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
414
+MODULE_AUTHOR("Vladimir Zapolskiy <vz@mleia.com>");
164415 MODULE_DESCRIPTION("GPIO driver for LPC18xx/43xx");
165416 MODULE_LICENSE("GPL v2");