| .. | .. |
|---|
| 1 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
|---|
| 2 | | -/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */ |
|---|
| 2 | +/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ |
|---|
| 3 | 3 | |
|---|
| 4 | 4 | #ifndef _CC_CRYPTO_CTX_H_ |
|---|
| 5 | 5 | #define _CC_CRYPTO_CTX_H_ |
|---|
| .. | .. |
|---|
| 55 | 55 | |
|---|
| 56 | 56 | #define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX |
|---|
| 57 | 57 | |
|---|
| 58 | +#define CC_CPP_NUM_SLOTS 8 |
|---|
| 59 | +#define CC_CPP_NUM_ALGS 2 |
|---|
| 60 | + |
|---|
| 61 | +enum cc_cpp_alg { |
|---|
| 62 | + CC_CPP_SM4 = 1, |
|---|
| 63 | + CC_CPP_AES = 0 |
|---|
| 64 | +}; |
|---|
| 65 | + |
|---|
| 58 | 66 | enum drv_engine_type { |
|---|
| 59 | 67 | DRV_ENGINE_NULL = 0, |
|---|
| 60 | 68 | DRV_ENGINE_AES = 1, |
|---|
| .. | .. |
|---|
| 100 | 108 | DRV_CIPHER_CBC_CTS = 11, |
|---|
| 101 | 109 | DRV_CIPHER_GCTR = 12, |
|---|
| 102 | 110 | DRV_CIPHER_ESSIV = 13, |
|---|
| 103 | | - DRV_CIPHER_BITLOCKER = 14, |
|---|
| 104 | 111 | DRV_CIPHER_RESERVE32B = S32_MAX |
|---|
| 105 | 112 | }; |
|---|
| 106 | 113 | |
|---|
| .. | .. |
|---|
| 115 | 122 | DRV_HASH_CBC_MAC = 6, |
|---|
| 116 | 123 | DRV_HASH_XCBC_MAC = 7, |
|---|
| 117 | 124 | DRV_HASH_CMAC = 8, |
|---|
| 118 | | - DRV_HASH_MODE_NUM = 9, |
|---|
| 125 | + DRV_HASH_SM3 = 9, |
|---|
| 126 | + DRV_HASH_MODE_NUM = 10, |
|---|
| 119 | 127 | DRV_HASH_RESERVE32B = S32_MAX |
|---|
| 120 | 128 | }; |
|---|
| 121 | 129 | |
|---|
| .. | .. |
|---|
| 127 | 135 | DRV_HASH_HW_SHA512 = 4, |
|---|
| 128 | 136 | DRV_HASH_HW_SHA384 = 12, |
|---|
| 129 | 137 | DRV_HASH_HW_GHASH = 6, |
|---|
| 138 | + DRV_HASH_HW_SM3 = 14, |
|---|
| 130 | 139 | DRV_HASH_HW_RESERVE32B = S32_MAX |
|---|
| 131 | 140 | }; |
|---|
| 132 | 141 | |
|---|