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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/clocksource/timer-imx-tpm.c
....@@ -8,9 +8,9 @@
88 #include <linux/clocksource.h>
99 #include <linux/delay.h>
1010 #include <linux/interrupt.h>
11
-#include <linux/of_address.h>
12
-#include <linux/of_irq.h>
1311 #include <linux/sched_clock.h>
12
+
13
+#include "timer-of.h"
1414 
1515 #define TPM_PARAM			0x4
1616 #define TPM_PARAM_WIDTH_SHIFT		16
....@@ -33,9 +33,7 @@
3333 #define TPM_C0V				0x24
3434 
3535 static int counter_width;
36
-static int rating;
3736 static void __iomem *timer_base;
38
-static struct clock_event_device clockevent_tpm;
3937 
4038 static inline void tpm_timer_disable(void)
4139 {
....@@ -63,34 +61,23 @@
6361 	writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS);
6462 }
6563 
66
-static struct delay_timer tpm_delay_timer;
67
-
6864 static inline unsigned long tpm_read_counter(void)
6965 {
7066 	return readl(timer_base + TPM_CNT);
7167 }
7268 
69
+#if defined(CONFIG_ARM)
70
+static struct delay_timer tpm_delay_timer;
71
+
7372 static unsigned long tpm_read_current_timer(void)
7473 {
7574 	return tpm_read_counter();
7675 }
76
+#endif
7777 
7878 static u64 notrace tpm_read_sched_clock(void)
7979 {
8080 	return tpm_read_counter();
81
-}
82
-
83
-static int __init tpm_clocksource_init(unsigned long rate)
84
-{
85
-	tpm_delay_timer.read_current_timer = &tpm_read_current_timer;
86
-	tpm_delay_timer.freq = rate;
87
-	register_current_timer_delay(&tpm_delay_timer);
88
-
89
-	sched_clock_register(tpm_read_sched_clock, counter_width, rate);
90
-
91
-	return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm",
92
-				     rate, rating, counter_width,
93
-				     clocksource_mmio_readl_up);
9481 }
9582 
9683 static int tpm_set_next_event(unsigned long delta,
....@@ -137,74 +124,82 @@
137124 	return IRQ_HANDLED;
138125 }
139126 
140
-static struct clock_event_device clockevent_tpm = {
141
-	.name			= "i.MX7ULP TPM Timer",
142
-	.features		= CLOCK_EVT_FEAT_ONESHOT,
143
-	.set_state_oneshot	= tpm_set_state_oneshot,
144
-	.set_next_event		= tpm_set_next_event,
145
-	.set_state_shutdown	= tpm_set_state_shutdown,
127
+static struct timer_of to_tpm = {
128
+	.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
129
+	.clkevt = {
130
+		.name			= "i.MX7ULP TPM Timer",
131
+		.rating			= 200,
132
+		.features		= CLOCK_EVT_FEAT_ONESHOT,
133
+		.set_state_shutdown	= tpm_set_state_shutdown,
134
+		.set_state_oneshot	= tpm_set_state_oneshot,
135
+		.set_next_event		= tpm_set_next_event,
136
+		.cpumask		= cpu_possible_mask,
137
+	},
138
+	.of_irq = {
139
+		.handler		= tpm_timer_interrupt,
140
+		.flags			= IRQF_TIMER | IRQF_IRQPOLL,
141
+	},
142
+	.of_clk = {
143
+		.name = "per",
144
+	},
146145 };
147146 
148
-static int __init tpm_clockevent_init(unsigned long rate, int irq)
147
+static int __init tpm_clocksource_init(void)
149148 {
150
-	int ret;
149
+#if defined(CONFIG_ARM)
150
+	tpm_delay_timer.read_current_timer = &tpm_read_current_timer;
151
+	tpm_delay_timer.freq = timer_of_rate(&to_tpm) >> 3;
152
+	register_current_timer_delay(&tpm_delay_timer);
153
+#endif
151154 
152
-	ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
153
-			  "i.MX7ULP TPM Timer", &clockevent_tpm);
155
+	sched_clock_register(tpm_read_sched_clock, counter_width,
156
+			     timer_of_rate(&to_tpm) >> 3);
154157 
155
-	clockevent_tpm.rating = rating;
156
-	clockevent_tpm.cpumask = cpumask_of(0);
157
-	clockevent_tpm.irq = irq;
158
-	clockevents_config_and_register(&clockevent_tpm, rate, 300,
159
-					GENMASK(counter_width - 1, 1));
158
+	return clocksource_mmio_init(timer_base + TPM_CNT,
159
+				     "imx-tpm",
160
+				     timer_of_rate(&to_tpm) >> 3,
161
+				     to_tpm.clkevt.rating,
162
+				     counter_width,
163
+				     clocksource_mmio_readl_up);
164
+}
160165 
161
-	return ret;
166
+static void __init tpm_clockevent_init(void)
167
+{
168
+	clockevents_config_and_register(&to_tpm.clkevt,
169
+					timer_of_rate(&to_tpm) >> 3,
170
+					300,
171
+					GENMASK(counter_width - 1,
172
+					1));
162173 }
163174 
164175 static int __init tpm_timer_init(struct device_node *np)
165176 {
166
-	struct clk *ipg, *per;
167
-	int irq, ret;
168
-	u32 rate;
169
-
170
-	timer_base = of_iomap(np, 0);
171
-	if (!timer_base) {
172
-		pr_err("tpm: failed to get base address\n");
173
-		return -ENXIO;
174
-	}
175
-
176
-	irq = irq_of_parse_and_map(np, 0);
177
-	if (!irq) {
178
-		pr_err("tpm: failed to get irq\n");
179
-		ret = -ENOENT;
180
-		goto err_iomap;
181
-	}
177
+	struct clk *ipg;
178
+	int ret;
182179 
183180 	ipg = of_clk_get_by_name(np, "ipg");
184
-	per = of_clk_get_by_name(np, "per");
185
-	if (IS_ERR(ipg) || IS_ERR(per)) {
186
-		pr_err("tpm: failed to get ipg or per clk\n");
187
-		ret = -ENODEV;
188
-		goto err_clk_get;
181
+	if (IS_ERR(ipg)) {
182
+		pr_err("tpm: failed to get ipg clk\n");
183
+		return -ENODEV;
189184 	}
190
-
191185 	/* enable clk before accessing registers */
192186 	ret = clk_prepare_enable(ipg);
193187 	if (ret) {
194188 		pr_err("tpm: ipg clock enable failed (%d)\n", ret);
195
-		goto err_clk_get;
189
+		clk_put(ipg);
190
+		return ret;
196191 	}
197192 
198
-	ret = clk_prepare_enable(per);
199
-	if (ret) {
200
-		pr_err("tpm: per clock enable failed (%d)\n", ret);
201
-		goto err_per_clk_enable;
202
-	}
193
+	ret = timer_of_init(np, &to_tpm);
194
+	if (ret)
195
+		return ret;
203196 
204
-	counter_width = (readl(timer_base + TPM_PARAM) & TPM_PARAM_WIDTH_MASK)
205
-		>> TPM_PARAM_WIDTH_SHIFT;
197
+	timer_base = timer_of_base(&to_tpm);
198
+
199
+	counter_width = (readl(timer_base + TPM_PARAM)
200
+		& TPM_PARAM_WIDTH_MASK) >> TPM_PARAM_WIDTH_SHIFT;
206201 	/* use rating 200 for 32-bit counter and 150 for 16-bit counter */
207
-	rating = counter_width == 0x20 ? 200 : 150;
202
+	to_tpm.clkevt.rating = counter_width == 0x20 ? 200 : 150;
208203 
209204 	/*
210205 	 * Initialize tpm module to a known state
....@@ -229,29 +224,13 @@
229224 	writel(TPM_SC_CMOD_INC_PER_CNT |
230225 		(counter_width == 0x20 ?
231226 		TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX),
232
-		     timer_base + TPM_SC);
227
+		timer_base + TPM_SC);
233228 
234229 	/* set MOD register to maximum for free running mode */
235230 	writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);
236231 
237
-	rate = clk_get_rate(per) >> 3;
238
-	ret = tpm_clocksource_init(rate);
239
-	if (ret)
240
-		goto err_per_clk_enable;
232
+	tpm_clockevent_init();
241233 
242
-	ret = tpm_clockevent_init(rate, irq);
243
-	if (ret)
244
-		goto err_per_clk_enable;
245
-
246
-	return 0;
247
-
248
-err_per_clk_enable:
249
-	clk_disable_unprepare(ipg);
250
-err_clk_get:
251
-	clk_put(per);
252
-	clk_put(ipg);
253
-err_iomap:
254
-	iounmap(timer_base);
255
-	return ret;
234
+	return tpm_clocksource_init();
256235 }
257236 TIMER_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);