forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/drivers/base/regmap/regmap-irq.c
....@@ -1,14 +1,10 @@
1
-/*
2
- * regmap based irq_chip
3
- *
4
- * Copyright 2011 Wolfson Microelectronics plc
5
- *
6
- * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License version 2 as
10
- * published by the Free Software Foundation.
11
- */
1
+// SPDX-License-Identifier: GPL-2.0
2
+//
3
+// regmap based irq_chip
4
+//
5
+// Copyright 2011 Wolfson Microelectronics plc
6
+//
7
+// Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
128 
139 #include <linux/device.h>
1410 #include <linux/export.h>
....@@ -35,6 +31,7 @@
3531 	int wake_count;
3632 
3733 	void *status_reg_buf;
34
+	unsigned int *main_status_buf;
3835 	unsigned int *status_buf;
3936 	unsigned int *mask_buf;
4037 	unsigned int *mask_buf_def;
....@@ -44,6 +41,8 @@
4441 
4542 	unsigned int irq_reg_stride;
4643 	unsigned int type_reg_stride;
44
+
45
+	bool clear_status:1;
4746 };
4847 
4948 static inline const
....@@ -77,12 +76,27 @@
7776 	int i, ret;
7877 	u32 reg;
7978 	u32 unmask_offset;
79
+	u32 val;
8080 
8181 	if (d->chip->runtime_pm) {
8282 		ret = pm_runtime_get_sync(map->dev);
8383 		if (ret < 0)
8484 			dev_err(map->dev, "IRQ sync failed to resume: %d\n",
8585 				ret);
86
+	}
87
+
88
+	if (d->clear_status) {
89
+		for (i = 0; i < d->chip->num_regs; i++) {
90
+			reg = d->chip->status_base +
91
+				(i * map->reg_stride * d->irq_reg_stride);
92
+
93
+			ret = regmap_read(map, reg, &val);
94
+			if (ret)
95
+				dev_err(d->map->dev,
96
+					"Failed to clear the interrupt status bits\n");
97
+		}
98
+
99
+		d->clear_status = false;
86100 	}
87101 
88102 	/*
....@@ -154,29 +168,35 @@
154168 				ret = regmap_write(map, reg, ~d->mask_buf[i]);
155169 			else
156170 				ret = regmap_write(map, reg, d->mask_buf[i]);
157
-			/* some chips needs to clear ack reg after ack */
158
-			if (d->chip->clear_ack)
159
-				ret = regmap_write(map, reg, 0x0);
171
+			if (d->chip->clear_ack) {
172
+				if (d->chip->ack_invert && !ret)
173
+					ret = regmap_write(map, reg, UINT_MAX);
174
+				else if (!ret)
175
+					ret = regmap_write(map, reg, 0);
176
+			}
160177 			if (ret != 0)
161178 				dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
162179 					reg, ret);
163180 		}
164181 	}
165182 
166
-	for (i = 0; i < d->chip->num_type_reg; i++) {
167
-		if (!d->type_buf_def[i])
168
-			continue;
169
-		reg = d->chip->type_base +
170
-			(i * map->reg_stride * d->type_reg_stride);
171
-		if (d->chip->type_invert)
172
-			ret = regmap_irq_update_bits(d, reg,
173
-				d->type_buf_def[i], ~d->type_buf[i]);
174
-		else
175
-			ret = regmap_irq_update_bits(d, reg,
176
-				d->type_buf_def[i], d->type_buf[i]);
177
-		if (ret != 0)
178
-			dev_err(d->map->dev, "Failed to sync type in %x\n",
179
-				reg);
183
+	/* Don't update the type bits if we're using mask bits for irq type. */
184
+	if (!d->chip->type_in_mask) {
185
+		for (i = 0; i < d->chip->num_type_reg; i++) {
186
+			if (!d->type_buf_def[i])
187
+				continue;
188
+			reg = d->chip->type_base +
189
+				(i * map->reg_stride * d->type_reg_stride);
190
+			if (d->chip->type_invert)
191
+				ret = regmap_irq_update_bits(d, reg,
192
+					d->type_buf_def[i], ~d->type_buf[i]);
193
+			else
194
+				ret = regmap_irq_update_bits(d, reg,
195
+					d->type_buf_def[i], d->type_buf[i]);
196
+			if (ret != 0)
197
+				dev_err(d->map->dev, "Failed to sync type in %x\n",
198
+					reg);
199
+		}
180200 	}
181201 
182202 	if (d->chip->runtime_pm)
....@@ -200,8 +220,31 @@
200220 	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
201221 	struct regmap *map = d->map;
202222 	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
223
+	unsigned int reg = irq_data->reg_offset / map->reg_stride;
224
+	unsigned int mask, type;
203225 
204
-	d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
226
+	type = irq_data->type.type_falling_val | irq_data->type.type_rising_val;
227
+
228
+	/*
229
+	 * The type_in_mask flag means that the underlying hardware uses
230
+	 * separate mask bits for rising and falling edge interrupts, but
231
+	 * we want to make them into a single virtual interrupt with
232
+	 * configurable edge.
233
+	 *
234
+	 * If the interrupt we're enabling defines the falling or rising
235
+	 * masks then instead of using the regular mask bits for this
236
+	 * interrupt, use the value previously written to the type buffer
237
+	 * at the corresponding offset in regmap_irq_set_type().
238
+	 */
239
+	if (d->chip->type_in_mask && type)
240
+		mask = d->type_buf[reg] & irq_data->mask;
241
+	else
242
+		mask = irq_data->mask;
243
+
244
+	if (d->chip->clear_on_unmask)
245
+		d->clear_status = true;
246
+
247
+	d->mask_buf[reg] &= ~mask;
205248 }
206249 
207250 static void regmap_irq_disable(struct irq_data *data)
....@@ -218,27 +261,42 @@
218261 	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
219262 	struct regmap *map = d->map;
220263 	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
221
-	int reg = irq_data->type_reg_offset / map->reg_stride;
264
+	int reg;
265
+	const struct regmap_irq_type *t = &irq_data->type;
222266 
223
-	if (!(irq_data->type_rising_mask | irq_data->type_falling_mask))
267
+	if ((t->types_supported & type) != type)
224268 		return 0;
225269 
226
-	d->type_buf[reg] &= ~(irq_data->type_falling_mask |
227
-					irq_data->type_rising_mask);
270
+	reg = t->type_reg_offset / map->reg_stride;
271
+
272
+	if (t->type_reg_mask)
273
+		d->type_buf[reg] &= ~t->type_reg_mask;
274
+	else
275
+		d->type_buf[reg] &= ~(t->type_falling_val |
276
+				      t->type_rising_val |
277
+				      t->type_level_low_val |
278
+				      t->type_level_high_val);
228279 	switch (type) {
229280 	case IRQ_TYPE_EDGE_FALLING:
230
-		d->type_buf[reg] |= irq_data->type_falling_mask;
281
+		d->type_buf[reg] |= t->type_falling_val;
231282 		break;
232283 
233284 	case IRQ_TYPE_EDGE_RISING:
234
-		d->type_buf[reg] |= irq_data->type_rising_mask;
285
+		d->type_buf[reg] |= t->type_rising_val;
235286 		break;
236287 
237288 	case IRQ_TYPE_EDGE_BOTH:
238
-		d->type_buf[reg] |= (irq_data->type_falling_mask |
239
-					irq_data->type_rising_mask);
289
+		d->type_buf[reg] |= (t->type_falling_val |
290
+					t->type_rising_val);
240291 		break;
241292 
293
+	case IRQ_TYPE_LEVEL_HIGH:
294
+		d->type_buf[reg] |= t->type_level_high_val;
295
+		break;
296
+
297
+	case IRQ_TYPE_LEVEL_LOW:
298
+		d->type_buf[reg] |= t->type_level_low_val;
299
+		break;
242300 	default:
243301 		return -EINVAL;
244302 	}
....@@ -275,6 +333,33 @@
275333 	.irq_set_wake		= regmap_irq_set_wake,
276334 };
277335 
336
+static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
337
+					   unsigned int b)
338
+{
339
+	const struct regmap_irq_chip *chip = data->chip;
340
+	struct regmap *map = data->map;
341
+	struct regmap_irq_sub_irq_map *subreg;
342
+	int i, ret = 0;
343
+
344
+	if (!chip->sub_reg_offsets) {
345
+		/* Assume linear mapping */
346
+		ret = regmap_read(map, chip->status_base +
347
+				  (b * map->reg_stride * data->irq_reg_stride),
348
+				   &data->status_buf[b]);
349
+	} else {
350
+		subreg = &chip->sub_reg_offsets[b];
351
+		for (i = 0; i < subreg->num_regs; i++) {
352
+			unsigned int offset = subreg->offset[i];
353
+
354
+			ret = regmap_read(map, chip->status_base + offset,
355
+					  &data->status_buf[offset]);
356
+			if (ret)
357
+				break;
358
+		}
359
+	}
360
+	return ret;
361
+}
362
+
278363 static irqreturn_t regmap_irq_thread(int irq, void *d)
279364 {
280365 	struct regmap_irq_chip_data *data = d;
....@@ -292,17 +377,68 @@
292377 		if (ret < 0) {
293378 			dev_err(map->dev, "IRQ thread failed to resume: %d\n",
294379 				ret);
295
-			pm_runtime_put(map->dev);
296380 			goto exit;
297381 		}
298382 	}
299383 
300384 	/*
301
-	 * Read in the statuses, using a single bulk read if possible
302
-	 * in order to reduce the I/O overheads.
385
+	 * Read only registers with active IRQs if the chip has 'main status
386
+	 * register'. Else read in the statuses, using a single bulk read if
387
+	 * possible in order to reduce the I/O overheads.
303388 	 */
304
-	if (!map->use_single_read && map->reg_stride == 1 &&
305
-	    data->irq_reg_stride == 1) {
389
+
390
+	if (chip->num_main_regs) {
391
+		unsigned int max_main_bits;
392
+		unsigned long size;
393
+
394
+		size = chip->num_regs * sizeof(unsigned int);
395
+
396
+		max_main_bits = (chip->num_main_status_bits) ?
397
+				 chip->num_main_status_bits : chip->num_regs;
398
+		/* Clear the status buf as we don't read all status regs */
399
+		memset(data->status_buf, 0, size);
400
+
401
+		/* We could support bulk read for main status registers
402
+		 * but I don't expect to see devices with really many main
403
+		 * status registers so let's only support single reads for the
404
+		 * sake of simplicity. and add bulk reads only if needed
405
+		 */
406
+		for (i = 0; i < chip->num_main_regs; i++) {
407
+			ret = regmap_read(map, chip->main_status +
408
+				  (i * map->reg_stride
409
+				   * data->irq_reg_stride),
410
+				  &data->main_status_buf[i]);
411
+			if (ret) {
412
+				dev_err(map->dev,
413
+					"Failed to read IRQ status %d\n",
414
+					ret);
415
+				goto exit;
416
+			}
417
+		}
418
+
419
+		/* Read sub registers with active IRQs */
420
+		for (i = 0; i < chip->num_main_regs; i++) {
421
+			unsigned int b;
422
+			const unsigned long mreg = data->main_status_buf[i];
423
+
424
+			for_each_set_bit(b, &mreg, map->format.val_bytes * 8) {
425
+				if (i * map->format.val_bytes * 8 + b >
426
+				    max_main_bits)
427
+					break;
428
+				ret = read_sub_irq_data(data, b);
429
+
430
+				if (ret != 0) {
431
+					dev_err(map->dev,
432
+						"Failed to read IRQ status %d\n",
433
+						ret);
434
+					goto exit;
435
+				}
436
+			}
437
+
438
+		}
439
+	} else if (!map->use_single_read && map->reg_stride == 1 &&
440
+		   data->irq_reg_stride == 1) {
441
+
306442 		u8 *buf8 = data->status_reg_buf;
307443 		u16 *buf16 = data->status_reg_buf;
308444 		u32 *buf32 = data->status_reg_buf;
....@@ -346,8 +482,6 @@
346482 				dev_err(map->dev,
347483 					"Failed to read IRQ status: %d\n",
348484 					ret);
349
-				if (chip->runtime_pm)
350
-					pm_runtime_put(map->dev);
351485 				goto exit;
352486 			}
353487 		}
....@@ -366,10 +500,18 @@
366500 		if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
367501 			reg = chip->ack_base +
368502 				(i * map->reg_stride * data->irq_reg_stride);
369
-			ret = regmap_write(map, reg, data->status_buf[i]);
370
-			/* some chips needs to clear ack reg after ack */
371
-			if (chip->clear_ack)
372
-				ret = regmap_write(map, reg, 0x0);
503
+			if (chip->ack_invert)
504
+				ret = regmap_write(map, reg,
505
+						~data->status_buf[i]);
506
+			else
507
+				ret = regmap_write(map, reg,
508
+						data->status_buf[i]);
509
+			if (chip->clear_ack) {
510
+				if (chip->ack_invert && !ret)
511
+					ret = regmap_write(map, reg, UINT_MAX);
512
+				else if (!ret)
513
+					ret = regmap_write(map, reg, 0);
514
+			}
373515 			if (ret != 0)
374516 				dev_err(map->dev, "Failed to ack 0x%x: %d\n",
375517 					reg, ret);
....@@ -384,10 +526,10 @@
384526 		}
385527 	}
386528 
529
+exit:
387530 	if (chip->runtime_pm)
388531 		pm_runtime_put(map->dev);
389532 
390
-exit:
391533 	if (chip->handle_post_irq)
392534 		chip->handle_post_irq(chip->irq_drv_data);
393535 
....@@ -417,8 +559,9 @@
417559 };
418560 
419561 /**
420
- * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
562
+ * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
421563  *
564
+ * @fwnode: The firmware node where the IRQ domain should be added to.
422565  * @map: The regmap for the device.
423566  * @irq: The IRQ the device uses to signal interrupts.
424567  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
....@@ -432,17 +575,23 @@
432575  * register cache.  The chip driver is responsible for restoring the
433576  * register values used by the IRQ controller over suspend and resume.
434577  */
435
-int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
436
-			int irq_base, const struct regmap_irq_chip *chip,
437
-			struct regmap_irq_chip_data **data)
578
+int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode,
579
+			       struct regmap *map, int irq,
580
+			       int irq_flags, int irq_base,
581
+			       const struct regmap_irq_chip *chip,
582
+			       struct regmap_irq_chip_data **data)
438583 {
439584 	struct regmap_irq_chip_data *d;
440585 	int i;
441586 	int ret = -ENOMEM;
587
+	int num_type_reg;
442588 	u32 reg;
443589 	u32 unmask_offset;
444590 
445591 	if (chip->num_regs <= 0)
592
+		return -EINVAL;
593
+
594
+	if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
446595 		return -EINVAL;
447596 
448597 	for (i = 0; i < chip->num_irqs; i++) {
....@@ -466,6 +615,15 @@
466615 	if (!d)
467616 		return -ENOMEM;
468617 
618
+	if (chip->num_main_regs) {
619
+		d->main_status_buf = kcalloc(chip->num_main_regs,
620
+					     sizeof(unsigned int),
621
+					     GFP_KERNEL);
622
+
623
+		if (!d->main_status_buf)
624
+			goto err_alloc;
625
+	}
626
+
469627 	d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
470628 				GFP_KERNEL);
471629 	if (!d->status_buf)
....@@ -488,13 +646,14 @@
488646 			goto err_alloc;
489647 	}
490648 
491
-	if (chip->num_type_reg) {
492
-		d->type_buf_def = kcalloc(chip->num_type_reg,
493
-					sizeof(unsigned int), GFP_KERNEL);
649
+	num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg;
650
+	if (num_type_reg) {
651
+		d->type_buf_def = kcalloc(num_type_reg,
652
+					  sizeof(unsigned int), GFP_KERNEL);
494653 		if (!d->type_buf_def)
495654 			goto err_alloc;
496655 
497
-		d->type_buf = kcalloc(chip->num_type_reg, sizeof(unsigned int),
656
+		d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int),
498657 				      GFP_KERNEL);
499658 		if (!d->type_buf)
500659 			goto err_alloc;
....@@ -581,9 +740,12 @@
581740 			else
582741 				ret = regmap_write(map, reg,
583742 					d->status_buf[i] & d->mask_buf[i]);
584
-			/* some chips needs to clear ack reg after ack */
585
-			if (chip->clear_ack)
586
-				ret = regmap_write(map, reg, 0x0);
743
+			if (chip->clear_ack) {
744
+				if (chip->ack_invert && !ret)
745
+					ret = regmap_write(map, reg, UINT_MAX);
746
+				else if (!ret)
747
+					ret = regmap_write(map, reg, 0);
748
+			}
587749 			if (ret != 0) {
588750 				dev_err(map->dev, "Failed to ack 0x%x: %d\n",
589751 					reg, ret);
....@@ -615,27 +777,18 @@
615777 		}
616778 	}
617779 
618
-	if (chip->num_type_reg) {
619
-		for (i = 0; i < chip->num_irqs; i++) {
620
-			reg = chip->irqs[i].type_reg_offset / map->reg_stride;
621
-			d->type_buf_def[reg] |= chip->irqs[i].type_rising_mask |
622
-					chip->irqs[i].type_falling_mask;
623
-		}
780
+	if (chip->num_type_reg && !chip->type_in_mask) {
624781 		for (i = 0; i < chip->num_type_reg; ++i) {
625
-			if (!d->type_buf_def[i])
626
-				continue;
627
-
628782 			reg = chip->type_base +
629783 				(i * map->reg_stride * d->type_reg_stride);
630
-			if (chip->type_invert)
631
-				ret = regmap_irq_update_bits(d, reg,
632
-					d->type_buf_def[i], 0xFF);
633
-			else
634
-				ret = regmap_irq_update_bits(d, reg,
635
-					d->type_buf_def[i], 0x0);
636
-			if (ret != 0) {
637
-				dev_err(map->dev,
638
-					"Failed to set type in 0x%x: %x\n",
784
+
785
+			ret = regmap_read(map, reg, &d->type_buf_def[i]);
786
+
787
+			if (d->chip->type_invert)
788
+				d->type_buf_def[i] = ~d->type_buf_def[i];
789
+
790
+			if (ret) {
791
+				dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n",
639792 					reg, ret);
640793 				goto err_alloc;
641794 			}
....@@ -643,11 +796,11 @@
643796 	}
644797 
645798 	if (irq_base)
646
-		d->domain = irq_domain_add_legacy(map->dev->of_node,
647
-						  chip->num_irqs, irq_base, 0,
648
-						  &regmap_domain_ops, d);
799
+		d->domain = irq_domain_add_legacy(to_of_node(fwnode),
800
+						  chip->num_irqs, irq_base,
801
+						  0, &regmap_domain_ops, d);
649802 	else
650
-		d->domain = irq_domain_add_linear(map->dev->of_node,
803
+		d->domain = irq_domain_add_linear(to_of_node(fwnode),
651804 						  chip->num_irqs,
652805 						  &regmap_domain_ops, d);
653806 	if (!d->domain) {
....@@ -681,6 +834,30 @@
681834 	kfree(d->status_reg_buf);
682835 	kfree(d);
683836 	return ret;
837
+}
838
+EXPORT_SYMBOL_GPL(regmap_add_irq_chip_fwnode);
839
+
840
+/**
841
+ * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
842
+ *
843
+ * @map: The regmap for the device.
844
+ * @irq: The IRQ the device uses to signal interrupts.
845
+ * @irq_flags: The IRQF_ flags to use for the primary interrupt.
846
+ * @irq_base: Allocate at specific IRQ number if irq_base > 0.
847
+ * @chip: Configuration for the interrupt controller.
848
+ * @data: Runtime data structure for the controller, allocated on success.
849
+ *
850
+ * Returns 0 on success or an errno on failure.
851
+ *
852
+ * This is the same as regmap_add_irq_chip_fwnode, except that the firmware
853
+ * node of the regmap is used.
854
+ */
855
+int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
856
+			int irq_base, const struct regmap_irq_chip *chip,
857
+			struct regmap_irq_chip_data **data)
858
+{
859
+	return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq,
860
+					  irq_flags, irq_base, chip, data);
684861 }
685862 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
686863 
....@@ -749,6 +926,52 @@
749926 }
750927 
751928 /**
929
+ * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
930
+ *
931
+ * @dev: The device pointer on which irq_chip belongs to.
932
+ * @fwnode: The firmware node where the IRQ domain should be added to.
933
+ * @map: The regmap for the device.
934
+ * @irq: The IRQ the device uses to signal interrupts
935
+ * @irq_flags: The IRQF_ flags to use for the primary interrupt.
936
+ * @irq_base: Allocate at specific IRQ number if irq_base > 0.
937
+ * @chip: Configuration for the interrupt controller.
938
+ * @data: Runtime data structure for the controller, allocated on success
939
+ *
940
+ * Returns 0 on success or an errno on failure.
941
+ *
942
+ * The &regmap_irq_chip_data will be automatically released when the device is
943
+ * unbound.
944
+ */
945
+int devm_regmap_add_irq_chip_fwnode(struct device *dev,
946
+				    struct fwnode_handle *fwnode,
947
+				    struct regmap *map, int irq,
948
+				    int irq_flags, int irq_base,
949
+				    const struct regmap_irq_chip *chip,
950
+				    struct regmap_irq_chip_data **data)
951
+{
952
+	struct regmap_irq_chip_data **ptr, *d;
953
+	int ret;
954
+
955
+	ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
956
+			   GFP_KERNEL);
957
+	if (!ptr)
958
+		return -ENOMEM;
959
+
960
+	ret = regmap_add_irq_chip_fwnode(fwnode, map, irq, irq_flags, irq_base,
961
+					 chip, &d);
962
+	if (ret < 0) {
963
+		devres_free(ptr);
964
+		return ret;
965
+	}
966
+
967
+	*ptr = d;
968
+	devres_add(dev, ptr);
969
+	*data = d;
970
+	return 0;
971
+}
972
+EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip_fwnode);
973
+
974
+/**
752975  * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
753976  *
754977  * @dev: The device pointer on which irq_chip belongs to.
....@@ -769,25 +992,9 @@
769992 			     const struct regmap_irq_chip *chip,
770993 			     struct regmap_irq_chip_data **data)
771994 {
772
-	struct regmap_irq_chip_data **ptr, *d;
773
-	int ret;
774
-
775
-	ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
776
-			   GFP_KERNEL);
777
-	if (!ptr)
778
-		return -ENOMEM;
779
-
780
-	ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base,
781
-				  chip, &d);
782
-	if (ret < 0) {
783
-		devres_free(ptr);
784
-		return ret;
785
-	}
786
-
787
-	*ptr = d;
788
-	devres_add(dev, ptr);
789
-	*data = d;
790
-	return 0;
995
+	return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map,
996
+					       irq, irq_flags, irq_base, chip,
997
+					       data);
791998 }
792999 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
7931000