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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/arch/x86/include/asm/cpufeatures.h
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@@ -96,7 +96,7 @@
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 #define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */
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 #define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */
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 #define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */
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-#define X86_FEATURE_MFENCE_RDTSC	( 3*32+17) /* "" MFENCE synchronizes RDTSC */
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+#define X86_FEATURE_SME_COHERENT	( 3*32+17) /* "" AMD hardware-enforced cache coherency */
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 #define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */
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 #define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */
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 #define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */
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@@ -108,6 +108,7 @@
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 #define X86_FEATURE_EXTD_APICID		( 3*32+26) /* Extended APICID (8 bits) */
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 #define X86_FEATURE_AMD_DCM		( 3*32+27) /* AMD multi-node processor */
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 #define X86_FEATURE_APERFMPERF		( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */
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+/* free					( 3*32+29) */
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 #define X86_FEATURE_NONSTOP_TSC_S3	( 3*32+30) /* TSC doesn't stop in S3 state */
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 #define X86_FEATURE_TSC_KNOWN_FREQ	( 3*32+31) /* TSC has known frequency */
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@@ -202,8 +203,8 @@
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 #define X86_FEATURE_PROC_FEEDBACK	( 7*32+ 9) /* AMD ProcFeedbackInterface */
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 #define X86_FEATURE_SME			( 7*32+10) /* AMD Secure Memory Encryption */
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 #define X86_FEATURE_PTI			( 7*32+11) /* Kernel Page Table Isolation enabled */
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-#define X86_FEATURE_RETPOLINE		( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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-#define X86_FEATURE_RETPOLINE_AMD	( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
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+#define X86_FEATURE_KERNEL_IBRS		( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */
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+#define X86_FEATURE_RSB_VMEXIT		( 7*32+13) /* "" Fill RSB on VM-Exit */
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 #define X86_FEATURE_INTEL_PPIN		( 7*32+14) /* Intel Processor Inventory Number */
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 #define X86_FEATURE_CDP_L2		( 7*32+15) /* Code and Data Prioritization L2 */
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 #define X86_FEATURE_MSR_SPEC_CTRL	( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
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@@ -218,9 +219,10 @@
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 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
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 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
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 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
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-#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
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+#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
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 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
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 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
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+#define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
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 /* Virtualization flags: Linux defined, word 8 */
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 #define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */
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@@ -232,6 +234,9 @@
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 #define X86_FEATURE_VMMCALL		( 8*32+15) /* Prefer VMMCALL to VMCALL */
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 #define X86_FEATURE_XENPV		( 8*32+16) /* "" Xen paravirtual guest */
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 #define X86_FEATURE_EPT_AD		( 8*32+17) /* Intel Extended Page Table access-dirty bit */
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+#define X86_FEATURE_VMCALL		( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
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+#define X86_FEATURE_VMW_VMMCALL		( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
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+#define X86_FEATURE_SEV_ES		( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */
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 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
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 #define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
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@@ -283,18 +288,38 @@
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 #define X86_FEATURE_CQM_MBM_LOCAL	(11*32+ 3) /* LLC Local MBM monitoring */
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 #define X86_FEATURE_FENCE_SWAPGS_USER	(11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
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 #define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
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+#define X86_FEATURE_SPLIT_LOCK_DETECT	(11*32+ 6) /* #AC for split lock */
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+#define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
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+/* FREE!				(11*32+ 8) */
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+/* FREE!				(11*32+ 9) */
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+#define X86_FEATURE_ENTRY_IBPB		(11*32+10) /* "" Issue an IBPB on kernel entry */
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+#define X86_FEATURE_RRSBA_CTRL		(11*32+11) /* "" RET prediction control */
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+#define X86_FEATURE_RETPOLINE		(11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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+#define X86_FEATURE_RETPOLINE_LFENCE	(11*32+13) /* "" Use LFENCE for Spectre variant 2 */
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+#define X86_FEATURE_RETHUNK		(11*32+14) /* "" Use REturn THUNK */
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+#define X86_FEATURE_UNRET		(11*32+15) /* "" AMD BTB untrain return */
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+#define X86_FEATURE_USE_IBPB_FW		(11*32+16) /* "" Use IBPB during runtime firmware calls */
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+#define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
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+#define X86_FEATURE_MSR_TSX_CTRL	(11*32+18) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
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+
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+/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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+#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
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 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
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 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
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 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
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 #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */
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+#define X86_FEATURE_RDPRU		(13*32+ 4) /* Read processor register at user level */
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+#define X86_FEATURE_WBNOINVD		(13*32+ 9) /* WBNOINVD instruction */
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 #define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */
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 #define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */
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 #define X86_FEATURE_AMD_STIBP		(13*32+15) /* "" Single Thread Indirect Branch Predictors */
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 #define X86_FEATURE_AMD_STIBP_ALWAYS_ON	(13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
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+#define X86_FEATURE_AMD_PPIN		(13*32+23) /* Protected Processor Inventory Number */
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 #define X86_FEATURE_AMD_SSBD		(13*32+24) /* "" Speculative Store Bypass Disable */
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 #define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */
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 #define X86_FEATURE_AMD_SSB_NO		(13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
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+#define X86_FEATURE_BTC_NO		(13*32+29) /* "" Not vulnerable to Branch Type Confusion */
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 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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 #define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */
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@@ -328,6 +353,7 @@
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 #define X86_FEATURE_UMIP		(16*32+ 2) /* User Mode Instruction Protection */
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 #define X86_FEATURE_PKU			(16*32+ 3) /* Protection Keys for Userspace */
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 #define X86_FEATURE_OSPKE		(16*32+ 4) /* OS Protection Keys Enable */
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+#define X86_FEATURE_WAITPKG		(16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
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 #define X86_FEATURE_AVX512_VBMI2	(16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
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 #define X86_FEATURE_GFNI		(16*32+ 8) /* Galois Field New Instructions */
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 #define X86_FEATURE_VAES		(16*32+ 9) /* Vector AES */
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@@ -339,6 +365,9 @@
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 #define X86_FEATURE_LA57		(16*32+16) /* 5-level page tables */
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 #define X86_FEATURE_RDPID		(16*32+22) /* RDPID instruction */
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 #define X86_FEATURE_CLDEMOTE		(16*32+25) /* CLDEMOTE instruction */
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+#define X86_FEATURE_MOVDIRI		(16*32+27) /* MOVDIRI instruction */
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+#define X86_FEATURE_MOVDIR64B		(16*32+28) /* MOVDIR64B instruction */
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+#define X86_FEATURE_ENQCMD		(16*32+29) /* ENQCMD and ENQCMDS instructions */
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 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
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 #define X86_FEATURE_OVERFLOW_RECOV	(17*32+ 0) /* MCA overflow recovery support */
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@@ -348,14 +377,20 @@
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 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
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 #define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */
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 #define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
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+#define X86_FEATURE_FSRM		(18*32+ 4) /* Fast Short Rep Mov */
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+#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
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 #define X86_FEATURE_SRBDS_CTRL		(18*32+ 9) /* "" SRBDS mitigation MSR available */
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-#define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
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 #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
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+#define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
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+#define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
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+#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */
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 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
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+#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
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 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
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 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
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 #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */
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 #define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
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+#define X86_FEATURE_CORE_CAPABILITIES	(18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
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 #define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */
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 /*
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 #define X86_BUG_TAA			X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
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 #define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
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 #define X86_BUG_SRBDS			X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
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+#define X86_BUG_MMIO_STALE_DATA		X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */
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+#define X86_BUG_MMIO_UNKNOWN		X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */
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+#define X86_BUG_RETBLEED		X86_BUG(27) /* CPU is affected by RETBleed */
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+#define X86_BUG_EIBRS_PBRSB		X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */
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 #endif /* _ASM_X86_CPUFEATURES_H */