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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/arch/powerpc/kernel/misc_64.S
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * This file contains miscellaneous low-level functions.
34  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
....@@ -6,12 +7,6 @@
67  * and Paul Mackerras.
78  * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
89  * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
9
- *
10
- * This program is free software; you can redistribute it and/or
11
- * modify it under the terms of the GNU General Public License
12
- * as published by the Free Software Foundation; either version
13
- * 2 of the License, or (at your option) any later version.
14
- *
1510  */
1611 
1712 #include <linux/sys.h>
....@@ -32,7 +27,7 @@
3227 
3328 	.text
3429 
35
-#ifndef CONFIG_PREEMPT_RT_FULL
30
+#ifndef CONFIG_PREEMPT_RT
3631 _GLOBAL(call_do_softirq)
3732 	mflr	r0
3833 	std	r0,16(r1)
....@@ -54,160 +49,6 @@
5449 	ld	r1,0(r1)
5550 	ld	r0,16(r1)
5651 	mtlr	r0
57
-	blr
58
-
59
-	.section	".toc","aw"
60
-PPC64_CACHES:
61
-	.tc		ppc64_caches[TC],ppc64_caches
62
-	.section	".text"
63
-
64
-/*
65
- * Write any modified data cache blocks out to memory
66
- * and invalidate the corresponding instruction cache blocks.
67
- *
68
- * flush_icache_range(unsigned long start, unsigned long stop)
69
- *
70
- *   flush all bytes from start through stop-1 inclusive
71
- */
72
-
73
-_GLOBAL_TOC(flush_icache_range)
74
-BEGIN_FTR_SECTION
75
-	PURGE_PREFETCHED_INS
76
-	blr
77
-END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
78
-/*
79
- * Flush the data cache to memory 
80
- * 
81
- * Different systems have different cache line sizes
82
- * and in some cases i-cache and d-cache line sizes differ from
83
- * each other.
84
- */
85
- 	ld	r10,PPC64_CACHES@toc(r2)
86
-	lwz	r7,DCACHEL1BLOCKSIZE(r10)/* Get cache block size */
87
-	addi	r5,r7,-1
88
-	andc	r6,r3,r5		/* round low to line bdy */
89
-	subf	r8,r6,r4		/* compute length */
90
-	add	r8,r8,r5		/* ensure we get enough */
91
-	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of cache block size */
92
-	srd.	r8,r8,r9		/* compute line count */
93
-	beqlr				/* nothing to do? */
94
-	mtctr	r8
95
-1:	dcbst	0,r6
96
-	add	r6,r6,r7
97
-	bdnz	1b
98
-	sync
99
-
100
-/* Now invalidate the instruction cache */
101
-	
102
-	lwz	r7,ICACHEL1BLOCKSIZE(r10)	/* Get Icache block size */
103
-	addi	r5,r7,-1
104
-	andc	r6,r3,r5		/* round low to line bdy */
105
-	subf	r8,r6,r4		/* compute length */
106
-	add	r8,r8,r5
107
-	lwz	r9,ICACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of Icache block size */
108
-	srd.	r8,r8,r9		/* compute line count */
109
-	beqlr				/* nothing to do? */
110
-	mtctr	r8
111
-2:	icbi	0,r6
112
-	add	r6,r6,r7
113
-	bdnz	2b
114
-	isync
115
-	blr
116
-_ASM_NOKPROBE_SYMBOL(flush_icache_range)
117
-EXPORT_SYMBOL(flush_icache_range)
118
-
119
-/*
120
- * Like above, but only do the D-cache.
121
- *
122
- * flush_dcache_range(unsigned long start, unsigned long stop)
123
- *
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- *    flush all bytes from start to stop-1 inclusive
125
- */
126
-_GLOBAL_TOC(flush_dcache_range)
127
-
128
-/*
129
- * Flush the data cache to memory 
130
- * 
131
- * Different systems have different cache line sizes
132
- */
133
- 	ld	r10,PPC64_CACHES@toc(r2)
134
-	lwz	r7,DCACHEL1BLOCKSIZE(r10)	/* Get dcache block size */
135
-	addi	r5,r7,-1
136
-	andc	r6,r3,r5		/* round low to line bdy */
137
-	subf	r8,r6,r4		/* compute length */
138
-	add	r8,r8,r5		/* ensure we get enough */
139
-	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of dcache block size */
140
-	srd.	r8,r8,r9		/* compute line count */
141
-	beqlr				/* nothing to do? */
142
-	mtctr	r8
143
-0:	dcbst	0,r6
144
-	add	r6,r6,r7
145
-	bdnz	0b
146
-	sync
147
-	blr
148
-EXPORT_SYMBOL(flush_dcache_range)
149
-
150
-_GLOBAL(flush_inval_dcache_range)
151
- 	ld	r10,PPC64_CACHES@toc(r2)
152
-	lwz	r7,DCACHEL1BLOCKSIZE(r10)	/* Get dcache block size */
153
-	addi	r5,r7,-1
154
-	andc	r6,r3,r5		/* round low to line bdy */
155
-	subf	r8,r6,r4		/* compute length */
156
-	add	r8,r8,r5		/* ensure we get enough */
157
-	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */
158
-	srd.	r8,r8,r9		/* compute line count */
159
-	beqlr				/* nothing to do? */
160
-	sync
161
-	isync
162
-	mtctr	r8
163
-0:	dcbf	0,r6
164
-	add	r6,r6,r7
165
-	bdnz	0b
166
-	sync
167
-	isync
168
-	blr
169
-
170
-
171
-/*
172
- * Flush a particular page from the data cache to RAM.
173
- * Note: this is necessary because the instruction cache does *not*
174
- * snoop from the data cache.
175
- *
176
- *	void __flush_dcache_icache(void *page)
177
- */
178
-_GLOBAL(__flush_dcache_icache)
179
-/*
180
- * Flush the data cache to memory 
181
- * 
182
- * Different systems have different cache line sizes
183
- */
184
-
185
-BEGIN_FTR_SECTION
186
-	PURGE_PREFETCHED_INS
187
-	blr
188
-END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
189
-
190
-/* Flush the dcache */
191
- 	ld	r7,PPC64_CACHES@toc(r2)
192
-	clrrdi	r3,r3,PAGE_SHIFT           	    /* Page align */
193
-	lwz	r4,DCACHEL1BLOCKSPERPAGE(r7)	/* Get # dcache blocks per page */
194
-	lwz	r5,DCACHEL1BLOCKSIZE(r7)	/* Get dcache block size */
195
-	mr	r6,r3
196
-	mtctr	r4
197
-0:	dcbst	0,r6
198
-	add	r6,r6,r5
199
-	bdnz	0b
200
-	sync
201
-
202
-/* Now invalidate the icache */	
203
-
204
-	lwz	r4,ICACHEL1BLOCKSPERPAGE(r7)	/* Get # icache blocks per page */
205
-	lwz	r5,ICACHEL1BLOCKSIZE(r7)	/* Get icache block size */
206
-	mtctr	r4
207
-1:	icbi	0,r3
208
-	add	r3,r3,r5
209
-	bdnz	1b
210
-	isync
21152 	blr
21253 
21354 _GLOBAL(__bswapdi2)
....@@ -491,18 +332,13 @@
491332 	rlwimi	r9,r10,16,4,15		/* Setup MAS0 = TLBSEL | ESEL(r9) */
492333 
493334 /* Set up a temp identity mapping v:0 to p:0 and return to it. */
494
-#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
495
-#define M_IF_NEEDED	MAS2_M
496
-#else
497
-#define M_IF_NEEDED	0
498
-#endif
499335 	mtspr	SPRN_MAS0,r9
500336 
501337 	lis	r9,(MAS1_VALID|MAS1_IPROT)@h
502338 	ori	r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
503339 	mtspr	SPRN_MAS1,r9
504340 
505
-	LOAD_REG_IMMEDIATE(r9, 0x0 | M_IF_NEEDED)
341
+	LOAD_REG_IMMEDIATE(r9, 0x0 | MAS2_M_IF_NEEDED)
506342 	mtspr	SPRN_MAS2,r9
507343 
508344 	LOAD_REG_IMMEDIATE(r9, 0x0 | MAS3_SR | MAS3_SW | MAS3_SX)
....@@ -531,7 +367,6 @@
531367 
532368 	li	r4,KEXEC_STATE_REAL_MODE
533369 	stb	r4,PACAKEXECSTATE(r13)
534
-	SYNC
535370 
536371 	b	kexec_wait
537372 
....@@ -578,20 +413,6 @@
578413 
579414 	li	r0,0
580415 	std	r0,16(r1)
581
-
582
-BEGIN_FTR_SECTION
583
-	/*
584
-	 * This is the best time to turn AMR/IAMR off.
585
-	 * key 0 is used in radix for supervisor<->user
586
-	 * protection, but on hash key 0 is reserved
587
-	 * ideally we want to enter with a clean state.
588
-	 * NOTE, we rely on r0 being 0 from above.
589
-	 */
590
-	mtspr	SPRN_IAMR,r0
591
-BEGIN_FTR_SECTION_NESTED(42)
592
-	mtspr	SPRN_AMOR,r0
593
-END_FTR_SECTION_NESTED_IFSET(CPU_FTR_HVMODE, 42)
594
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
595416 
596417 	/* save regs for local vars on new stack.
597418 	 * yes, we won't go back, but ...