.. | .. |
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81 | 81 | cpu0: PowerPC,e6500@0 { |
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82 | 82 | device_type = "cpu"; |
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83 | 83 | reg = <0 1>; |
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84 | | - clocks = <&mux0>; |
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| 84 | + clocks = <&clockgen 1 0>; |
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85 | 85 | next-level-cache = <&L2_1>; |
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86 | 86 | fsl,portid-mapping = <0x80000000>; |
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87 | 87 | }; |
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88 | 88 | cpu1: PowerPC,e6500@2 { |
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89 | 89 | device_type = "cpu"; |
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90 | 90 | reg = <2 3>; |
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91 | | - clocks = <&mux0>; |
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| 91 | + clocks = <&clockgen 1 0>; |
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92 | 92 | next-level-cache = <&L2_1>; |
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93 | 93 | fsl,portid-mapping = <0x80000000>; |
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94 | 94 | }; |
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95 | 95 | cpu2: PowerPC,e6500@4 { |
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96 | 96 | device_type = "cpu"; |
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97 | 97 | reg = <4 5>; |
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98 | | - clocks = <&mux0>; |
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| 98 | + clocks = <&clockgen 1 0>; |
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99 | 99 | next-level-cache = <&L2_1>; |
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100 | 100 | fsl,portid-mapping = <0x80000000>; |
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101 | 101 | }; |
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102 | 102 | cpu3: PowerPC,e6500@6 { |
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103 | 103 | device_type = "cpu"; |
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104 | 104 | reg = <6 7>; |
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105 | | - clocks = <&mux0>; |
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| 105 | + clocks = <&clockgen 1 0>; |
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106 | 106 | next-level-cache = <&L2_1>; |
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107 | 107 | fsl,portid-mapping = <0x80000000>; |
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108 | 108 | }; |
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