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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/arch/mips/mm/tlbex.c
..
..
@@ -28,11 +28,11 @@
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28
 #include <linux/smp.h>
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29
 #include <linux/string.h>
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30
 #include <linux/cache.h>
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+#include <linux/pgtable.h>
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32
 
32
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 #include <asm/cacheflush.h>
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 #include <asm/cpu-type.h>
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 #include <asm/mmu_context.h>
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-#include <asm/pgtable.h>
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 #include <asm/war.h>
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 #include <asm/uasm.h>
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 #include <asm/setup.h>
..
..
@@ -83,14 +83,18 @@
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 	return 0;
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 }
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85
 
86
+extern int sb1250_m3_workaround_needed(void);
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+
86
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 static inline int __maybe_unused bcm1250_m3_war(void)
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 {
88
-	return BCM1250_M3_WAR;
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+	if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
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+		return sb1250_m3_workaround_needed();
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+	return 0;
89
93
 }
90
94
 
91
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 static inline int __maybe_unused r10000_llsc_war(void)
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 {
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-	return R10000_LLSC_WAR;
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+	return IS_ENABLED(CONFIG_WAR_R10000_LLSC);
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98
 }
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99
 
96
100
 static int use_bbit_insns(void)
..
..
@@ -545,7 +549,6 @@
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549
 		tlbw(p);
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550
 		break;
547
551
 
548
-	case CPU_R4300:
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552
 	case CPU_5KC:
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553
 	case CPU_TX49XX:
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554
 	case CPU_PR4450:
..
..
@@ -572,11 +575,12 @@
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 	case CPU_BMIPS4350:
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576
 	case CPU_BMIPS4380:
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577
 	case CPU_BMIPS5000:
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-	case CPU_LOONGSON2:
576
-	case CPU_LOONGSON3:
578
+	case CPU_LOONGSON2EF:
579
+	case CPU_LOONGSON64:
577
580
 	case CPU_R5500:
578
581
 		if (m4kc_tlbp_war())
579
582
 			uasm_i_nop(p);
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+		fallthrough;
580
584
 	case CPU_ALCHEMY:
581
585
 		tlbw(p);
582
586
 		break;
..
..
@@ -603,13 +607,12 @@
603
607
 
604
608
 	case CPU_VR4131:
605
609
 	case CPU_VR4133:
606
-	case CPU_R5432:
607
610
 		uasm_i_nop(p);
608
611
 		uasm_i_nop(p);
609
612
 		tlbw(p);
610
613
 		break;
611
614
 
612
-	case CPU_JZRISC:
615
+	case CPU_XBURST:
613
616
 		tlbw(p);
614
617
 		uasm_i_nop(p);
615
618
 		break;
..
..
@@ -630,7 +633,7 @@
630
633
 		return;
631
634
 	}
632
635
 
633
-	if (cpu_has_rixi && !!_PAGE_NO_EXEC) {
636
+	if (cpu_has_rixi && _PAGE_NO_EXEC != 0) {
634
637
 		if (fill_includes_sw_bits) {
635
638
 			UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
636
639
 		} else {
..
..
@@ -943,6 +946,8 @@
943
946
 		 * to mimic that here by taking a load/istream page
944
947
 		 * fault.
945
948
 		 */
949
+		if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
950
+			uasm_i_sync(p, 0);
946
951
 		UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
947
952
 		uasm_i_jr(p, ptr);
948
953
 
..
..
@@ -1376,7 +1381,7 @@
1376
1381
 	switch (boot_cpu_type()) {
1377
1382
 	default:
1378
1383
 		if (sizeof(long) == 4) {
1379
-	case CPU_LOONGSON2:
1384
+	case CPU_LOONGSON2EF:
1380
1385
 		/* Loongson2 ebase is different than r4k, we have more space */
1381
1386
 			if ((p - tlb_handler) > 64)
1382
1387
 				panic("TLB refill handler space exceeded");
..
..
@@ -1666,6 +1671,8 @@
1666
1671
 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1667
1672
 {
1668
1673
 #ifdef CONFIG_SMP
1674
+	if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
1675
+		uasm_i_sync(p, 0);
1669
1676
 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1670
1677
 	if (cpu_has_64bits)
1671
1678
 		uasm_i_lld(p, pte, 0, ptr);
..
..
@@ -2279,6 +2286,8 @@
2279
2286
 #endif
2280
2287
 
2281
2288
 	uasm_l_nopage_tlbl(&l, p);
2289
+	if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
2290
+		uasm_i_sync(&p, 0);
2282
2291
 	build_restore_work_registers(&p);
2283
2292
 #ifdef CONFIG_CPU_MICROMIPS
2284
2293
 	if ((unsigned long)tlb_do_page_fault_0 & 1) {
..
..
@@ -2333,6 +2342,8 @@
2333
2342
 #endif
2334
2343
 
2335
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 	uasm_l_nopage_tlbs(&l, p);
2345
+	if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
2346
+		uasm_i_sync(&p, 0);
2336
2347
 	build_restore_work_registers(&p);
2337
2348
 #ifdef CONFIG_CPU_MICROMIPS
2338
2349
 	if ((unsigned long)tlb_do_page_fault_1 & 1) {
..
..
@@ -2388,6 +2399,8 @@
2388
2399
 #endif
2389
2400
 
2390
2401
 	uasm_l_nopage_tlbm(&l, p);
2402
+	if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
2403
+		uasm_i_sync(&p, 0);
2391
2404
 	build_restore_work_registers(&p);
2392
2405
 #ifdef CONFIG_CPU_MICROMIPS
2393
2406
 	if ((unsigned long)tlb_do_page_fault_1 & 1) {
..
..
@@ -2559,7 +2572,7 @@
2559
2572
 	unsigned long entry;
2560
2573
 	unsigned pabits, fillbits;
2561
2574
 
2562
-	if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
2575
+	if (!cpu_has_rixi || _PAGE_NO_EXEC == 0) {
2563
2576
 		/*
2564
2577
 		 * We'll only be making use of the fact that we can rotate bits
2565
2578
 		 * into the fill if the CPU supports RIXI, so don't bother
..
..
@@ -2608,21 +2621,11 @@
2608
2621
 	check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2609
2622
 #endif
2610
2623
 
2611
-	switch (current_cpu_type()) {
2612
-	case CPU_R2000:
2613
-	case CPU_R3000:
2614
-	case CPU_R3000A:
2615
-	case CPU_R3081E:
2616
-	case CPU_TX3912:
2617
-	case CPU_TX3922:
2618
-	case CPU_TX3927:
2624
+	if (cpu_has_3kex) {
2619
2625
 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2620
-		if (cpu_has_local_ebase)
2621
-			build_r3000_tlb_refill_handler();
2622
2626
 		if (!run_once) {
2623
-			if (!cpu_has_local_ebase)
2624
-				build_r3000_tlb_refill_handler();
2625
2627
 			build_setup_pgd();
2628
+			build_r3000_tlb_refill_handler();
2626
2629
 			build_r3000_tlb_load_handler();
2627
2630
 			build_r3000_tlb_store_handler();
2628
2631
 			build_r3000_tlb_modify_handler();
..
..
@@ -2632,34 +2635,27 @@
2632
2635
 #else
2633
2636
 		panic("No R3000 TLB refill handler");
2634
2637
 #endif
2635
-		break;
2636
-
2637
-	case CPU_R8000:
2638
-		panic("No R8000 TLB refill handler yet");
2639
-		break;
2640
-
2641
-	default:
2642
-		if (cpu_has_ldpte)
2643
-			setup_pw();
2644
-
2645
-		if (!run_once) {
2646
-			scratch_reg = allocate_kscratch();
2647
-			build_setup_pgd();
2648
-			build_r4000_tlb_load_handler();
2649
-			build_r4000_tlb_store_handler();
2650
-			build_r4000_tlb_modify_handler();
2651
-			if (cpu_has_ldpte)
2652
-				build_loongson3_tlb_refill_handler();
2653
-			else if (!cpu_has_local_ebase)
2654
-				build_r4000_tlb_refill_handler();
2655
-			flush_tlb_handlers();
2656
-			run_once++;
2657
-		}
2658
-		if (cpu_has_local_ebase)
2659
-			build_r4000_tlb_refill_handler();
2660
-		if (cpu_has_xpa)
2661
-			config_xpa_params();
2662
-		if (cpu_has_htw)
2663
-			config_htw_params();
2638
+		return;
2664
2639
 	}
2640
+
2641
+	if (cpu_has_ldpte)
2642
+		setup_pw();
2643
+
2644
+	if (!run_once) {
2645
+		scratch_reg = allocate_kscratch();
2646
+		build_setup_pgd();
2647
+		build_r4000_tlb_load_handler();
2648
+		build_r4000_tlb_store_handler();
2649
+		build_r4000_tlb_modify_handler();
2650
+		if (cpu_has_ldpte)
2651
+			build_loongson3_tlb_refill_handler();
2652
+		else
2653
+			build_r4000_tlb_refill_handler();
2654
+		flush_tlb_handlers();
2655
+		run_once++;
2656
+	}
2657
+	if (cpu_has_xpa)
2658
+		config_xpa_params();
2659
+	if (cpu_has_htw)
2660
+		config_htw_params();
2665
2661
 }