移去rt

hc

2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/arch/mips/mm/c-tx39.c
..
..
@@ -17,7 +17,6 @@
17
17
 
18
18
 #include <asm/cacheops.h>
19
19
 #include <asm/page.h>
20
-#include <asm/pgtable.h>
21
20
 #include <asm/mmu_context.h>
22
21
 #include <asm/isadep.h>
23
22
 #include <asm/io.h>
..
..
@@ -169,8 +168,6 @@
169
168
 {
170
169
 	int exec = vma->vm_flags & VM_EXEC;
171
170
 	struct mm_struct *mm = vma->vm_mm;
172
-	pgd_t *pgdp;
173
-	pud_t *pudp;
174
171
 	pmd_t *pmdp;
175
172
 	pte_t *ptep;
176
173
 
..
..
@@ -182,10 +179,8 @@
182
179
 		return;
183
180
 
184
181
 	page &= PAGE_MASK;
185
-	pgdp = pgd_offset(mm, page);
186
-	pudp = pud_offset(pgdp, page);
187
-	pmdp = pmd_offset(pudp, page);
188
-	ptep = pte_offset(pmdp, page);
182
+	pmdp = pmd_off(mm, page);
183
+	ptep = pte_offset_kernel(pmdp, page);
189
184
 
190
185
 	/*
191
186
 	 * If the page isn't marked valid, the page cannot possibly be
..
..
@@ -290,25 +285,6 @@
290
285
 	}
291
286
 }
292
287
 
293
-static void tx39_flush_cache_sigtramp(unsigned long addr)
294
-{
295
-	unsigned long ic_lsize = current_cpu_data.icache.linesz;
296
-	unsigned long dc_lsize = current_cpu_data.dcache.linesz;
297
-	unsigned long config;
298
-	unsigned long flags;
299
-
300
-	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
301
-
302
-	/* disable icache (set ICE#) */
303
-	local_irq_save(flags);
304
-	config = read_c0_conf();
305
-	write_c0_conf(config & ~TX39_CONF_ICE);
306
-	TX39_STOP_STREAMING();
307
-	protected_flush_icache_line(addr & ~(ic_lsize - 1));
308
-	write_c0_conf(config);
309
-	local_irq_restore(flags);
310
-}
311
-
312
288
 static __init void tx39_probe_cache(void)
313
289
 {
314
290
 	unsigned long config;
..
..
@@ -368,7 +344,6 @@
368
344
 		flush_icache_range	= (void *) tx39h_flush_icache_all;
369
345
 		local_flush_icache_range = (void *) tx39h_flush_icache_all;
370
346
 
371
-		flush_cache_sigtramp	= (void *) tx39h_flush_icache_all;
372
347
 		local_flush_data_cache_page	= (void *) tx39h_flush_icache_all;
373
348
 		flush_data_cache_page	= (void *) tx39h_flush_icache_all;
374
349
 
..
..
@@ -397,7 +372,6 @@
397
372
 
398
373
 		__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
399
374
 
400
-		flush_cache_sigtramp = tx39_flush_cache_sigtramp;
401
375
 		local_flush_data_cache_page = local_tx39_flush_data_cache_page;
402
376
 		flush_data_cache_page = tx39_flush_data_cache_page;
403
377
 
..
..
@@ -429,9 +403,9 @@
429
403
 	current_cpu_data.icache.waybit = 0;
430
404
 	current_cpu_data.dcache.waybit = 0;
431
405
 
432
-	printk("Primary instruction cache %ldkB, linesize %d bytes\n",
406
+	pr_info("Primary instruction cache %ldkB, linesize %d bytes\n",
433
407
 		icache_size >> 10, current_cpu_data.icache.linesz);
434
-	printk("Primary data cache %ldkB, linesize %d bytes\n",
408
+	pr_info("Primary data cache %ldkB, linesize %d bytes\n",
435
409
 		dcache_size >> 10, current_cpu_data.dcache.linesz);
436
410
 
437
411
 	build_clear_page();