forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/arch/arm64/include/asm/sysreg.h
....@@ -1,27 +1,17 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Macros for accessing system registers with older binutils.
34  *
45  * Copyright (C) 2014 ARM Ltd.
56  * Author: Catalin Marinas <catalin.marinas@arm.com>
6
- *
7
- * This program is free software: you can redistribute it and/or modify
8
- * it under the terms of the GNU General Public License version 2 as
9
- * published by the Free Software Foundation.
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
- * GNU General Public License for more details.
15
- *
16
- * You should have received a copy of the GNU General Public License
17
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
187  */
198 
209 #ifndef __ASM_SYSREG_H
2110 #define __ASM_SYSREG_H
2211 
23
-#include <asm/compiler.h>
12
+#include <linux/bits.h>
2413 #include <linux/stringify.h>
14
+#include <linux/kasan-tags.h>
2515 
2616 /*
2717  * ARMv8 ARM reserves the following encoding for system registers:
....@@ -102,15 +92,30 @@
10292 #define PSTATE_PAN			pstate_field(0, 4)
10393 #define PSTATE_UAO			pstate_field(0, 3)
10494 #define PSTATE_SSBS			pstate_field(3, 1)
95
+#define PSTATE_TCO			pstate_field(3, 4)
10596 
10697 #define SET_PSTATE_PAN(x)		__emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
10798 #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
10899 #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
100
+#define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
101
+
102
+#define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
103
+#define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
104
+#define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
105
+
106
+#define __SYS_BARRIER_INSN(CRm, op2, Rt) \
107
+	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
108
+
109
+#define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
109110 
110111 #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
111112 #define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
112113 #define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
113114 
115
+/*
116
+ * System registers, organised loosely by encoding but grouped together
117
+ * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
118
+ */
114119 #define SYS_OSDTRRX_EL1			sys_reg(2, 0, 0, 0, 2)
115120 #define SYS_MDCCINT_EL1			sys_reg(2, 0, 0, 2, 0)
116121 #define SYS_MDSCR_EL1			sys_reg(2, 0, 0, 2, 2)
....@@ -140,12 +145,16 @@
140145 
141146 #define SYS_ID_PFR0_EL1			sys_reg(3, 0, 0, 1, 0)
142147 #define SYS_ID_PFR1_EL1			sys_reg(3, 0, 0, 1, 1)
148
+#define SYS_ID_PFR2_EL1			sys_reg(3, 0, 0, 3, 4)
143149 #define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)
150
+#define SYS_ID_DFR1_EL1			sys_reg(3, 0, 0, 3, 5)
144151 #define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)
145152 #define SYS_ID_MMFR0_EL1		sys_reg(3, 0, 0, 1, 4)
146153 #define SYS_ID_MMFR1_EL1		sys_reg(3, 0, 0, 1, 5)
147154 #define SYS_ID_MMFR2_EL1		sys_reg(3, 0, 0, 1, 6)
148155 #define SYS_ID_MMFR3_EL1		sys_reg(3, 0, 0, 1, 7)
156
+#define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)
157
+#define SYS_ID_MMFR5_EL1		sys_reg(3, 0, 0, 3, 6)
149158 
150159 #define SYS_ID_ISAR0_EL1		sys_reg(3, 0, 0, 2, 0)
151160 #define SYS_ID_ISAR1_EL1		sys_reg(3, 0, 0, 2, 1)
....@@ -153,7 +162,7 @@
153162 #define SYS_ID_ISAR3_EL1		sys_reg(3, 0, 0, 2, 3)
154163 #define SYS_ID_ISAR4_EL1		sys_reg(3, 0, 0, 2, 4)
155164 #define SYS_ID_ISAR5_EL1		sys_reg(3, 0, 0, 2, 5)
156
-#define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)
165
+#define SYS_ID_ISAR6_EL1		sys_reg(3, 0, 0, 2, 7)
157166 
158167 #define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
159168 #define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
....@@ -171,6 +180,7 @@
171180 
172181 #define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
173182 #define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
183
+#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)
174184 
175185 #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
176186 #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
....@@ -179,12 +189,31 @@
179189 #define SYS_SCTLR_EL1			sys_reg(3, 0, 1, 0, 0)
180190 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
181191 #define SYS_CPACR_EL1			sys_reg(3, 0, 1, 0, 2)
192
+#define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
193
+#define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
182194 
183195 #define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
196
+#define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
184197 
185198 #define SYS_TTBR0_EL1			sys_reg(3, 0, 2, 0, 0)
186199 #define SYS_TTBR1_EL1			sys_reg(3, 0, 2, 0, 1)
187200 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
201
+
202
+#define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
203
+#define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
204
+#define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
205
+#define SYS_APIBKEYHI_EL1		sys_reg(3, 0, 2, 1, 3)
206
+
207
+#define SYS_APDAKEYLO_EL1		sys_reg(3, 0, 2, 2, 0)
208
+#define SYS_APDAKEYHI_EL1		sys_reg(3, 0, 2, 2, 1)
209
+#define SYS_APDBKEYLO_EL1		sys_reg(3, 0, 2, 2, 2)
210
+#define SYS_APDBKEYHI_EL1		sys_reg(3, 0, 2, 2, 3)
211
+
212
+#define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
213
+#define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
214
+
215
+#define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
216
+#define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
188217 
189218 #define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
190219 
....@@ -200,9 +229,14 @@
200229 #define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)
201230 #define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)
202231 #define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)
232
+#define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)
233
+#define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)
203234 
204235 #define SYS_FAR_EL1			sys_reg(3, 0, 6, 0, 0)
205236 #define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
237
+
238
+#define SYS_PAR_EL1_F			BIT(0)
239
+#define SYS_PAR_EL1_FST			GENMASK(6, 1)
206240 
207241 /*** Statistical Profiling Extension ***/
208242 /* ID registers */
....@@ -297,8 +331,59 @@
297331 
298332 /*** End of Statistical Profiling Extension ***/
299333 
334
+/*
335
+ * TRBE Registers
336
+ */
337
+#define SYS_TRBLIMITR_EL1		sys_reg(3, 0, 9, 11, 0)
338
+#define SYS_TRBPTR_EL1			sys_reg(3, 0, 9, 11, 1)
339
+#define SYS_TRBBASER_EL1		sys_reg(3, 0, 9, 11, 2)
340
+#define SYS_TRBSR_EL1			sys_reg(3, 0, 9, 11, 3)
341
+#define SYS_TRBMAR_EL1			sys_reg(3, 0, 9, 11, 4)
342
+#define SYS_TRBTRG_EL1			sys_reg(3, 0, 9, 11, 6)
343
+#define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)
344
+
345
+#define TRBLIMITR_LIMIT_MASK		GENMASK_ULL(51, 0)
346
+#define TRBLIMITR_LIMIT_SHIFT		12
347
+#define TRBLIMITR_NVM			BIT(5)
348
+#define TRBLIMITR_TRIG_MODE_MASK	GENMASK(1, 0)
349
+#define TRBLIMITR_TRIG_MODE_SHIFT	3
350
+#define TRBLIMITR_FILL_MODE_MASK	GENMASK(1, 0)
351
+#define TRBLIMITR_FILL_MODE_SHIFT	1
352
+#define TRBLIMITR_ENABLE		BIT(0)
353
+#define TRBPTR_PTR_MASK			GENMASK_ULL(63, 0)
354
+#define TRBPTR_PTR_SHIFT		0
355
+#define TRBBASER_BASE_MASK		GENMASK_ULL(51, 0)
356
+#define TRBBASER_BASE_SHIFT		12
357
+#define TRBSR_EC_MASK			GENMASK(5, 0)
358
+#define TRBSR_EC_SHIFT			26
359
+#define TRBSR_IRQ			BIT(22)
360
+#define TRBSR_TRG			BIT(21)
361
+#define TRBSR_WRAP			BIT(20)
362
+#define TRBSR_ABORT			BIT(18)
363
+#define TRBSR_STOP			BIT(17)
364
+#define TRBSR_MSS_MASK			GENMASK(15, 0)
365
+#define TRBSR_MSS_SHIFT			0
366
+#define TRBSR_BSC_MASK			GENMASK(5, 0)
367
+#define TRBSR_BSC_SHIFT			0
368
+#define TRBSR_FSC_MASK			GENMASK(5, 0)
369
+#define TRBSR_FSC_SHIFT			0
370
+#define TRBMAR_SHARE_MASK		GENMASK(1, 0)
371
+#define TRBMAR_SHARE_SHIFT		8
372
+#define TRBMAR_OUTER_MASK		GENMASK(3, 0)
373
+#define TRBMAR_OUTER_SHIFT		4
374
+#define TRBMAR_INNER_MASK		GENMASK(3, 0)
375
+#define TRBMAR_INNER_SHIFT		0
376
+#define TRBTRG_TRG_MASK			GENMASK(31, 0)
377
+#define TRBTRG_TRG_SHIFT		0
378
+#define TRBIDR_FLAG			BIT(5)
379
+#define TRBIDR_PROG			BIT(4)
380
+#define TRBIDR_ALIGN_MASK		GENMASK(3, 0)
381
+#define TRBIDR_ALIGN_SHIFT		0
382
+
300383 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
301384 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
385
+
386
+#define SYS_PMMIR_EL1			sys_reg(3, 0, 9, 14, 6)
302387 
303388 #define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
304389 #define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
....@@ -343,15 +428,22 @@
343428 #define SYS_CONTEXTIDR_EL1		sys_reg(3, 0, 13, 0, 1)
344429 #define SYS_TPIDR_EL1			sys_reg(3, 0, 13, 0, 4)
345430 
431
+#define SYS_SCXTNUM_EL1			sys_reg(3, 0, 13, 0, 7)
432
+
346433 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
347434 
435
+#define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)
348436 #define SYS_CLIDR_EL1			sys_reg(3, 1, 0, 0, 1)
437
+#define SYS_GMID_EL1			sys_reg(3, 1, 0, 0, 4)
349438 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
350439 
351440 #define SYS_CSSELR_EL1			sys_reg(3, 2, 0, 0, 0)
352441 
353442 #define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
354443 #define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)
444
+
445
+#define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
446
+#define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
355447 
356448 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
357449 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
....@@ -370,11 +462,56 @@
370462 #define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
371463 #define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
372464 
465
+#define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
466
+
467
+/* Definitions for system register interface to AMU for ARMv8.4 onwards */
468
+#define SYS_AM_EL0(crm, op2)		sys_reg(3, 3, 13, (crm), (op2))
469
+#define SYS_AMCR_EL0			SYS_AM_EL0(2, 0)
470
+#define SYS_AMCFGR_EL0			SYS_AM_EL0(2, 1)
471
+#define SYS_AMCGCR_EL0			SYS_AM_EL0(2, 2)
472
+#define SYS_AMUSERENR_EL0		SYS_AM_EL0(2, 3)
473
+#define SYS_AMCNTENCLR0_EL0		SYS_AM_EL0(2, 4)
474
+#define SYS_AMCNTENSET0_EL0		SYS_AM_EL0(2, 5)
475
+#define SYS_AMCNTENCLR1_EL0		SYS_AM_EL0(3, 0)
476
+#define SYS_AMCNTENSET1_EL0		SYS_AM_EL0(3, 1)
477
+
478
+/*
479
+ * Group 0 of activity monitors (architected):
480
+ *                op0  op1  CRn   CRm       op2
481
+ * Counter:       11   011  1101  010:n<3>  n<2:0>
482
+ * Type:          11   011  1101  011:n<3>  n<2:0>
483
+ * n: 0-15
484
+ *
485
+ * Group 1 of activity monitors (auxiliary):
486
+ *                op0  op1  CRn   CRm       op2
487
+ * Counter:       11   011  1101  110:n<3>  n<2:0>
488
+ * Type:          11   011  1101  111:n<3>  n<2:0>
489
+ * n: 0-15
490
+ */
491
+
492
+#define SYS_AMEVCNTR0_EL0(n)		SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
493
+#define SYS_AMEVTYPER0_EL0(n)		SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
494
+#define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
495
+#define SYS_AMEVTYPER1_EL0(n)		SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
496
+
497
+/* AMU v1: Fixed (architecturally defined) activity monitors */
498
+#define SYS_AMEVCNTR0_CORE_EL0		SYS_AMEVCNTR0_EL0(0)
499
+#define SYS_AMEVCNTR0_CONST_EL0		SYS_AMEVCNTR0_EL0(1)
500
+#define SYS_AMEVCNTR0_INST_RET_EL0	SYS_AMEVCNTR0_EL0(2)
501
+#define SYS_AMEVCNTR0_MEM_STALL		SYS_AMEVCNTR0_EL0(3)
502
+
373503 #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
374504 
375505 #define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
376506 #define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
377507 #define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
508
+
509
+#define SYS_CNTV_CTL_EL0		sys_reg(3, 3, 14, 3, 1)
510
+#define SYS_CNTV_CVAL_EL0		sys_reg(3, 3, 14, 3, 2)
511
+
512
+#define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
513
+#define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
514
+#define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
378515 
379516 #define __PMEV_op2(n)			((n) & 0x7)
380517 #define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
....@@ -382,14 +519,20 @@
382519 #define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
383520 #define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
384521 
385
-#define SYS_PMCCFILTR_EL0		sys_reg (3, 3, 14, 15, 7)
522
+#define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
386523 
524
+#define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
387525 #define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)
388
-
526
+#define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
389527 #define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
528
+#define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
529
+#define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
390530 #define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
531
+#define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
391532 #define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
392533 #define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
534
+#define SYS_TFSR_EL2			sys_reg(3, 4, 5, 6, 0)
535
+#define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
393536 
394537 #define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1,  1)
395538 #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
....@@ -410,7 +553,7 @@
410553 #define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
411554 #define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
412555 #define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
413
-#define SYS_ICH_ELSR_EL2		sys_reg(3, 4, 12, 11, 5)
556
+#define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
414557 #define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
415558 
416559 #define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
....@@ -433,90 +576,135 @@
433576 #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
434577 #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
435578 
436
-/* Common SCTLR_ELx flags. */
437
-#define SCTLR_ELx_DSSBS	(1UL << 44)
438
-#define SCTLR_ELx_EE    (1 << 25)
439
-#define SCTLR_ELx_IESB	(1 << 21)
440
-#define SCTLR_ELx_WXN	(1 << 19)
441
-#define SCTLR_ELx_I	(1 << 12)
442
-#define SCTLR_ELx_SA	(1 << 3)
443
-#define SCTLR_ELx_C	(1 << 2)
444
-#define SCTLR_ELx_A	(1 << 1)
445
-#define SCTLR_ELx_M	1
579
+/* VHE encodings for architectural EL0/1 system registers */
580
+#define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
581
+#define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
582
+#define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
583
+#define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
584
+#define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
585
+#define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
586
+#define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
587
+#define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
588
+#define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
589
+#define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
590
+#define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
591
+#define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)
592
+#define SYS_FAR_EL12			sys_reg(3, 5, 6, 0, 0)
593
+#define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
594
+#define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
595
+#define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
596
+#define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)
597
+#define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
598
+#define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
599
+#define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
600
+#define SYS_CNTP_CVAL_EL02		sys_reg(3, 5, 14, 2, 2)
601
+#define SYS_CNTV_TVAL_EL02		sys_reg(3, 5, 14, 3, 0)
602
+#define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
603
+#define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
446604 
447
-#define SCTLR_ELx_FLAGS	(SCTLR_ELx_M  | SCTLR_ELx_A | SCTLR_ELx_C | \
448
-			 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB)
605
+/* Common SCTLR_ELx flags. */
606
+#define SCTLR_ELx_DSSBS	(BIT(44))
607
+#define SCTLR_ELx_ATA	(BIT(43))
608
+
609
+#define SCTLR_ELx_TCF_SHIFT	40
610
+#define SCTLR_ELx_TCF_NONE	(UL(0x0) << SCTLR_ELx_TCF_SHIFT)
611
+#define SCTLR_ELx_TCF_SYNC	(UL(0x1) << SCTLR_ELx_TCF_SHIFT)
612
+#define SCTLR_ELx_TCF_ASYNC	(UL(0x2) << SCTLR_ELx_TCF_SHIFT)
613
+#define SCTLR_ELx_TCF_MASK	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)
614
+
615
+#define SCTLR_ELx_ENIA_SHIFT	31
616
+
617
+#define SCTLR_ELx_ITFSB	(BIT(37))
618
+#define SCTLR_ELx_ENIA	(BIT(SCTLR_ELx_ENIA_SHIFT))
619
+#define SCTLR_ELx_ENIB	(BIT(30))
620
+#define SCTLR_ELx_ENDA	(BIT(27))
621
+#define SCTLR_ELx_EE    (BIT(25))
622
+#define SCTLR_ELx_IESB	(BIT(21))
623
+#define SCTLR_ELx_WXN	(BIT(19))
624
+#define SCTLR_ELx_ENDB	(BIT(13))
625
+#define SCTLR_ELx_I	(BIT(12))
626
+#define SCTLR_ELx_SA	(BIT(3))
627
+#define SCTLR_ELx_C	(BIT(2))
628
+#define SCTLR_ELx_A	(BIT(1))
629
+#define SCTLR_ELx_M	(BIT(0))
449630 
450631 /* SCTLR_EL2 specific flags. */
451
-#define SCTLR_EL2_RES1	((1 << 4)  | (1 << 5)  | (1 << 11) | (1 << 16) | \
452
-			 (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \
453
-			 (1 << 29))
454
-#define SCTLR_EL2_RES0	((1 << 6)  | (1 << 7)  | (1 << 8)  | (1 << 9)  | \
455
-			 (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \
456
-			 (1 << 17) | (1 << 20) | (1 << 24) | (1 << 26) | \
457
-			 (1 << 27) | (1 << 30) | (1 << 31) | \
458
-			 (0xffffefffUL << 32))
632
+#define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
633
+			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
634
+			 (BIT(29)))
459635 
460636 #ifdef CONFIG_CPU_BIG_ENDIAN
461637 #define ENDIAN_SET_EL2		SCTLR_ELx_EE
462
-#define ENDIAN_CLEAR_EL2	0
463638 #else
464639 #define ENDIAN_SET_EL2		0
465
-#define ENDIAN_CLEAR_EL2	SCTLR_ELx_EE
466640 #endif
467641 
468
-/* SCTLR_EL2 value used for the hyp-stub */
469
-#define SCTLR_EL2_SET	(SCTLR_ELx_IESB   | ENDIAN_SET_EL2   | SCTLR_EL2_RES1)
470
-#define SCTLR_EL2_CLEAR	(SCTLR_ELx_M      | SCTLR_ELx_A    | SCTLR_ELx_C   | \
471
-			 SCTLR_ELx_SA     | SCTLR_ELx_I    | SCTLR_ELx_WXN | \
472
-			 SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
642
+#define INIT_SCTLR_EL2_MMU_ON						\
643
+	(SCTLR_ELx_M  | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I |	\
644
+	 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | SCTLR_EL2_RES1)
473645 
474
-#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffff
475
-#error "Inconsistent SCTLR_EL2 set/clear bits"
476
-#endif
646
+#define INIT_SCTLR_EL2_MMU_OFF \
647
+	(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
477648 
478649 /* SCTLR_EL1 specific flags. */
479
-#define SCTLR_EL1_UCI		(1 << 26)
480
-#define SCTLR_EL1_E0E		(1 << 24)
481
-#define SCTLR_EL1_SPAN		(1 << 23)
482
-#define SCTLR_EL1_NTWE		(1 << 18)
483
-#define SCTLR_EL1_NTWI		(1 << 16)
484
-#define SCTLR_EL1_UCT		(1 << 15)
485
-#define SCTLR_EL1_DZE		(1 << 14)
486
-#define SCTLR_EL1_UMA		(1 << 9)
487
-#define SCTLR_EL1_SED		(1 << 8)
488
-#define SCTLR_EL1_ITD		(1 << 7)
489
-#define SCTLR_EL1_CP15BEN	(1 << 5)
490
-#define SCTLR_EL1_SA0		(1 << 4)
650
+#define SCTLR_EL1_ATA0		(BIT(42))
491651 
492
-#define SCTLR_EL1_RES1	((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \
493
-			 (1 << 29))
494
-#define SCTLR_EL1_RES0  ((1 << 6)  | (1 << 10) | (1 << 13) | (1 << 17) | \
495
-			 (1 << 27) | (1 << 30) | (1 << 31) | \
496
-			 (0xffffefffUL << 32))
652
+#define SCTLR_EL1_TCF0_SHIFT	38
653
+#define SCTLR_EL1_TCF0_NONE	(UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
654
+#define SCTLR_EL1_TCF0_SYNC	(UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
655
+#define SCTLR_EL1_TCF0_ASYNC	(UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
656
+#define SCTLR_EL1_TCF0_MASK	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
657
+
658
+#define SCTLR_EL1_BT1		(BIT(36))
659
+#define SCTLR_EL1_BT0		(BIT(35))
660
+#define SCTLR_EL1_UCI		(BIT(26))
661
+#define SCTLR_EL1_E0E		(BIT(24))
662
+#define SCTLR_EL1_SPAN		(BIT(23))
663
+#define SCTLR_EL1_NTWE		(BIT(18))
664
+#define SCTLR_EL1_NTWI		(BIT(16))
665
+#define SCTLR_EL1_UCT		(BIT(15))
666
+#define SCTLR_EL1_DZE		(BIT(14))
667
+#define SCTLR_EL1_UMA		(BIT(9))
668
+#define SCTLR_EL1_SED		(BIT(8))
669
+#define SCTLR_EL1_ITD		(BIT(7))
670
+#define SCTLR_EL1_CP15BEN	(BIT(5))
671
+#define SCTLR_EL1_SA0		(BIT(4))
672
+
673
+#define SCTLR_EL1_RES1	((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
674
+			 (BIT(29)))
497675 
498676 #ifdef CONFIG_CPU_BIG_ENDIAN
499677 #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
500
-#define ENDIAN_CLEAR_EL1	0
501678 #else
502679 #define ENDIAN_SET_EL1		0
503
-#define ENDIAN_CLEAR_EL1	(SCTLR_EL1_E0E | SCTLR_ELx_EE)
504680 #endif
505681 
506
-#define SCTLR_EL1_SET	(SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   |\
507
-			 SCTLR_EL1_SA0  | SCTLR_EL1_SED  | SCTLR_ELx_I    |\
508
-			 SCTLR_EL1_DZE  | SCTLR_EL1_UCT  | SCTLR_EL1_NTWI |\
509
-			 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
510
-			 ENDIAN_SET_EL1 | SCTLR_EL1_UCI  | SCTLR_EL1_RES1)
511
-#define SCTLR_EL1_CLEAR	(SCTLR_ELx_A   | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD    |\
512
-			 SCTLR_EL1_UMA | SCTLR_ELx_WXN     | ENDIAN_CLEAR_EL1 |\
513
-			 SCTLR_ELx_DSSBS | SCTLR_EL1_RES0)
682
+#define INIT_SCTLR_EL1_MMU_OFF \
683
+	(ENDIAN_SET_EL1 | SCTLR_EL1_RES1)
514684 
515
-#if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffff
516
-#error "Inconsistent SCTLR_EL1 set/clear bits"
517
-#endif
685
+#define INIT_SCTLR_EL1_MMU_ON \
686
+	(SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   | SCTLR_EL1_SA0   | \
687
+	 SCTLR_EL1_SED  | SCTLR_ELx_I    | SCTLR_EL1_DZE  | SCTLR_EL1_UCT   | \
688
+	 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
689
+	 ENDIAN_SET_EL1 | SCTLR_EL1_UCI  | SCTLR_EL1_RES1)
690
+
691
+/* MAIR_ELx memory attributes (used by Linux) */
692
+#define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
693
+#define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
694
+#define MAIR_ATTR_DEVICE_GRE		UL(0x0c)
695
+#define MAIR_ATTR_NORMAL_NC		UL(0x44)
696
+#define MAIR_ATTR_NORMAL_WT		UL(0xbb)
697
+#define MAIR_ATTR_NORMAL_TAGGED		UL(0xf0)
698
+#define MAIR_ATTR_NORMAL		UL(0xff)
699
+#define MAIR_ATTR_MASK			UL(0xff)
700
+#define MAIR_ATTR_NORMAL_iNC_oWB	UL(0xf4)
701
+
702
+/* Position the attr at the correct index */
703
+#define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
518704 
519705 /* id_aa64isar0 */
706
+#define ID_AA64ISAR0_RNDR_SHIFT		60
707
+#define ID_AA64ISAR0_TLB_SHIFT		56
520708 #define ID_AA64ISAR0_TS_SHIFT		52
521709 #define ID_AA64ISAR0_FHM_SHIFT		48
522710 #define ID_AA64ISAR0_DP_SHIFT		44
....@@ -530,16 +718,64 @@
530718 #define ID_AA64ISAR0_SHA1_SHIFT		8
531719 #define ID_AA64ISAR0_AES_SHIFT		4
532720 
721
+#define ID_AA64ISAR0_TLB_RANGE_NI	0x0
722
+#define ID_AA64ISAR0_TLB_RANGE		0x2
723
+
533724 /* id_aa64isar1 */
725
+#define ID_AA64ISAR1_I8MM_SHIFT		52
726
+#define ID_AA64ISAR1_DGH_SHIFT		48
727
+#define ID_AA64ISAR1_BF16_SHIFT		44
728
+#define ID_AA64ISAR1_SPECRES_SHIFT	40
729
+#define ID_AA64ISAR1_SB_SHIFT		36
730
+#define ID_AA64ISAR1_FRINTTS_SHIFT	32
731
+#define ID_AA64ISAR1_GPI_SHIFT		28
732
+#define ID_AA64ISAR1_GPA_SHIFT		24
534733 #define ID_AA64ISAR1_LRCPC_SHIFT	20
535734 #define ID_AA64ISAR1_FCMA_SHIFT		16
536735 #define ID_AA64ISAR1_JSCVT_SHIFT	12
736
+#define ID_AA64ISAR1_API_SHIFT		8
737
+#define ID_AA64ISAR1_APA_SHIFT		4
537738 #define ID_AA64ISAR1_DPB_SHIFT		0
739
+
740
+#define ID_AA64ISAR1_APA_NI			0x0
741
+#define ID_AA64ISAR1_APA_ARCHITECTED		0x1
742
+#define ID_AA64ISAR1_APA_ARCH_EPAC		0x2
743
+#define ID_AA64ISAR1_APA_ARCH_EPAC2		0x3
744
+#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC	0x4
745
+#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB	0x5
746
+#define ID_AA64ISAR1_API_NI			0x0
747
+#define ID_AA64ISAR1_API_IMP_DEF		0x1
748
+#define ID_AA64ISAR1_API_IMP_DEF_EPAC		0x2
749
+#define ID_AA64ISAR1_API_IMP_DEF_EPAC2		0x3
750
+#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC	0x4
751
+#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB	0x5
752
+#define ID_AA64ISAR1_GPA_NI			0x0
753
+#define ID_AA64ISAR1_GPA_ARCHITECTED		0x1
754
+#define ID_AA64ISAR1_GPI_NI			0x0
755
+#define ID_AA64ISAR1_GPI_IMP_DEF		0x1
756
+
757
+/* id_aa64isar2 */
758
+#define ID_AA64ISAR2_CLEARBHB_SHIFT	28
759
+#define ID_AA64ISAR2_RPRES_SHIFT	4
760
+#define ID_AA64ISAR2_WFXT_SHIFT		0
761
+
762
+#define ID_AA64ISAR2_RPRES_8BIT		0x0
763
+#define ID_AA64ISAR2_RPRES_12BIT	0x1
764
+/*
765
+ * Value 0x1 has been removed from the architecture, and is
766
+ * reserved, but has not yet been removed from the ARM ARM
767
+ * as of ARM DDI 0487G.b.
768
+ */
769
+#define ID_AA64ISAR2_WFXT_NI		0x0
770
+#define ID_AA64ISAR2_WFXT_SUPPORTED	0x2
538771 
539772 /* id_aa64pfr0 */
540773 #define ID_AA64PFR0_CSV3_SHIFT		60
541774 #define ID_AA64PFR0_CSV2_SHIFT		56
542775 #define ID_AA64PFR0_DIT_SHIFT		48
776
+#define ID_AA64PFR0_AMU_SHIFT		44
777
+#define ID_AA64PFR0_MPAM_SHIFT		40
778
+#define ID_AA64PFR0_SEL2_SHIFT		36
543779 #define ID_AA64PFR0_SVE_SHIFT		32
544780 #define ID_AA64PFR0_RAS_SHIFT		28
545781 #define ID_AA64PFR0_GIC_SHIFT		24
....@@ -550,6 +786,7 @@
550786 #define ID_AA64PFR0_EL1_SHIFT		4
551787 #define ID_AA64PFR0_EL0_SHIFT		0
552788 
789
+#define ID_AA64PFR0_AMU			0x1
553790 #define ID_AA64PFR0_SVE			0x1
554791 #define ID_AA64PFR0_RAS_V1		0x1
555792 #define ID_AA64PFR0_FP_NI		0xf
....@@ -557,17 +794,55 @@
557794 #define ID_AA64PFR0_ASIMD_NI		0xf
558795 #define ID_AA64PFR0_ASIMD_SUPPORTED	0x0
559796 #define ID_AA64PFR0_EL1_64BIT_ONLY	0x1
797
+#define ID_AA64PFR0_EL1_32BIT_64BIT	0x2
560798 #define ID_AA64PFR0_EL0_64BIT_ONLY	0x1
561799 #define ID_AA64PFR0_EL0_32BIT_64BIT	0x2
562800 
563801 /* id_aa64pfr1 */
802
+#define ID_AA64PFR1_MPAMFRAC_SHIFT	16
803
+#define ID_AA64PFR1_RASFRAC_SHIFT	12
804
+#define ID_AA64PFR1_MTE_SHIFT		8
564805 #define ID_AA64PFR1_SSBS_SHIFT		4
806
+#define ID_AA64PFR1_BT_SHIFT		0
565807 
566808 #define ID_AA64PFR1_SSBS_PSTATE_NI	0
567809 #define ID_AA64PFR1_SSBS_PSTATE_ONLY	1
568810 #define ID_AA64PFR1_SSBS_PSTATE_INSNS	2
811
+#define ID_AA64PFR1_BT_BTI		0x1
812
+
813
+#define ID_AA64PFR1_MTE_NI		0x0
814
+#define ID_AA64PFR1_MTE_EL0		0x1
815
+#define ID_AA64PFR1_MTE			0x2
816
+
817
+/* id_aa64zfr0 */
818
+#define ID_AA64ZFR0_F64MM_SHIFT		56
819
+#define ID_AA64ZFR0_F32MM_SHIFT		52
820
+#define ID_AA64ZFR0_I8MM_SHIFT		44
821
+#define ID_AA64ZFR0_SM4_SHIFT		40
822
+#define ID_AA64ZFR0_SHA3_SHIFT		32
823
+#define ID_AA64ZFR0_BF16_SHIFT		20
824
+#define ID_AA64ZFR0_BITPERM_SHIFT	16
825
+#define ID_AA64ZFR0_AES_SHIFT		4
826
+#define ID_AA64ZFR0_SVEVER_SHIFT	0
827
+
828
+#define ID_AA64ZFR0_F64MM		0x1
829
+#define ID_AA64ZFR0_F32MM		0x1
830
+#define ID_AA64ZFR0_I8MM		0x1
831
+#define ID_AA64ZFR0_BF16		0x1
832
+#define ID_AA64ZFR0_SM4			0x1
833
+#define ID_AA64ZFR0_SHA3		0x1
834
+#define ID_AA64ZFR0_BITPERM		0x1
835
+#define ID_AA64ZFR0_AES			0x1
836
+#define ID_AA64ZFR0_AES_PMULL		0x2
837
+#define ID_AA64ZFR0_SVEVER_SVE2		0x1
569838 
570839 /* id_aa64mmfr0 */
840
+#define ID_AA64MMFR0_ECV_SHIFT		60
841
+#define ID_AA64MMFR0_FGT_SHIFT		56
842
+#define ID_AA64MMFR0_EXS_SHIFT		44
843
+#define ID_AA64MMFR0_TGRAN4_2_SHIFT	40
844
+#define ID_AA64MMFR0_TGRAN64_2_SHIFT	36
845
+#define ID_AA64MMFR0_TGRAN16_2_SHIFT	32
571846 #define ID_AA64MMFR0_TGRAN4_SHIFT	28
572847 #define ID_AA64MMFR0_TGRAN64_SHIFT	24
573848 #define ID_AA64MMFR0_TGRAN16_SHIFT	20
....@@ -577,14 +852,23 @@
577852 #define ID_AA64MMFR0_ASID_SHIFT		4
578853 #define ID_AA64MMFR0_PARANGE_SHIFT	0
579854 
580
-#define ID_AA64MMFR0_TGRAN4_NI		0xf
581
-#define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
582
-#define ID_AA64MMFR0_TGRAN64_NI		0xf
583
-#define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
584
-#define ID_AA64MMFR0_TGRAN16_NI		0x0
585
-#define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1
855
+#define ID_AA64MMFR0_TGRAN4_NI			0xf
856
+#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN	0x0
857
+#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX	0x7
858
+#define ID_AA64MMFR0_TGRAN64_NI			0xf
859
+#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN	0x0
860
+#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX	0x7
861
+#define ID_AA64MMFR0_TGRAN16_NI			0x0
862
+#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN	0x1
863
+#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX	0xf
864
+
586865 #define ID_AA64MMFR0_PARANGE_48		0x5
587866 #define ID_AA64MMFR0_PARANGE_52		0x6
867
+
868
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT	0x0
869
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE	0x1
870
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN	0x2
871
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX	0x7
588872 
589873 #ifdef CONFIG_ARM64_PA_BITS_52
590874 #define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_52
....@@ -593,6 +877,12 @@
593877 #endif
594878 
595879 /* id_aa64mmfr1 */
880
+#define ID_AA64MMFR1_ECBHB_SHIFT	60
881
+#define ID_AA64MMFR1_AFP_SHIFT		44
882
+#define ID_AA64MMFR1_ETS_SHIFT		36
883
+#define ID_AA64MMFR1_TWED_SHIFT		32
884
+#define ID_AA64MMFR1_XNX_SHIFT		28
885
+#define ID_AA64MMFR1_SPECSEI_SHIFT	24
596886 #define ID_AA64MMFR1_PAN_SHIFT		20
597887 #define ID_AA64MMFR1_LOR_SHIFT		16
598888 #define ID_AA64MMFR1_HPD_SHIFT		12
....@@ -604,8 +894,16 @@
604894 #define ID_AA64MMFR1_VMIDBITS_16	2
605895 
606896 /* id_aa64mmfr2 */
897
+#define ID_AA64MMFR2_E0PD_SHIFT		60
898
+#define ID_AA64MMFR2_EVT_SHIFT		56
899
+#define ID_AA64MMFR2_BBM_SHIFT		52
900
+#define ID_AA64MMFR2_TTL_SHIFT		48
607901 #define ID_AA64MMFR2_FWB_SHIFT		40
902
+#define ID_AA64MMFR2_IDS_SHIFT		36
608903 #define ID_AA64MMFR2_AT_SHIFT		32
904
+#define ID_AA64MMFR2_ST_SHIFT		28
905
+#define ID_AA64MMFR2_NV_SHIFT		24
906
+#define ID_AA64MMFR2_CCIDX_SHIFT	20
609907 #define ID_AA64MMFR2_LVA_SHIFT		16
610908 #define ID_AA64MMFR2_IESB_SHIFT		12
611909 #define ID_AA64MMFR2_LSM_SHIFT		8
....@@ -613,6 +911,9 @@
613911 #define ID_AA64MMFR2_CNP_SHIFT		0
614912 
615913 /* id_aa64dfr0 */
914
+#define ID_AA64DFR0_TRBE_SHIFT		44
915
+#define ID_AA64DFR0_TRACE_FILT_SHIFT	40
916
+#define ID_AA64DFR0_DOUBLELOCK_SHIFT	36
616917 #define ID_AA64DFR0_PMSVER_SHIFT	32
617918 #define ID_AA64DFR0_CTX_CMPS_SHIFT	28
618919 #define ID_AA64DFR0_WRPS_SHIFT		20
....@@ -621,12 +922,90 @@
621922 #define ID_AA64DFR0_TRACEVER_SHIFT	4
622923 #define ID_AA64DFR0_DEBUGVER_SHIFT	0
623924 
925
+#define ID_AA64DFR0_PMUVER_8_0		0x1
926
+#define ID_AA64DFR0_PMUVER_8_1		0x4
927
+#define ID_AA64DFR0_PMUVER_8_4		0x5
928
+#define ID_AA64DFR0_PMUVER_8_5		0x6
929
+#define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
930
+
931
+#define ID_DFR0_PERFMON_SHIFT		24
932
+
933
+#define ID_DFR0_PERFMON_8_0		0x3
934
+#define ID_DFR0_PERFMON_8_1		0x4
935
+#define ID_DFR0_PERFMON_8_4		0x5
936
+#define ID_DFR0_PERFMON_8_5		0x6
937
+
938
+#define ID_ISAR4_SWP_FRAC_SHIFT		28
939
+#define ID_ISAR4_PSR_M_SHIFT		24
940
+#define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT	20
941
+#define ID_ISAR4_BARRIER_SHIFT		16
942
+#define ID_ISAR4_SMC_SHIFT		12
943
+#define ID_ISAR4_WRITEBACK_SHIFT	8
944
+#define ID_ISAR4_WITHSHIFTS_SHIFT	4
945
+#define ID_ISAR4_UNPRIV_SHIFT		0
946
+
947
+#define ID_DFR1_MTPMU_SHIFT		0
948
+
949
+#define ID_ISAR0_DIVIDE_SHIFT		24
950
+#define ID_ISAR0_DEBUG_SHIFT		20
951
+#define ID_ISAR0_COPROC_SHIFT		16
952
+#define ID_ISAR0_CMPBRANCH_SHIFT	12
953
+#define ID_ISAR0_BITFIELD_SHIFT		8
954
+#define ID_ISAR0_BITCOUNT_SHIFT		4
955
+#define ID_ISAR0_SWAP_SHIFT		0
956
+
624957 #define ID_ISAR5_RDM_SHIFT		24
625958 #define ID_ISAR5_CRC32_SHIFT		16
626959 #define ID_ISAR5_SHA2_SHIFT		12
627960 #define ID_ISAR5_SHA1_SHIFT		8
628961 #define ID_ISAR5_AES_SHIFT		4
629962 #define ID_ISAR5_SEVL_SHIFT		0
963
+
964
+#define ID_ISAR6_I8MM_SHIFT		24
965
+#define ID_ISAR6_BF16_SHIFT		20
966
+#define ID_ISAR6_SPECRES_SHIFT		16
967
+#define ID_ISAR6_SB_SHIFT		12
968
+#define ID_ISAR6_FHM_SHIFT		8
969
+#define ID_ISAR6_DP_SHIFT		4
970
+#define ID_ISAR6_JSCVT_SHIFT		0
971
+
972
+#define ID_MMFR0_INNERSHR_SHIFT		28
973
+#define ID_MMFR0_FCSE_SHIFT		24
974
+#define ID_MMFR0_AUXREG_SHIFT		20
975
+#define ID_MMFR0_TCM_SHIFT		16
976
+#define ID_MMFR0_SHARELVL_SHIFT		12
977
+#define ID_MMFR0_OUTERSHR_SHIFT		8
978
+#define ID_MMFR0_PMSA_SHIFT		4
979
+#define ID_MMFR0_VMSA_SHIFT		0
980
+
981
+#define ID_MMFR4_EVT_SHIFT		28
982
+#define ID_MMFR4_CCIDX_SHIFT		24
983
+#define ID_MMFR4_LSM_SHIFT		20
984
+#define ID_MMFR4_HPDS_SHIFT		16
985
+#define ID_MMFR4_CNP_SHIFT		12
986
+#define ID_MMFR4_XNX_SHIFT		8
987
+#define ID_MMFR4_AC2_SHIFT		4
988
+#define ID_MMFR4_SPECSEI_SHIFT		0
989
+
990
+#define ID_MMFR5_ETS_SHIFT		0
991
+
992
+#define ID_PFR0_DIT_SHIFT		24
993
+#define ID_PFR0_CSV2_SHIFT		16
994
+#define ID_PFR0_STATE3_SHIFT		12
995
+#define ID_PFR0_STATE2_SHIFT		8
996
+#define ID_PFR0_STATE1_SHIFT		4
997
+#define ID_PFR0_STATE0_SHIFT		0
998
+
999
+#define ID_DFR0_PERFMON_SHIFT		24
1000
+#define ID_DFR0_MPROFDBG_SHIFT		20
1001
+#define ID_DFR0_MMAPTRC_SHIFT		16
1002
+#define ID_DFR0_COPTRC_SHIFT		12
1003
+#define ID_DFR0_MMAPDBG_SHIFT		8
1004
+#define ID_DFR0_COPSDBG_SHIFT		4
1005
+#define ID_DFR0_COPDBG_SHIFT		0
1006
+
1007
+#define ID_PFR2_SSBS_SHIFT		4
1008
+#define ID_PFR2_CSV3_SHIFT		0
6301009 
6311010 #define MVFR0_FPROUND_SHIFT		28
6321011 #define MVFR0_FPSHVEC_SHIFT		24
....@@ -646,29 +1025,34 @@
6461025 #define MVFR1_FPDNAN_SHIFT		4
6471026 #define MVFR1_FPFTZ_SHIFT		0
6481027 
649
-
650
-#define ID_AA64MMFR0_TGRAN4_SHIFT	28
651
-#define ID_AA64MMFR0_TGRAN64_SHIFT	24
652
-#define ID_AA64MMFR0_TGRAN16_SHIFT	20
653
-
654
-#define ID_AA64MMFR0_TGRAN4_NI		0xf
655
-#define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
656
-#define ID_AA64MMFR0_TGRAN64_NI		0xf
657
-#define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
658
-#define ID_AA64MMFR0_TGRAN16_NI		0x0
659
-#define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1
1028
+#define ID_PFR1_GIC_SHIFT		28
1029
+#define ID_PFR1_VIRT_FRAC_SHIFT		24
1030
+#define ID_PFR1_SEC_FRAC_SHIFT		20
1031
+#define ID_PFR1_GENTIMER_SHIFT		16
1032
+#define ID_PFR1_VIRTUALIZATION_SHIFT	12
1033
+#define ID_PFR1_MPROGMOD_SHIFT		8
1034
+#define ID_PFR1_SECURITY_SHIFT		4
1035
+#define ID_PFR1_PROGMOD_SHIFT		0
6601036 
6611037 #if defined(CONFIG_ARM64_4K_PAGES)
662
-#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN4_SHIFT
663
-#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN4_SUPPORTED
1038
+#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN4_SHIFT
1039
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN
1040
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX
6641041 #elif defined(CONFIG_ARM64_16K_PAGES)
665
-#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN16_SHIFT
666
-#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN16_SUPPORTED
1042
+#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN16_SHIFT
1043
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN
1044
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX
6671045 #elif defined(CONFIG_ARM64_64K_PAGES)
668
-#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN64_SHIFT
669
-#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN64_SUPPORTED
1046
+#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN64_SHIFT
1047
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN
1048
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX
6701049 #endif
6711050 
1051
+#define MVFR2_FPMISC_SHIFT		4
1052
+#define MVFR2_SIMDMISC_SHIFT		0
1053
+
1054
+#define DCZID_DZP_SHIFT			4
1055
+#define DCZID_BS_SHIFT			0
6721056 
6731057 /*
6741058  * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
....@@ -679,13 +1063,58 @@
6791063 #define ZCR_ELx_LEN_SIZE	9
6801064 #define ZCR_ELx_LEN_MASK	0x1ff
6811065 
682
-#define CPACR_EL1_ZEN_EL1EN	(1 << 16) /* enable EL1 access */
683
-#define CPACR_EL1_ZEN_EL0EN	(1 << 17) /* enable EL0 access, if EL1EN set */
1066
+#define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
1067
+#define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
6841068 #define CPACR_EL1_ZEN		(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
6851069 
1070
+/* TCR EL1 Bit Definitions */
1071
+#define SYS_TCR_EL1_TCMA1	(BIT(58))
1072
+#define SYS_TCR_EL1_TCMA0	(BIT(57))
1073
+
1074
+/* GCR_EL1 Definitions */
1075
+#define SYS_GCR_EL1_RRND	(BIT(16))
1076
+#define SYS_GCR_EL1_EXCL_MASK	0xffffUL
1077
+
1078
+#ifdef CONFIG_KASAN_HW_TAGS
1079
+/*
1080
+ * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
1081
+ * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
1082
+ */
1083
+#define __MTE_TAG_MIN		(KASAN_TAG_MIN & 0xf)
1084
+#define __MTE_TAG_MAX		(KASAN_TAG_MAX & 0xf)
1085
+#define __MTE_TAG_INCL		GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
1086
+#define KERNEL_GCR_EL1_EXCL	(SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
1087
+#else
1088
+#define KERNEL_GCR_EL1_EXCL	SYS_GCR_EL1_EXCL_MASK
1089
+#endif
1090
+
1091
+#define KERNEL_GCR_EL1		(SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
1092
+
1093
+/* RGSR_EL1 Definitions */
1094
+#define SYS_RGSR_EL1_TAG_MASK	0xfUL
1095
+#define SYS_RGSR_EL1_SEED_SHIFT	8
1096
+#define SYS_RGSR_EL1_SEED_MASK	0xffffUL
1097
+
1098
+/* GMID_EL1 field definitions */
1099
+#define SYS_GMID_EL1_BS_SHIFT	0
1100
+#define SYS_GMID_EL1_BS_SIZE	4
1101
+
1102
+/* TFSR{,E0}_EL1 bit definitions */
1103
+#define SYS_TFSR_EL1_TF0_SHIFT	0
1104
+#define SYS_TFSR_EL1_TF1_SHIFT	1
1105
+#define SYS_TFSR_EL1_TF0	(UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
1106
+#define SYS_TFSR_EL1_TF1	(UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
6861107 
6871108 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
688
-#define SYS_MPIDR_SAFE_VAL		(1UL << 31)
1109
+#define SYS_MPIDR_SAFE_VAL	(BIT(31))
1110
+
1111
+#define TRFCR_ELx_TS_SHIFT		5
1112
+#define TRFCR_ELx_TS_VIRTUAL		((0x1UL) << TRFCR_ELx_TS_SHIFT)
1113
+#define TRFCR_ELx_TS_GUEST_PHYSICAL	((0x2UL) << TRFCR_ELx_TS_SHIFT)
1114
+#define TRFCR_ELx_TS_PHYSICAL		((0x3UL) << TRFCR_ELx_TS_SHIFT)
1115
+#define TRFCR_EL2_CX			BIT(3)
1116
+#define TRFCR_ELx_ExTRE			BIT(1)
1117
+#define TRFCR_ELx_E0TRE			BIT(0)
6891118 
6901119 #ifdef __ASSEMBLY__
6911120 
....@@ -706,6 +1135,7 @@
7061135 
7071136 #include <linux/build_bug.h>
7081137 #include <linux/types.h>
1138
+#include <asm/alternative.h>
7091139 
7101140 #define __DEFINE_MRS_MSR_S_REGNUM				\
7111141 "	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
....@@ -787,6 +1217,21 @@
7871217 		write_sysreg(__scs_new, sysreg);			\
7881218 } while (0)
7891219 
1220
+#define sysreg_clear_set_s(sysreg, clear, set) do {			\
1221
+	u64 __scs_val = read_sysreg_s(sysreg);				\
1222
+	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
1223
+	if (__scs_new != __scs_val)					\
1224
+		write_sysreg_s(__scs_new, sysreg);			\
1225
+} while (0)
1226
+
1227
+#define read_sysreg_par() ({						\
1228
+	u64 par;							\
1229
+	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
1230
+	par = read_sysreg(par_el1);					\
1231
+	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
1232
+	par;								\
1233
+})
1234
+
7901235 #endif
7911236 
7921237 #endif	/* __ASM_SYSREG_H */