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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/arch/arm64/include/asm/arch_gicv3.h
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@@ -1,19 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * arch/arm64/include/asm/arch_gicv3.h
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  *
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  * Copyright (C) 2015 ARM Ltd.
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- *
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- * This program is free software: you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 #ifndef __ASM_ARCH_GICV3_H
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 #define __ASM_ARCH_GICV3_H
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@@ -22,6 +11,7 @@
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11
 
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 #ifndef __ASSEMBLY__
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+#include <linux/irqchip/arm-gic-common.h>
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 #include <linux/stringify.h>
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 #include <asm/barrier.h>
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 #include <asm/cacheflush.h>
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@@ -42,7 +32,7 @@
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 	isb();
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 }
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-static inline void gic_write_dir(u32 irq)
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+static __always_inline void gic_write_dir(u32 irq)
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 {
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 	write_sysreg_s(irq, SYS_ICC_DIR_EL1);
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 	isb();
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@@ -114,6 +104,21 @@
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 	write_sysreg_s(val, SYS_ICC_BPR1_EL1);
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 }
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+static inline u32 gic_read_pmr(void)
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+{
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+	return read_sysreg_s(SYS_ICC_PMR_EL1);
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+}
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+
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+static __always_inline void gic_write_pmr(u32 val)
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+{
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+	write_sysreg_s(val, SYS_ICC_PMR_EL1);
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+}
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+
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+static inline u32 gic_read_rpr(void)
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+{
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+	return read_sysreg_s(SYS_ICC_RPR_EL1);
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+}
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+
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 #define gic_read_typer(c)		readq_relaxed(c)
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 #define gic_write_irouter(v, c)		writeq_relaxed(v, c)
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 #define gic_read_lpir(c)		readq_relaxed(c)
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@@ -135,10 +140,41 @@
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 #define gicr_write_pendbaser(v, c)	writeq_relaxed(v, c)
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 #define gicr_read_pendbaser(c)		readq_relaxed(c)
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-#define gits_write_vpropbaser(v, c)	writeq_relaxed(v, c)
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+#define gicr_write_vpropbaser(v, c)	writeq_relaxed(v, c)
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+#define gicr_read_vpropbaser(c)		readq_relaxed(c)
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-#define gits_write_vpendbaser(v, c)	writeq_relaxed(v, c)
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-#define gits_read_vpendbaser(c)		readq_relaxed(c)
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+#define gicr_write_vpendbaser(v, c)	writeq_relaxed(v, c)
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+#define gicr_read_vpendbaser(c)		readq_relaxed(c)
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+
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+static inline bool gic_prio_masking_enabled(void)
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+{
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+	return system_uses_irq_prio_masking();
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+}
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+
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+static inline void gic_pmr_mask_irqs(void)
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+{
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+	BUILD_BUG_ON(GICD_INT_DEF_PRI < (__GIC_PRIO_IRQOFF |
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+					 GIC_PRIO_PSR_I_SET));
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+	BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);
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+	/*
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+	 * Need to make sure IRQON allows IRQs when SCR_EL3.FIQ is cleared
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+	 * and non-secure PMR accesses are not subject to the shifts that
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+	 * are applied to IRQ priorities
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+	 */
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+	BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON);
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+	/*
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+	 * Same situation as above, but now we make sure that we can mask
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+	 * regular interrupts.
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+	 */
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+	BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) < (__GIC_PRIO_IRQOFF_NS |
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+							 GIC_PRIO_PSR_I_SET));
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+	gic_write_pmr(GIC_PRIO_IRQOFF);
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+}
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+
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+static inline void gic_arch_enable_irqs(void)
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+{
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+	asm volatile ("msr daifclr, #2" : : : "memory");
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+}
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 #endif /* __ASSEMBLY__ */
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 #endif /* __ASM_ARCH_GICV3_H */