~hc/RK356X_SDK_RELEASE.git

..	..	@@ -8,6 +8,7 @@
8	8
9	9	#include <dt-bindings/gpio/gpio.h>
10	10	#include <dt-bindings/pinctrl/rockchip.h>
	11	+#include <dt-bindings/display/media-bus-format.h>
11	12	#include "rk3568.dtsi"
12	13	#include "rk3568-evb.dtsi"
13	14
..	..	@@ -17,7 +18,8 @@
17	18
18	19	rk_headset: rk-headset {
19	20	compatible = "rockchip_headset";
20		- headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
	21	+ headset_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>;
	22	+ spk_ctl_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;//AMP_SD_GPIO4_C2_3V3
21	23	pinctrl-names = "default";
22	24	pinctrl-0 = <&hp_det>;
23	25	};
..	..	@@ -67,7 +69,9 @@
67	69	regulator-name = "vcc3v3_pcie";
68	70	regulator-min-microvolt = <3300000>;
69	71	regulator-max-microvolt = <3300000>;
	72	+ regulator-always-on;
70	73	enable-active-high;
	74	+ regulator-boot-on;
71	75	gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
72	76	startup-delay-us = <5000>;
73	77	vin-supply = <&dc_12v>;
..	..	@@ -82,7 +86,7 @@
82	86	regulator-max-microvolt = <3300000>;
83	87	vin-supply = <&vcc5v0_sys>;
84	88	};
85		-
	89	+#if 0
86	90	vcc_camera: vcc-camera-regulator {
87	91	compatible = "regulator-fixed";
88	92	gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
..	..	@@ -92,43 +96,168 @@
92	96	enable-active-high;
93	97	regulator-always-on;
94	98	regulator-boot-on;
95		-
96	99	};
97		-
	100	+#endif
	101	+ ndj_io_init {
	102	+ compatible = "nk_io_control";
	103	+ pinctrl-names = "default";
	104	+ pinctrl-0 = <&nk_io_gpio>;
	105	+
	106	+ //gpio_op0 = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
	107	+
	108	+ vcc_5v {
	109	+ gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
	110	+ gpio_function = <0>;
	111	+ };
	112	+
	113	+ vcc_12v {
	114	+ gpio_num = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; //VCC12_IO_EN_GPIO0_C7_3V3
	115	+ gpio_function = <0>;
	116	+ };
	117	+
	118	+ hub_host2_rst {
	119	+ gpio_num = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; //HUB_RST_GPIO4_D2_3V3
	120	+ gpio_function = <3>;
	121	+ };
	122	+
	123	+ hub_host3 {
	124	+ gpio_num = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //HOST3_EN_GPIO4_B2_1V8
	125	+ gpio_function = <0>;
	126	+ };
	127	+
	128	+ wake_4g {
	129	+ gpio_num = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; //4G_WAKEUP_GPIO01_B1_3V3
	130	+ gpio_function = <0>;
	131	+ };
	132	+
	133	+ air_mode_4g {
	134	+ gpio_num = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; //4G_AIR_MODE_GPIO01_B0_3V3
	135	+ gpio_function = <0>;
	136	+ };
	137	+
	138	+ reset_4g {
	139	+ gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; //4G_RST_GPIO01_B2_3V3
	140	+ gpio_function = <3>;
	141	+ };
	142	+
	143	+ en_4g {
	144	+ gpio_num = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; //4G_PWREN_H_GPIO0_C6
	145	+ gpio_function = <0>;
	146	+ };
	147	+
	148	+ hp_en {
	149	+ gpio_num = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;//HP_EN_GPIO3_A6_3V3
	150	+ gpio_function = <0>;
	151	+ };
	152	+
	153	+ wifi_power_en {
	154	+ gpio_num = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
	155	+ gpio_function = <0>;
	156	+ };
	157	+ #if 0
	158	+ do1 {
	159	+ gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
	160	+ gpio_function = <0>;
	161	+ };
	162	+
	163	+ do2 {
	164	+ gpio_num = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
	165	+ gpio_function = <0>;
	166	+ };
	167	+
	168	+ do3 {
	169	+ gpio_num = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
	170	+ gpio_function = <0>;
	171	+ };
	172	+
	173	+ do4 {
	174	+ gpio_num = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
	175	+ gpio_function = <0>;
	176	+ };
	177	+
	178	+ do5 {
	179	+ gpio_num = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>;
	180	+ gpio_function = <0>;
	181	+ };
	182	+
	183	+ do6 {
	184	+ gpio_num = <&gpio2 RK_PD7 GPIO_ACTIVE_LOW>;
	185	+ gpio_function = <0>;
	186	+ };
	187	+
	188	+ do7 {
	189	+ gpio_num = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
	190	+ gpio_function = <0>;
	191	+ };
	192	+
	193	+ di1 {
	194	+ gpio_num = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
	195	+ gpio_function = <1>;
	196	+ };
	197	+ #endif
	198	+ };
	199	+#if 0
98	200	nk_io_init {
99	201	compatible = "nk_io_control";
100		- hub_host2_5v_gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; //USB_HOST_PWREN_H_GPIO0_A6
101		- usb_en_oc_gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; //USB_EN_OC_GPIO0_A5
102		- lcd_bk_en_gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
103		- lcd_pwblk_gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
104		- vcc3_io_en_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
	202	+// vcc3_io_en_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
105	203	hub_host2_5V_rest_gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; //HUB_RST_GPIO4_D2_3V3
106	204	hub_host3_5v_gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //HOST3_EN_GPIO4_B2_1V8
107		-// hub_host3_5V_rest_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
108	205	vcc_5v_io = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
109	206	vcc_12v_io = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; //VCC12_IO_EN_GPIO0_C7_3V3
110	207	en_4g_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; //4G_PWREN_H_GPIO0_C6
111	208	reset_4g_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; //4G_RST_GPIO01_B2_3V3
112	209	air_mode_4g_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; //4G_AIR_MODE_GPIO01_B0_3V3
113	210	wake_4g_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; //4G_WAKEUP_GPIO01_B1_3V3
114		-
115		- edp_enable_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
116		- edp_gpio0 = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; //7511_GPIO0-GPIO3_D2
117		- edp_gpio1 = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>; //7511_GPIO1-GPIO3_D3
118		- edp_gpio2 = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; //7511_GPIO2-GPIO3_D4
119		- edp_gpio3 = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; //7511_GPIO3-GPIO3_D5
120		- edp_reset = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; //7511_RST_GPIO3_D1
121		-// tp_reset = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
122		-// vddio_mipi = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
123		-
124		- wifi_power_en_gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
125		-
126		- // pinctrl-names = "default";
127		-// pinctrl-0 = <&nk_io_gpio>;
128		- nodka_lvds = <9>;
	211	+ hp_en_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;//HP_EN_GPIO3_A6_3V3
	212	+// spk_out_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;//AMP_SD_GPIO4_C2_3V3
	213	+ wifi_power_en_gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
	214	+// pcie_power_en_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;//PCIE_PWREN_H_GPIO0_D4
	215	+ pinctrl-names = "default";
	216	+ pinctrl-0 = <&nk_io_gpio>;
129	217	};
	218	+#endif
	219	+ panel: panel {
	220	+ compatible = "simple-panel";
	221	+ backlight = <&backlight>;
	222	+ power-supply = <&vcc3v3_lcd0_n>;
	223	+ enable-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; //LCD0_VDD_H_GPIO2_D4
	224	+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; //7511_RST_GPIO3_D1
	225	+ edp-bl-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
	226	+ edp-bl-en = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
	227	+ bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
	228	+ bpc = <8>;
	229	+ prepare-delay-ms = <200>;
	230	+ enable-delay-ms = <20>;
	231	+ lvds-gpio0 = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; //7511_GPIO0-GPIO3_D2
	232	+ lvds-gpio1 = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; //7511_GPIO1-GPIO3_D3
	233	+ lvds-gpio2 = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; //7511_GPIO2-GPIO3_D4
	234	+ lvds-gpio3 = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; //7511_GPIO3-GPIO3_D5
	235	+ nodka-lvds = <15>;
130	236
131		-
	237	+ display-timings {
	238	+ native-mode = <&timing0>;
	239	+ timing0: timing0 {
	240	+ clock-frequency = <72500000>;
	241	+ hactive = <1280>;
	242	+ vactive = <800>;
	243	+ hfront-porch = <70>;
	244	+ hsync-len = <2>;
	245	+ hback-porch = <88>;
	246	+ vfront-porch = <7>;
	247	+ vsync-len = <4>;
	248	+ vback-porch = <17>;
	249	+ hsync-active = <21>;
	250	+ vsync-active = <0>;
	251	+ de-active = <0>;
	252	+ pixelclk-active = <0>;
	253	+ };
	254	+ };
	255	+ ports {
	256	+ panel_in: endpoint {
	257	+ remote-endpoint = <&edp_out>;
	258	+ };
	259	+ };
	260	+ };
132	261	};
133	262
134	263	&combphy0_us {
..	..	@@ -144,11 +273,11 @@
144	273	};
145	274
146	275	&csi2_dphy_hw {
147		- status = "okay";
	276	+ status = "disabled";
148	277	};
149	278
150	279	&csi2_dphy0 {
151		- status = "okay";
	280	+ status = "disabled";
152	281
153	282	ports {
154	283	#address-cells = <1>;
..	..	@@ -191,8 +320,12 @@
191	320	* video_phy0 needs to be enabled
192	321	* when dsi0 is enabled
193	322	*/
	323	+&video_phy0 {
	324	+ status = "disabled";
	325	+};
	326	+
194	327	&dsi0 {
195		- status = "okay";
	328	+ status = "disabled";
196	329	};
197	330
198	331	&dsi0_in_vp0 {
..	..	@@ -200,7 +333,7 @@
200	333	};
201	334
202	335	&dsi0_in_vp1 {
203		- status = "okay";
	336	+ status = "disabled";
204	337	};
205	338
206	339	&dsi0_panel {
..	..	@@ -211,6 +344,10 @@
211	344	* video_phy1 needs to be enabled
212	345	* when dsi1 is enabled
213	346	*/
	347	+
	348	+&video_phy1 {
	349	+ status = "okay";
	350	+};
214	351	&dsi1 {
215	352	status = "disabled";
216	353	};
..	..	@@ -220,16 +357,40 @@
220	357	};
221	358
222	359	&dsi1_in_vp1 {
223		- status = "disabled";
	360	+ status = "okay";
224	361	};
225	362
226	363	&dsi1_panel {
227		- power-supply = <&vcc3v3_lcd1_n>;
	364	+ power-supply = <&vcc3v3_lcd1_n>; //MIPI_3V3EN_GPIO3_A3_d_3V3
	365	+ vddio-mipi = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; //MIPI_EN_1V8_GPIO3_A4_d_3V3
	366	+ reset-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>; //MIPI_RST_L_GPIO3_C7
	367	+ vcc-5v-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
	368	+ pinctrl-names = "default";
	369	+ pinctrl-0 = <&lcd1_rst_gpio>;
228	370	};
229	371
	372	+&route_dsi1 {
	373	+ status = "disabled";
	374	+ connect = <&vp1_out_dsi1>;
	375	+};
	376	+
	377	+
	378	+/*
	379	+* edp_start
	380	+*/
	381	+
230	382	&edp {
231		- hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
232		- status = "okay";
	383	+ force-hpd;
	384	+ status = "okay";
	385	+ ports {
	386	+ port@1 {
	387	+ reg = <1>;
	388	+ edp_out: endpoint {
	389	+ remote-endpoint = <&panel_in>;
	390	+ };
	391	+ };
	392	+
	393	+ };
233	394	};
234	395
235	396	&edp_phy {
..	..	@@ -237,18 +398,67 @@
237	398	};
238	399
239	400	&edp_in_vp0 {
240		- status = "okay";
	401	+ status = "disabled";
241	402	};
242	403
243	404	&edp_in_vp1 {
	405	+ status = "okay";
	406	+
	407	+};
	408	+
	409	+&route_edp {
	410	+ status = "okay";
	411	+ connect = <&vp1_out_edp>;
	412	+};
	413	+
	414	+&route_edp {
	415	+ status = "okay";
	416	+};
	417	+/*
	418	+* edp_end
	419	+*/
	420	+
	421	+/*
	422	+* Hdmi_start
	423	+*/
	424	+
	425	+&hdmi {
	426	+ status = "okay";
	427	+ rockchip,phy-table =
	428	+ <92812500 0x8009 0x0000 0x0270>,
	429	+ <165000000 0x800b 0x0000 0x026d>,
	430	+ <185625000 0x800b 0x0000 0x01ed>,
	431	+ <297000000 0x800b 0x0000 0x01ad>,
	432	+ <594000000 0x8029 0x0000 0x0088>,
	433	+ <000000000 0x0000 0x0000 0x0000>;
	434	+};
	435	+
	436	+&route_hdmi {
	437	+ status = "okay";
	438	+ connect = <&vp0_out_hdmi>;
	439	+};
	440	+
	441	+&hdmi_in_vp0 {
	442	+ status = "okay";
	443	+};
	444	+
	445	+&hdmi_in_vp1 {
244	446	status = "disabled";
245	447	};
	448	+
	449	+&hdmi_sound {
	450	+ status = "okay";
	451	+};
	452	+
	453	+/*
	454	+ * Hdmi_END
	455	+*/
246	456
247	457	&gmac0 {
248	458	phy-mode = "rgmii";
249	459	clock_in_out = "output";
250	460
251		- snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
	461	+ snps,reset-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
252	462	snps,reset-active-low;
253	463	/* Reset time is 20ms, 100ms for rtl8211f */
254	464	snps,reset-delays-us = <0 20000 100000>;
..	..	@@ -268,7 +478,9 @@
268	478	rx_delay = <0x2f>;
269	479
270	480	phy-handle = <&rgmii_phy0>;
	481	+
271	482	status = "disabled";
	483	+
272	484	};
273	485
274	486	&gmac1 {
..	..	@@ -302,9 +514,7 @@
302	514	* power-supply should switche to vcc3v3_lcd1_n
303	515	* when mipi panel is connected to dsi1.
304	516	*/
305		-&gt1x {
306		- power-supply = <&vcc3v3_lcd0_n>;
307		-};
	517	+
308	518
309	519	&i2c3 {
310	520	status = "okay";
..	..	@@ -320,13 +530,10 @@
320	530	compatible = "nk_mcu";
321	531	reg = <0x15>;
322	532	};
323		-
324		-
325		-
326	533	};
327	534
328	535	&i2c4 {
329		- status = "okay";
	536	+ status = "disabled";
330	537	gc8034: gc8034@37 {
331	538	compatible = "galaxycore,gc8034";
332	539	status = "okay";
..	..	@@ -338,7 +545,6 @@
338	545	reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
339	546	pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>;
340	547	rockchip,grf = <&grf>;
341		- power-domains = <&power RK3568_PD_VI>;
342	548	rockchip,camera-module-index = <0>;
343	549	rockchip,camera-module-facing = "back";
344	550	rockchip,camera-module-name = "RK-CMK-8M-2-v1";
..	..	@@ -372,7 +578,7 @@
372	578	};
373	579	};
374	580	ov5695: ov5695@36 {
375		- status = "okay";
	581	+ status = "disabled";
376	582	compatible = "ovti,ov5695";
377	583	reg = <0x36>;
378	584	clocks = <&cru CLK_CIF_OUT>;
..	..	@@ -395,6 +601,19 @@
395	601	};
396	602	};
397	603
	604	+&i2c5 {
	605	+ status = "okay";
	606	+
	607	+ hym8563: hym8563@51 {
	608	+ compatible = "haoyu,hym8563";
	609	+ reg = <0x51>;
	610	+ #clock-cells = <0>;
	611	+ clock-frequency = <32768>;
	612	+ clock-output-names = "xin32k";
	613	+ /* rtc_int is not connected */
	614	+ };
	615	+};
	616	+
398	617	&mdio0 {
399	618	rgmii_phy0: phy@0 {
400	619	compatible = "ethernet-phy-ieee802.3-c22";
..	..	@@ -409,73 +628,88 @@
409	628	};
410	629	};
411	630
412		-&video_phy0 {
413		- status = "okay";
414		-};
415	631
416		-&video_phy1 {
417		- status = "disabled";
418		-};
419	632
420	633	&pcie30phy {
421	634	status = "okay";
422	635	};
423	636
424		-&pcie3x2 {
425		- reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
	637	+&pcie2x1 {
	638	+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
426	639	vpcie3v3-supply = <&vcc3v3_pcie>;
427	640	status = "okay";
428	641	};
429	642
430	643	&pinctrl {
431		- cam {
432		- camera_pwr: camera-pwr {
433		- rockchip,pins =
434		- /* camera power en */
435		- <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
436		- };
437		- };
	644	+// cam {
	645	+// camera_pwr: camera-pwr {
	646	+// rockchip,pins =
	647	+// /* camera power en */
	648	+// <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
	649	+// };
	650	+// };
438	651	headphone {
439	652	hp_det: hp-det {
440		- rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
	653	+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>,
	654	+ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
441	655	};
442	656	};
443	657
444	658	wireless-wlan {
445	659	wifi_host_wake_irq: wifi-host-wake-irq {
446		- rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
	660	+ rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
447	661	};
448	662	};
449	663
450	664	wireless-bluetooth {
451		- uart8_gpios: uart8-gpios {
452		- rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
	665	+ uart1_gpios: uart1-gpios {
	666	+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
453	667	};
454	668	};
455		-
456		- nk_io_gpio: nk_io_gpio_col{
457		- rockchip,pins =
458		- <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
459		- <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
460		- <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
461		- <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
462		- <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>,
463		- <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
464		- <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
465		- <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
	669	+
	670	+ lcd1 {
	671	+ lcd1_rst_gpio: lcd1-rst-gpio {
	672	+ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
	673	+ };
	674	+ };
	675	+
	676	+ nk_io_init{
	677	+ nk_io_gpio: nk-io-gpio{
	678	+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
	679	+ <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
	680	+ <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
	681	+ <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
	682	+ <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
	683	+ <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>,
	684	+ <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>,
	685	+ <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
	686	+ <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
	687	+ <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,
	688	+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
	689	+ <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
	690	+ <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
	691	+ <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>,
	692	+ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
	693	+ <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
	694	+ <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,//93 SPI2_CS0_M1_3V3
	695	+ <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>,//94 SPI2_MOSI_M1_3V3
	696	+ <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>,//95 SPI2_MISO_M1_3V3
	697	+ <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,//96 SPI2_CLK_M1_3V3
	698	+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
	699	+ };
466	700	};
467	701	};
468	702
469	703	&rkisp {
470		- status = "okay";
	704	+ status = "disabled";
471	705	};
472	706
473	707	&rkisp_mmu {
474		- status = "okay";
	708	+ status = "disabled";
475	709	};
476	710
477	711	&rkisp_vir0 {
478		- status = "okay";
	712	+ status = "disabled";
479	713
480	714	port {
481	715	#address-cells = <1>;
..	..	@@ -488,34 +722,30 @@
488	722	};
489	723	};
490	724
491		-&route_dsi0 {
492		- status = "okay";
493		- connect = <&vp1_out_dsi0>;
494		-};
495	725
496		-&route_edp {
497		- status = "okay";
498		- connect = <&vp0_out_edp>;
499		-};
500	726
501	727	&sata2 {
502	728	status = "okay";
503	729	};
504	730
505	731	&sdmmc2 {
506		- max-frequency = <150000000>;
507		- supports-sdio;
508		- bus-width = <4>;
509		- disable-wp;
510		- cap-sd-highspeed;
511		- cap-sdio-irq;
512		- keep-power-in-suspend;
513		- mmc-pwrseq = <&sdio_pwrseq>;
514		- non-removable;
515		- pinctrl-names = "default";
516		- pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
517		- sd-uhs-sdr104;
518		- status = "okay";
	732	+ status = "disabled";
	733	+};
	734	+
	735	+&sdmmc1 {
	736	+ max-frequency = <150000000>;
	737	+ supports-sdio;
	738	+ bus-width = <4>;
	739	+ disable-wp;
	740	+ cap-sd-highspeed;
	741	+ cap-sdio-irq;
	742	+ keep-power-in-suspend;
	743	+ mmc-pwrseq = <&sdio_pwrseq>;
	744	+ non-removable;
	745	+ pinctrl-names = "default";
	746	+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
	747	+ sd-uhs-sdr104;
	748	+ status = "okay";
519	749	};
520	750
521	751	&spdif_8ch {
..	..	@@ -531,12 +761,12 @@
531	761	};
532	762
533	763	&vcc3v3_lcd0_n {
534		- gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
	764	+ gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
535	765	enable-active-high;
536	766	};
537	767
538	768	&vcc3v3_lcd1_n {
539		- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
	769	+ gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; //MIPI_3V3EN_GPIO3_A3_d_3V3
540	770	enable-active-high;
541	771	};
542	772
..	..	@@ -551,12 +781,47 @@
551	781	clocks = <&rk809 1>;
552	782	clock-names = "ext_clock";
553	783	//wifi-bt-power-toggle;
554		- uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
	784	+ uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
555	785	pinctrl-names = "default", "rts_gpio";
556		- pinctrl-0 = <&uart8m0_rtsn>;
557		- pinctrl-1 = <&uart8_gpios>;
558		- BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
559		- BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
560		- BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
	786	+ pinctrl-0 = <&uart1m0_rtsn>;
	787	+ pinctrl-1 = <&uart1_gpios>;
	788	+ BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
	789	+ BT,wake_gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
	790	+ BT,wake_host_irq = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
561	791	status = "okay";
562	792	};
	793	+
	794	+&uart0 {
	795	+ status = "okay";
	796	+};
	797	+
	798	+&uart1 {
	799	+ pinctrl-names = "default";
	800	+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
	801	+ status = "okay";
	802	+};
	803	+
	804	+&uart3 {
	805	+ status = "okay";
	806	+ pinctrl-0 = <&uart3m1_xfer>;
	807	+};
	808	+
	809	+&uart4 {
	810	+ status = "okay";
	811	+ pinctrl-0 = <&uart4m1_xfer>;
	812	+};
	813	+
	814	+&uart5 {
	815	+ status = "okay";
	816	+ pinctrl-0 = <&uart5m1_xfer>;
	817	+};
	818	+
	819	+&uart7 {
	820	+ status = "okay";
	821	+ pinctrl-0 = <&uart7m1_xfer>;
	822	+};
	823	+
	824	+&uart9 {
	825	+ status = "okay";
	826	+ pinctrl-0 = <&uart9m1_xfer>;
	827	+};