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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/arch/arm/mach-imx/common.h
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@@ -1,12 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
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  */
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-/*
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- */
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 #ifndef __ASM_ARCH_MXC_COMMON_H__
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 #define __ASM_ARCH_MXC_COMMON_H__
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@@ -21,29 +17,14 @@
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 enum mxc_cpu_pwr_mode;
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 struct of_device_id;
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-void mx21_map_io(void);
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-void mx27_map_io(void);
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 void mx31_map_io(void);
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 void mx35_map_io(void);
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 void imx21_init_early(void);
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-void imx27_init_early(void);
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 void imx31_init_early(void);
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 void imx35_init_early(void);
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 void mxc_init_irq(void __iomem *);
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-void mx21_init_irq(void);
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-void mx27_init_irq(void);
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 void mx31_init_irq(void);
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 void mx35_init_irq(void);
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-void imx21_soc_init(void);
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-void imx27_soc_init(void);
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-void imx31_soc_init(void);
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-void imx35_soc_init(void);
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-int mx21_clocks_init(unsigned long lref, unsigned long fref);
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-int mx27_clocks_init(unsigned long fref);
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-int mx31_clocks_init(unsigned long fref);
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-int mx35_clocks_init(void);
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-struct platform_device *mxc_register_gpio(char *name, int id,
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-	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
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 void mxc_set_cpu_type(unsigned int type);
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 void mxc_restart(enum reboot_mode, const char *);
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 void mxc_arch_reset_init(void __iomem *);
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@@ -53,7 +34,6 @@
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 int mxc_device_init(void);
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 void imx_set_soc_revision(unsigned int rev);
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 void imx_init_revision_from_anatop(void);
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-struct device *imx_soc_device_init(void);
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 void imx6_enable_rbc(bool enable);
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 void imx_gpc_check_dt(void);
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 void imx_gpc_set_arm_power_in_lpm(bool power_off);
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@@ -70,6 +50,15 @@
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 	WAIT_UNCLOCKED_POWER_OFF,	/* WAIT + SRPG */
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 	STOP_POWER_ON,		/* just STOP */
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 	STOP_POWER_OFF,		/* STOP + SRPG */
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+};
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+
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+enum ulp_cpu_pwr_mode {
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+	ULP_PM_HSRUN,    /* High speed run mode */
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+	ULP_PM_RUN,      /* Run mode */
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+	ULP_PM_WAIT,     /* Wait mode */
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+	ULP_PM_STOP,     /* Stop mode */
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+	ULP_PM_VLPS,     /* Very low power stop mode */
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+	ULP_PM_VLLS,     /* very low leakage stop mode */
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 };
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 void imx_enable_cpu(int cpu, bool enable);
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 void imx6_set_int_mem_clk_lpm(bool enable);
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 void imx6sl_set_wait_clk(bool enter);
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 int imx_mmdc_get_ddr_type(void);
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+int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
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 void imx_cpu_die(unsigned int cpu);
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 int imx_cpu_kill(unsigned int cpu);
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 void imx6sl_pm_init(void);
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 void imx6sx_pm_init(void);
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 void imx6ul_pm_init(void);
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+void imx7ulp_pm_init(void);
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 #ifdef CONFIG_PM
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 void imx51_pm_init(void);