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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/arch/arm/include/asm/arch_gicv3.h
....@@ -1,19 +1,8 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * arch/arm/include/asm/arch_gicv3.h
34  *
45  * Copyright (C) 2015 ARM Ltd.
5
- *
6
- * This program is free software: you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
9
- *
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- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
14
- *
15
- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
176  */
187 #ifndef __ASM_ARCH_GICV3_H
198 #define __ASM_ARCH_GICV3_H
....@@ -21,6 +10,7 @@
2110 #ifndef __ASSEMBLY__
2211 
2312 #include <linux/io.h>
13
+#include <linux/io-64-nonatomic-lo-hi.h>
2414 #include <asm/barrier.h>
2515 #include <asm/cacheflush.h>
2616 #include <asm/cp15.h>
....@@ -34,6 +24,7 @@
3424 #define ICC_SRE				__ACCESS_CP15(c12, 0, c12, 5)
3525 #define ICC_IGRPEN1			__ACCESS_CP15(c12, 0, c12, 7)
3626 #define ICC_BPR1			__ACCESS_CP15(c12, 0, c12, 3)
27
+#define ICC_RPR				__ACCESS_CP15(c12, 0, c11, 3)
3728 
3829 #define __ICC_AP0Rx(x)			__ACCESS_CP15(c12, 0, c8, 4 | x)
3930 #define ICC_AP0R0			__ICC_AP0Rx(0)
....@@ -47,71 +38,6 @@
4738 #define ICC_AP1R2			__ICC_AP1Rx(2)
4839 #define ICC_AP1R3			__ICC_AP1Rx(3)
4940 
50
-#define ICC_HSRE			__ACCESS_CP15(c12, 4, c9, 5)
51
-
52
-#define ICH_VSEIR			__ACCESS_CP15(c12, 4, c9, 4)
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-#define ICH_HCR				__ACCESS_CP15(c12, 4, c11, 0)
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-#define ICH_VTR				__ACCESS_CP15(c12, 4, c11, 1)
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-#define ICH_MISR			__ACCESS_CP15(c12, 4, c11, 2)
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-#define ICH_EISR			__ACCESS_CP15(c12, 4, c11, 3)
57
-#define ICH_ELSR			__ACCESS_CP15(c12, 4, c11, 5)
58
-#define ICH_VMCR			__ACCESS_CP15(c12, 4, c11, 7)
59
-
60
-#define __LR0(x)			__ACCESS_CP15(c12, 4, c12, x)
61
-#define __LR8(x)			__ACCESS_CP15(c12, 4, c13, x)
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-
63
-#define ICH_LR0				__LR0(0)
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-#define ICH_LR1				__LR0(1)
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-#define ICH_LR2				__LR0(2)
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-#define ICH_LR3				__LR0(3)
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-#define ICH_LR4				__LR0(4)
68
-#define ICH_LR5				__LR0(5)
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-#define ICH_LR6				__LR0(6)
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-#define ICH_LR7				__LR0(7)
71
-#define ICH_LR8				__LR8(0)
72
-#define ICH_LR9				__LR8(1)
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-#define ICH_LR10			__LR8(2)
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-#define ICH_LR11			__LR8(3)
75
-#define ICH_LR12			__LR8(4)
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-#define ICH_LR13			__LR8(5)
77
-#define ICH_LR14			__LR8(6)
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-#define ICH_LR15			__LR8(7)
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-
80
-/* LR top half */
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-#define __LRC0(x)			__ACCESS_CP15(c12, 4, c14, x)
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-#define __LRC8(x)			__ACCESS_CP15(c12, 4, c15, x)
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-
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-#define ICH_LRC0			__LRC0(0)
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-#define ICH_LRC1			__LRC0(1)
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-#define ICH_LRC2			__LRC0(2)
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-#define ICH_LRC3			__LRC0(3)
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-#define ICH_LRC4			__LRC0(4)
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-#define ICH_LRC5			__LRC0(5)
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-#define ICH_LRC6			__LRC0(6)
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-#define ICH_LRC7			__LRC0(7)
92
-#define ICH_LRC8			__LRC8(0)
93
-#define ICH_LRC9			__LRC8(1)
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-#define ICH_LRC10			__LRC8(2)
95
-#define ICH_LRC11			__LRC8(3)
96
-#define ICH_LRC12			__LRC8(4)
97
-#define ICH_LRC13			__LRC8(5)
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-#define ICH_LRC14			__LRC8(6)
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-#define ICH_LRC15			__LRC8(7)
100
-
101
-#define __ICH_AP0Rx(x)			__ACCESS_CP15(c12, 4, c8, x)
102
-#define ICH_AP0R0			__ICH_AP0Rx(0)
103
-#define ICH_AP0R1			__ICH_AP0Rx(1)
104
-#define ICH_AP0R2			__ICH_AP0Rx(2)
105
-#define ICH_AP0R3			__ICH_AP0Rx(3)
106
-
107
-#define __ICH_AP1Rx(x)			__ACCESS_CP15(c12, 4, c9, x)
108
-#define ICH_AP1R0			__ICH_AP1Rx(0)
109
-#define ICH_AP1R1			__ICH_AP1Rx(1)
110
-#define ICH_AP1R2			__ICH_AP1Rx(2)
111
-#define ICH_AP1R3			__ICH_AP1Rx(3)
112
-
113
-/* A32-to-A64 mappings used by VGIC save/restore */
114
-
11541 #define CPUIF_MAP(a32, a64)			\
11642 static inline void write_ ## a64(u32 val)	\
11743 {						\
....@@ -122,21 +48,6 @@
12248 	return read_sysreg(a32); 		\
12349 }						\
12450 
125
-#define CPUIF_MAP_LO_HI(a32lo, a32hi, a64)	\
126
-static inline void write_ ## a64(u64 val)	\
127
-{						\
128
-	write_sysreg(lower_32_bits(val), a32lo);\
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-	write_sysreg(upper_32_bits(val), a32hi);\
130
-}						\
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-static inline u64 read_ ## a64(void)		\
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-{						\
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-	u64 val = read_sysreg(a32lo);		\
134
-						\
135
-	val |=	(u64)read_sysreg(a32hi) << 32;	\
136
-						\
137
-	return val; 				\
138
-}
139
-
14051 CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
14152 CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
14253 CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
....@@ -146,40 +57,6 @@
14657 CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1)
14758 CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)
14859 CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)
149
-
150
-CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
151
-CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
152
-CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
153
-CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
154
-CPUIF_MAP(ICH_ELSR, ICH_ELSR_EL2)
155
-CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
156
-CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
157
-CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
158
-CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2)
159
-CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2)
160
-CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2)
161
-CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2)
162
-CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2)
163
-CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2)
164
-CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2)
165
-CPUIF_MAP(ICC_SRE, ICC_SRE_EL1)
166
-
167
-CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2)
168
-CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2)
169
-CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2)
170
-CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2)
171
-CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2)
172
-CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2)
173
-CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2)
174
-CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2)
175
-CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2)
176
-CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2)
177
-CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2)
178
-CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2)
179
-CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2)
180
-CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2)
181
-CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2)
182
-CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2)
18360 
18461 #define read_gicreg(r)                 read_##r()
18562 #define write_gicreg(v, r)             write_##r(v)
....@@ -243,6 +120,21 @@
243120 static inline void gic_write_bpr1(u32 val)
244121 {
245122 	write_sysreg(val, ICC_BPR1);
123
+}
124
+
125
+static inline u32 gic_read_pmr(void)
126
+{
127
+	return read_sysreg(ICC_PMR);
128
+}
129
+
130
+static inline void gic_write_pmr(u32 val)
131
+{
132
+	write_sysreg(val, ICC_PMR);
133
+}
134
+
135
+static inline u32 gic_read_rpr(void)
136
+{
137
+	return read_sysreg(ICC_RPR);
246138 }
247139 
248140 /*
....@@ -320,15 +212,16 @@
320212 #define gits_write_cwriter(v, c)	__gic_writeq_nonatomic(v, c)
321213 
322214 /*
323
- * GITS_VPROPBASER - hi and lo bits may be accessed independently.
215
+ * GICR_VPROPBASER - hi and lo bits may be accessed independently.
324216  */
325
-#define gits_write_vpropbaser(v, c)	__gic_writeq_nonatomic(v, c)
217
+#define gicr_read_vpropbaser(c)		__gic_readq_nonatomic(c)
218
+#define gicr_write_vpropbaser(v, c)	__gic_writeq_nonatomic(v, c)
326219 
327220 /*
328
- * GITS_VPENDBASER - the Valid bit must be cleared before changing
221
+ * GICR_VPENDBASER - the Valid bit must be cleared before changing
329222  * anything else.
330223  */
331
-static inline void gits_write_vpendbaser(u64 val, void * __iomem addr)
224
+static inline void gicr_write_vpendbaser(u64 val, void __iomem *addr)
332225 {
333226 	u32 tmp;
334227 
....@@ -345,7 +238,24 @@
345238 	__gic_writeq_nonatomic(val, addr);
346239 }
347240 
348
-#define gits_read_vpendbaser(c)		__gic_readq_nonatomic(c)
241
+#define gicr_read_vpendbaser(c)		__gic_readq_nonatomic(c)
242
+
243
+static inline bool gic_prio_masking_enabled(void)
244
+{
245
+	return false;
246
+}
247
+
248
+static inline void gic_pmr_mask_irqs(void)
249
+{
250
+	/* Should not get called. */
251
+	WARN_ON_ONCE(true);
252
+}
253
+
254
+static inline void gic_arch_enable_irqs(void)
255
+{
256
+	/* Should not get called. */
257
+	WARN_ON_ONCE(true);
258
+}
349259 
350260 #endif /* !__ASSEMBLY__ */
351261 #endif /* !__ASM_ARCH_GICV3_H */