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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/Documentation/devicetree/bindings/xilinx.txt
....@@ -86,149 +86,6 @@
8686 		xlnx,use-parity = <0>;
8787 	};
8888 
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-   Some IP cores actually implement 2 or more logical devices.  In
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-   this case, the device should still describe the whole IP core with
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-   a single node and add a child node for each logical device.  The
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-   ranges property can be used to translate from parent IP-core to the
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-   registers of each device.  In addition, the parent node should be
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-   compatible with the bus type 'xlnx,compound', and should contain
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-   #address-cells and #size-cells, as with any other bus.  (Note: this
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-   makes the assumption that both logical devices have the same bus
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-   binding.  If this is not true, then separate nodes should be used
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-   for each logical device).  The 'cell-index' property can be used to
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-   enumerate logical devices within an IP core.  For example, the
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-   following is the system.mhs entry for the dual ps2 controller found
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-   on the ml403 reference design.
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-
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-	BEGIN opb_ps2_dual_ref
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-		PARAMETER INSTANCE = opb_ps2_dual_ref_0
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-		PARAMETER HW_VER = 1.00.a
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-		PARAMETER C_BASEADDR = 0xA9000000
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-		PARAMETER C_HIGHADDR = 0xA9001FFF
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-		BUS_INTERFACE SOPB = opb_v20_0
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-		PORT Sys_Intr1 = ps2_1_intr
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-		PORT Sys_Intr2 = ps2_2_intr
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-		PORT Clkin1 = ps2_clk_rx_1
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-		PORT Clkin2 = ps2_clk_rx_2
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-		PORT Clkpd1 = ps2_clk_tx_1
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-		PORT Clkpd2 = ps2_clk_tx_2
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-		PORT Rx1 = ps2_d_rx_1
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-		PORT Rx2 = ps2_d_rx_2
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-		PORT Txpd1 = ps2_d_tx_1
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-		PORT Txpd2 = ps2_d_tx_2
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-	END
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-
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-   It would result in the following device tree nodes:
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-
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-	opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
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-		#address-cells = <1>;
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-		#size-cells = <1>;
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-		compatible = "xlnx,compound";
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-		ranges = <0 a9000000 2000>;
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-		// If this device had extra parameters, then they would
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-		// go here.
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-		ps2@0 {
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-			compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
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-			reg = <0 40>;
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-			interrupt-parent = <&opb_intc_0>;
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-			interrupts = <3 0>;
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-			cell-index = <0>;
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-		};
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-		ps2@1000 {
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-			compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
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-			reg = <1000 40>;
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-			interrupt-parent = <&opb_intc_0>;
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-			interrupts = <3 0>;
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-			cell-index = <0>;
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-		};
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-	};
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-
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-   Also, the system.mhs file defines bus attachments from the processor
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-   to the devices.  The device tree structure should reflect the bus
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-   attachments.  Again an example; this system.mhs fragment:
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-
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-	BEGIN ppc405_virtex4
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-		PARAMETER INSTANCE = ppc405_0
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-		PARAMETER HW_VER = 1.01.a
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-		BUS_INTERFACE DPLB = plb_v34_0
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-		BUS_INTERFACE IPLB = plb_v34_0
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-	END
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-
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-	BEGIN opb_intc
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-		PARAMETER INSTANCE = opb_intc_0
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-		PARAMETER HW_VER = 1.00.c
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-		PARAMETER C_BASEADDR = 0xD1000FC0
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-		PARAMETER C_HIGHADDR = 0xD1000FDF
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-		BUS_INTERFACE SOPB = opb_v20_0
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-	END
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-
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-	BEGIN opb_uart16550
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-		PARAMETER INSTANCE = opb_uart16550_0
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-		PARAMETER HW_VER = 1.00.d
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-		PARAMETER C_BASEADDR = 0xa0000000
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-		PARAMETER C_HIGHADDR = 0xa0001FFF
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-		BUS_INTERFACE SOPB = opb_v20_0
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-	END
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-
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-	BEGIN plb_v34
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-		PARAMETER INSTANCE = plb_v34_0
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-		PARAMETER HW_VER = 1.02.a
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-	END
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-
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-	BEGIN plb_bram_if_cntlr
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-		PARAMETER INSTANCE = plb_bram_if_cntlr_0
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-		PARAMETER HW_VER = 1.00.b
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-		PARAMETER C_BASEADDR = 0xFFFF0000
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-		PARAMETER C_HIGHADDR = 0xFFFFFFFF
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-		BUS_INTERFACE SPLB = plb_v34_0
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-	END
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-
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-	BEGIN plb2opb_bridge
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-		PARAMETER INSTANCE = plb2opb_bridge_0
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-		PARAMETER HW_VER = 1.01.a
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-		PARAMETER C_RNG0_BASEADDR = 0x20000000
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-		PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
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-		PARAMETER C_RNG1_BASEADDR = 0x60000000
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-		PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
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-		PARAMETER C_RNG2_BASEADDR = 0x80000000
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-		PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
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-		PARAMETER C_RNG3_BASEADDR = 0xC0000000
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-		PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
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-		BUS_INTERFACE SPLB = plb_v34_0
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-		BUS_INTERFACE MOPB = opb_v20_0
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-	END
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-
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-   Gives this device tree (some properties removed for clarity):
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-
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-	plb@0 {
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-		#address-cells = <1>;
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-		#size-cells = <1>;
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-		compatible = "xlnx,plb-v34-1.02.a";
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-		device_type = "ibm,plb";
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-		ranges; // 1:1 translation
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-
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-		plb_bram_if_cntrl_0: bram@ffff0000 {
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-			reg = <ffff0000 10000>;
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-		}
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-
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-		opb@20000000 {
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-			#address-cells = <1>;
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-			#size-cells = <1>;
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-			ranges = <20000000 20000000 20000000
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-				  60000000 60000000 20000000
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-				  80000000 80000000 40000000
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-				  c0000000 c0000000 20000000>;
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-
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-			opb_uart16550_0: serial@a0000000 {
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-				reg = <a00000000 2000>;
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-			};
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-
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-			opb_intc_0: interrupt-controller@d1000fc0 {
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-				reg = <d1000fc0 20>;
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-			};
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-		};
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-	};
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-
23289    That covers the general approach to binding xilinx IP cores into the
23390    device tree.  The following are bindings for specific devices:
23491