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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/Documentation/devicetree/bindings/usb/exynos-usb.txt
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@@ -12,13 +12,11 @@
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  - interrupts: interrupt number to the cpu.
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  - clocks: from common clock binding: handle to usb clock.
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  - clock-names: from common clock binding: Shall be "usbhost".
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- - port: if in the SoC there are EHCI phys, they should be listed here.
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-   One phy per port. Each port should have following entries:
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-	- reg: port number on EHCI controller, e.g
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-	       On Exynos5250, port 0 is USB2.0 otg phy
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-			      port 1 is HSIC phy0
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-			      port 2 is HSIC phy1
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-	- phys: from the *Generic PHY* bindings; specifying phy used by port.
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+ - phys: from the *Generic PHY* bindings; array specifying phy(s) used
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+   by the root port.
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+ - phy-names: from the *Generic PHY* bindings; array of the names for
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+   each phy for the root ports, must be a subset of the following:
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+   "host", "hsic0", "hsic1".
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 Optional properties:
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  - samsung,vbus-gpio:  if present, specifies the GPIO that
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@@ -35,12 +33,8 @@
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 		clocks = <&clock 285>;
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 		clock-names = "usbhost";
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-		#address-cells = <1>;
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-		#size-cells = <0>;
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-		port@0 {
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-		    reg = <0>;
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-		    phys = <&usb2phy 1>;
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-		};
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+		phys = <&usb2phy 1>;
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+		phy-names = "host";
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 	};
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 OHCI
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@@ -52,13 +46,11 @@
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  - interrupts: interrupt number to the cpu.
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  - clocks: from common clock binding: handle to usb clock.
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  - clock-names: from common clock binding: Shall be "usbhost".
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- - port: if in the SoC there are OHCI phys, they should be listed here.
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-   One phy per port. Each port should have following entries:
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-	- reg: port number on OHCI controller, e.g
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-	       On Exynos5250, port 0 is USB2.0 otg phy
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-			      port 1 is HSIC phy0
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-			      port 2 is HSIC phy1
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-	- phys: from the *Generic PHY* bindings, specifying phy used by port.
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+ - phys: from the *Generic PHY* bindings; array specifying phy(s) used
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+   by the root port.
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+ - phy-names: from the *Generic PHY* bindings; array of the names for
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+   each phy for the root ports, must be a subset of the following:
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+   "host", "hsic0", "hsic1".
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 Example:
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 	usb@12120000 {
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 		clocks = <&clock 285>;
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 		clock-names = "usbhost";
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-		#address-cells = <1>;
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-		#size-cells = <0>;
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-		port@0 {
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-		    reg = <0>;
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-		    phys = <&usb2phy 1>;
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-		};
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-
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+		phys = <&usb2phy 1>;
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+		phy-names = "host";
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 	};
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 DWC3
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@@ -83,13 +70,22 @@
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  - compatible: should be one of the following -
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 	       "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
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 					    Exynos5250/5420.
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+	       "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on
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+					    Exynos5433.
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 	       "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
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  - #address-cells, #size-cells : should be '1' if the device has sub-nodes
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 				 with 'reg' property.
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  - ranges: allows valid 1:1 translation between child's address space and
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 	   parent's address space
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  - clocks: Clock IDs array as required by the controller.
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- - clock-names: names of clocks correseponding to IDs in the clock property
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+ - clock-names: Names of clocks corresponding to IDs in the clock property.
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+                Following clock names shall be provided for different
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+                compatibles:
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+                 - samsung,exynos5250-dwusb3: "usbdrd30",
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+                 - samsung,exynos5433-dwusb3: "aclk", "susp_clk", "pipe_pclk",
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+                                              "phyclk",
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+                 - samsung,exynos7-dwusb3: "usbdrd30", "usbdrd30_susp_clk",
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+                                           "usbdrd30_axius_clk"
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  - vdd10-supply: 1.0V powr supply
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  - vdd33-supply: 3.0V/3.3V power supply
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