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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt
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@@ -25,18 +25,23 @@
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 ADI registers will make ADI controller registers chaos to lead incorrect results.
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 Then we need one hardware spinlock to synchronize between the multiple subsystems.
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+The new version ADI controller supplies multiple master channels for different
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+subsystem accessing, that means no need to add hardware spinlock to synchronize,
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+thus change the hardware spinlock support to be optional to keep backward
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+compatibility.
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+
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 Required properties:
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 - compatible: Should be "sprd,sc9860-adi".
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 - reg: Offset and length of ADI-SPI controller register space.
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-- hwlocks: Reference to a phandle of a hwlock provider node.
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-- hwlock-names: Reference to hwlock name strings defined in the same order
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-	as the hwlocks, should be "adi".
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 - #address-cells: Number of cells required to define a chip select address
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 	on the ADI-SPI bus. Should be set to 1.
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 - #size-cells: Size of cells required to define a chip select address size
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 	on the ADI-SPI bus. Should be set to 0.
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 Optional properties:
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+- hwlocks: Reference to a phandle of a hwlock provider node.
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+- hwlock-names: Reference to hwlock name strings defined in the same order
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+	as the hwlocks, should be "adi".
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 - sprd,hw-channels: This is an array of channel values up to 49 channels.
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 	The first value specifies the hardware channel id which is used to
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 	transfer data triggered by hardware automatically, and the second