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1 | 1 | Lantiq Synchronous Serial Controller (SSC) SPI master driver |
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2 | 2 | |
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3 | 3 | Required properties: |
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4 | | -- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi" |
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| 4 | +- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi", |
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| 5 | + "intel,lgm-spi" |
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5 | 6 | - #address-cells: see spi-bus.txt |
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6 | 7 | - #size-cells: see spi-bus.txt |
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7 | 8 | - reg: address and length of the spi master registers |
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8 | | -- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt. |
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| 9 | +- interrupts: |
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| 10 | + For compatible "intel,lgm-ssc" - the common interrupt number for |
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| 11 | + all of tx rx & err interrupts. |
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| 12 | + or |
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| 13 | + For rest of the compatibles, should contain the "spi_rx", "spi_tx" and |
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| 14 | + "spi_err" interrupt. |
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9 | 15 | |
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10 | 16 | |
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11 | 17 | Optional properties: |
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.. | .. |
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27 | 33 | num-cs = <6>; |
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28 | 34 | base-cs = <1>; |
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29 | 35 | }; |
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| 36 | + |
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| 37 | +ssc0: spi@e0800000 { |
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| 38 | + compatible = "intel,lgm-spi"; |
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| 39 | + reg = <0xe0800000 0x400>; |
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| 40 | + interrupt-parent = <&ioapic1>; |
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| 41 | + interrupts = <35 1>; |
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| 42 | + #address-cells = <1>; |
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| 43 | + #size-cells = <0>; |
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| 44 | + clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>; |
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| 45 | + clock-names = "freq", "gate"; |
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| 46 | +}; |
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